CN1645597B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN1645597B
CN1645597B CN2004100447191A CN200410044719A CN1645597B CN 1645597 B CN1645597 B CN 1645597B CN 2004100447191 A CN2004100447191 A CN 2004100447191A CN 200410044719 A CN200410044719 A CN 200410044719A CN 1645597 B CN1645597 B CN 1645597B
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semiconductor device
weld bond
rough region
weld
product information
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CN1645597A (zh
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纳谷欣一
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Zhao Tan Jing Co ltd
Aoi Electronics Co Ltd
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Casio Micronics Co Ltd
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Abstract

按照本发明,一种半导体器件具有其上形成有外部连接电极的上表面和与上表面相对并处于镜面态的下表面(10)(#a)。在部分下表面(10)(#a)形成由激光标记打毛的粗糙区(14)。粗糙区(14)包括半导体器件自身的产品信息标记(14)(#a)。产品信息标记(14)(#a)由激光标记印制。确定粗糙区(14)的数量、尺寸、形状和配置位置,以当用光辐照下表面(10)(#a)时,可以从粗糙区(14)和镜面抛光区(12)之间的光反射差读取产品信息。

Description

半导体器件及其制造方法
技术领域
本发明涉及具有例如安装在基板上互连图形部件的半导体器件及其制造方法,尤其涉及具有其上印刷了包括模件名和多个器件自身的产品信息下表面的半导体器件及其制造方法。
背景技术
在封装由Si或GaAs构成的半导体器件中,使用由直接面朝下的倒装芯片连接使得器件紧密和轻重量。封装的半导体器件常常经历测试步骤。为了该目的,如在例如日本专利申请KOKAI公开公报No.2000-114129、2001-85285、8-191038和4-106960中介绍的那样,通过油墨或激光标记在器件的下表面上印刷包括模件名和多个器件自身的产品信息和索引标记、测试标记等。
另一方面,因为这种半导体器件针对减小厚度,通过研磨机通常镜面磨光它的下表面。因为下表面比产品信息和标记光滑,该半导体器件不适合用于通过用于产品信息和标记的光学测试设备来自动测试。作为克服其的手段,如在例如日本专利申请KOKAI公开公报No.2003-318335中介绍的那样,形成光反射率比基板光反射率低的油墨应用部分。作为替换,被镜面磨光并具有产品信息和标记的下表面整个受到故意地表面打毛。用这种工艺,按照产品信息和标记抑制了衬度。因此,通过使用光学测试设备能够读取半导体器件的产品信息或能够识别标记位置。
表面打毛的实例是喷砂、使用磨粒的研磨和使用氢氟酸基混合酸的蚀刻。用这种表面打毛,用物理方法或化学方法不均匀地磨光半导体器件的下表面。这抑制了整个下表面的光泽度并允许通过光学测试设备的自动测试。
按照常规,暂时镜面抛光半导体器件的下表面。此后,在其上形成产品信息标记和索引标记和测试标记。接着,打毛下表面。
但是,当进行表面打毛时,由油墨印刷的标记变得局部不可见。对于由激光标记形成的标记,局部刮削它们的三维图形。由于这个原因,在由光学测试设备的自动测试中的标记识别准确率很低。
为了避免这样,在表面打毛之后再次形成标记。但是,当在粗糙表面上通过油墨印刷标记时,油墨变污,标记变模糊。因此这不能提供实际解决方案。因为它的三维图形,即使激光标记也能在粗糙表面上形成不稳定图形。这也提供了不实际的解决方案。当施加喷砂或使用混合酸的蚀刻时,仅能够打毛必要部分。但是,由于它们需要例如光刻、清洗和漂洗之类的许多附加步骤,这些方法是不利的。
如图1至5所示,半导体器件18包括硅基板60、密封树脂28和多个外部连接端子36。如图1所示,当沿着分割线25分割半导体器件并使其分割成半导体器件16时,预先与切割夹具62粘结的切割带20与下表面粘结。由粘合剂和基膜部件构成常规切割带20。使用丙烯酸树脂作为粘合剂。使用氯乙烯树脂作为基膜材料。
为了从半导体器件18分离半导体器件16,如图2所示,沿着切割线25由专用的切割锯17切开半导体器件18。接着,如图3所示,在由装有加热器64的台66和环68构成的扩展器上放置半导体器件。由加热器64加热切割带20。此后,在图3中通过公知的提升机构向上推进台66和环68,同时固定切割夹具不动。如图3所示,彼此邻近的半导体器件16之间的距离随着切割带20的伸展而增加,从而使半导体器件16彼此分离。如图4所示,在环68和切割夹具62之间切开切割带20并与台66分离。从它的下表面侧用UV射线70辐照切割带20。通过该UV射线辐照削弱了用作切割带20粘合剂的丙烯酸树脂的粘合力。在削弱粘合力之后,如图5所示,从每个半导体器件16的下表面去除切割带20。
在这种情况中,如果形成用作标记的三维图形足够小,那么能够容易地从下表面去除切割带20。当三维图形大到某种程度时,切割带20可以沿着三维图形焊接并难于去除。
发明内容
考虑到上述情况做出了本发明,作为其第一目的本发明提供了一种半导体器件及其制造方法,该半导体器件可以通过图像处理准确地识别在下表面(即使它被镜面磨光)上形成的产品信息标记等,由此通过光学测试设备执行自动测试。
本发明的第二目的是提供一种半导体器件及其制造方法,该半导体器件可以容易地去除与下表面粘结的切割带。
为了实现上述目的,本发明采取以下方法。
按照本发明的第一方案,提供了一种半导体器件,其具有其上形成有外部连接电极的第一表面和与第一表面相对并处于镜面态的第二表面,该器件包括:
形成在部分第二表面由激光标记打毛的粗糙区,由多个焊口形成粗糙区,每个焊口包括凹陷部分和环绕凹陷部分的突出部分,并且邻近焊口之间沿着所述第二表面的分离距离不大于沿着所述第二表面所述焊口的最大宽度,由此形成包含在所述半导体器件的产品信息内单个或多个字符中的每一个字符;
其中当将光照射到所述第二表面上时,在所述第二表面上所述粗糙区与除所述粗糙区之外的区域之间的光反射差是通过调整所述粗糙区的数量、尺寸、形状与配置位置进行调整的;以及
确定每一个所述焊口的数量、尺寸、形状与配置位置,以便在用光照射所述第二表面时,从所述光反射差中读取所述字符。
按照本发明的第二方案,在第一方案的半导体器件中,由多个焊口形成粗糙区,每个焊口包括凹陷部分和环绕凹陷部分的突出部分。凹陷部分的底部和突出部分的顶部之间的差是1到10μm。
按照本发明的第三方案,在第一或第二方案的半导体器件中,粗糙区包括多个焊口,每个焊口包括凹陷部分和环绕凹陷部分的突出部分。邻近焊口不重叠。
按照本发明的第四方案,在第一或第二方案的半导体器件中,粗糙区包括多个焊口,每个焊口包括凹陷部分和环绕凹陷部分的突出部分。邻近焊口之间沿着第二表面的分隔距离不大于沿着第二表面焊口的最大宽度。
按照本发明的第五方案,在第一至第四任一方案的半导体器件中,确定粗糙区的数量、尺寸、形状和配置位置,以当用光辐照第二表面时,可以从粗糙区和除了粗糙区之外的区之间的光反射差读取产品信息。
按照本发明的第六方案,在第一至第五任一方案的半导体器件中,粗糙区包括由激光标记形成的半导体器件自身的索引标记。
按照本发明的第七方案,在制备包括第一至第六任一方案的多个半导体器件的半导体器件组之后,把半导体器件组分割成预定尺寸来制造半导体器件。
根据本发明的第八方案,提供一种半导体器件,其具有其上形成有外部连接电极的第一表面和与第一表面相对并处于镜面态的第二表面,该器件包括:
第一粗糙区,通过激光标记设置多个焊口来打毛所述第二表面的一部分并形成包含在所述半导体器件的产品信息内一个或多个标记而形成,每个焊口包括凹陷部分和环绕凹陷部分的突出部分,并且焊口设置成沿着相邻焊口之间的所述第二表面的距离不大于沿着所述第二表面所述焊口的最大宽度;
第二粗糙区,通过激光标记设置多个焊口来打毛除所述第一粗糙区之外的所述第二表面的一部分而形成,每个焊口包括凹陷部分和环绕凹陷部分的突出部分,所述焊口设置成沿着相邻焊口之间的所述第二表面的距离不大于沿着所述第二表面所述焊口的最大宽度,
其中所述第一粗糙区与第二粗糙区可通过调整所述焊口的数量、尺寸、形状与配置位置而降低所述第二表面上的衬度。
因此,在本发明中,通过采用第一至第八方案的方法,由包括产品信息标记等的粗糙区能够减小下表面的衬度。因此,当用光辐照下表面时,可以从粗糙区和非粗糙区之间的光反射差读取产品信息等。因此,能够执行光学测试设备的有效自动测试。
特别是当采用第二至第四方案的方法时,还能够容易地去除与下表面粘结的切割带。
在以下介绍中将阐述发明的附加目的和优点,从介绍中部分附加目的和优点是明显的,或可以通过发明的实践得知。通过在下文特别指出的手段和组合可以实现和获得发明的目的和优点。
附图说明
与说明书结合并构成说明书一部分的附图现在说明发明的优选实施例,与上面给出的一般性介绍和以下给出的优选实施例的详细介绍一起用作解释发明的原理。
图1是部分常规晶片切割工艺(切割带粘结)的示图;
图2是部分常规晶片切割工艺(半导体晶片切割)的示图;
图3是部分常规晶片切割工艺(扩展)的示图;
图4是部分常规晶片切割工艺(UV辐照)的示图;
图5是部分常规晶片切割工艺(每个半导体器件的拾取)的示图;
图6是示出按照第一实施例半导体器件的下表面实例的平面图;
图7是示出在制造半导体器件方法的步骤(晶片制备)中按照第一实施例半导体器件的实例的纵向剖面图;
图8是示出在制造半导体器件方法的步骤(聚酰亚胺构图)中按照第一实施例半导体器件的实例的纵向剖面图;
图9是示出在制造半导体器件方法的步骤(UBM形成)中按照第一实施例半导体器件的实例的纵向剖面图;
图10是示出在制造半导体器件方法的步骤(光刻胶构图)中按照第一实施例半导体器件的实例的纵向剖面图;
图11是示出在制造半导体器件方法的步骤(再分布)中按照第一实施例半导体器件的实例的纵向剖面图;
图12是示出在制造半导体器件方法的步骤(光刻胶去除)中按照第一实施例半导体器件的实例的纵向剖面图;
图13是示出在制造半导体器件方法的步骤(干膜光刻胶构图等)中按照第一实施例半导体器件的实例的纵向剖面图;
图14是示出在制造半导体器件方法的步骤(柱电极形成)中按照第一实施例半导体器件的实例的纵向剖面图;
图15是示出在制造半导体器件方法的步骤(干膜光刻胶去除)中按照第一实施例半导体器件的实例的纵向剖面图;
图16是示出在制造半导体器件方法的步骤(UBM蚀刻)中按照第一实施例半导体器件的实例的纵向剖面图;
图17是示出在制造半导体器件方法的步骤(密封树脂层形成)中按照第一实施例半导体器件的实例的纵向剖面图;
图18是示出在制造半导体器件方法的步骤(表面抛光)中按照第一实施例半导体器件的实例的纵向剖面图;
图19是示出在制造半导体器件方法的步骤(保护带粘结)中按照第一实施例半导体器件的实例的纵向剖面图;
图20是示出在制造半导体器件方法的步骤(下表面抛光)中按照第一实施例半导体器件的实例的纵向剖面图;
图21是示出在制造半导体器件方法的步骤(外部连接端子形成)中按照第一实施例半导体器件的实例的纵向剖面图;
图22是示出在制造半导体器件方法的步骤(标记)中按照第一实施例半导体器件的实例的纵向剖面图;
图23是示出粗糙区实例的放大平面图;
图24示出成直线形成焊口的平面图和对应平面图的剖面图;
图25是示出粗糙区另一实例的放大平面图;
图26是示出按照第一实施例半导体器件下表面的另一实例的平面图;
图27是示出在制造半导体器件方法的步骤(切割带粘结)中按照第一实施例半导体器件的实例的纵向剖面图;
图28是示出在制造半导体器件方法的步骤(半导体晶片切割)中按照第一实施例半导体器件的实例的纵向剖面图;
图29是示出在制造半导体器件方法的步骤(每个半导体晶片的拾取)中按照第一实施例半导体器件的实例的纵向剖面图;
图30是示出按照第一实施例半导体器件的封装结构实例的纵向剖面图;
图31是示出按照第二实施例半导体器件的封装结构实例的纵向剖面图。
具体实施方式
以下将参照附图介绍进行本发明的最佳方式。
整个附图中如在图1至5中那样相同的参考标号代表相同的部件。
(第一实施例)
图6是示出按照本发明第一实施例半导体器件的下表面实例的平面图。
通过研磨机等镜面磨光按照该实施例半导体器件的下表面10(#a)。此后,在部分下表面上形成由激光标记打毛的粗糙区14。除粗糙区14之外的区是镜面磨光区12。
在粗糙区14形成半导体器件的产品信息标记14(#a)、索引标记或测试标记14(#b)和衬度调节标记14(#c)。
下面将介绍按照该实施例制造半导体器件的方法。
首先,如图7所示,通过常规方法在由硅或GaAs构成的半导体晶片10的有源区(未示出)中形成半导体元件。通过公知方法形成在有源区中与器件连接的电极焊盘13。除了电极焊盘13的表面之外,整个晶片的表面用由PSG、NSG或其组合构成的玻璃质保护膜11覆盖。即,制备仅电极焊盘13暴露到上表面的晶片10。参考标号25代表分割线。最后沿着分割线25切开晶片10以拾取每个半导体器件16。
如图8所示,通过使用例如旋涂的涂敷方法施加大约10μm厚的作为光敏前体的聚酰胺酸。执行前烘加热和脱水聚酰胺酸并使其固化。合成的聚酰亚胺层15的厚度为大约5μm。通过在预定条件下使用预定的玻璃掩模曝光并显影合成的结构,由此构图聚酰亚胺。再次二次硬化聚酰亚胺以使亚胺化反应率增加到90%或更高,由此形成最终的聚酰亚胺层15。
如图9所示,在聚酰亚胺层15的整个表面上形成UBM19。为了形成UBM19,例如,通过使用作为常规方法的溅射的预处理接着形成具有1000至
Figure B2004100447191D00081
(
Figure B2004100447191D00082
是10-8cm)厚的Ti层。随后,形成具有大约4500至厚的Cu层。
如图10所示,通过例如旋涂的涂敷方法施加光敏涂覆光刻胶液体21。进行前烘。通过使用预定玻璃掩模曝光并显影合成结构以构图涂覆光刻胶21。
如图11所示,通过使用例如Ni、Cu或Ag的导电材料和UBM19作为阴极形成再分布层23。在这种情况中,当通过使用例如Cu执行喷射或转动(rack)电解电镀时,厚度为大约5.0μm。
如图12所示,通过使用碱性释放剂去除涂覆光刻胶21。
如图13所示,通过真空或大气压下,层压具有再分布层23的晶片10的表面,层压具有大约100μm厚的光敏干膜光刻胶24。通过使用预定玻璃掩模曝光并显影合成结构来构图干膜光刻胶24,从而在应形成柱电极的部分在再分布层23上形成开口。
如图14所示,通过使用例如Cu和UBM19作为普通阴电极的电解电镀形成柱电极26。柱电极26的厚度为大约70至90μm。
如图15所示,通过使用碱性干膜光刻胶释放剂去除干膜光刻胶24以暴露UBM19。如图16所示,通过使用在大约30℃温度的(硫磺酸+过氧化氢)溶液基或碱基Cu蚀刻剂和通过使用再分布层23作为掩模从表面层,即Cu层,完全去除暴露的UBM19。当完成Cu层去除时,进行清洗和干燥。蚀刻暴露的Ti层。所用的蚀刻剂为Ti蚀刻剂,例如在大约50℃到65℃液体温度的过氧化氢。Ti层浸蘸到蚀刻剂中并去除Ti层。当完成去除时,通过DIW清洗合成结构并干燥。
如图17所示,通过例如转换模或印刷的密封方法施加环氧树脂液体以整个覆盖晶片10,从而完全埋置柱电极26。在惰性气氛或大气中通过使用烘箱或炉子(未示出)把密封树脂28加热到大约120℃到150℃大约60分钟并凝固。
如图18所示,通过CMP(化学机械抛光)抛光晶片10的上表面侧以暴露埋置在密封树脂28中的柱电极26的表面。因此,整平了密封树脂表面29,同时暴露了柱电极26的顶部表面30。同时,密封树脂28的厚度为80到90μm。
如图19所示,通过加热和加压把表面保护带34粘结到抛光的表面32上以防止污染和损伤表面。通过CMP(化学机械抛光)抛光晶片10的下表面10(#a)以把从在最初状态600到750μm的晶片厚度减小到500到400μm。通过该下表面抛光,如图20所示,在晶片10的下表面10(#a)上形成镜面。此外,把在形成外部连接端子之前的半导体器件厚度减小到大约500μm。为了最后把半导体器件的总厚度限制到800μm或更小该表面抛光步骤是必须的。
如图21所示,形成焊球或在暴露的柱电极26上印刷焊膏以提供导电材料形成外部连接端子。加热合成结构以暂时熔化焊料。通过熔化焊料的表面延伸形成具有突出形状的外部连接端子36。在该实例中,由焊料构成外部连接端子36。但是,本发明不限于此,还可以使用其它材料或结构,只要它有导电性。
如图22所示,在形成外部连接端子之后,在专用夹具38上放置晶片10,同时在图22中使外部连接端子36面朝下且晶片下表面10(#a)面朝上。晶片10安装在夹具38上,并设置在激光标记设备(未示出)中。通过使用激光标记设备(例如可用GSI Lumonics Inc.的WH-4100)并把印刷速度设置到500到1000mm/秒和把脉冲率设置到用于YAG激光束L二次谐波的5到15kHz、根据预设程序、在预定半导体器件上的预定位置形成预定信息或标记。例如,当印刷速度设置到1000mm/秒、脉冲率设置到10kHz时,可以在100μm的间距形成焊口40(以下将介绍)。形成由多个焊口40构成的产品信息标记、索引标记或测试标记和衬度调节标记。
接着将详细介绍焊口40的形成。图23是示出其中形成多个焊口40的粗糙区14的放大平面图。如图23所示,通过几乎周期性排列由用激光辐照晶片10的下表面10(#a)形成的多个焊口40形成标记14(#a、#b和#c)。
图24示出成直线形成的焊口40的平面图和对应平面图的剖面图。每个焊口40包括通过用激光辐照熔化下表面10(#a)形成的凹陷部分40(#a)和当在凹陷部分40(#a)周围建立熔化划痕时形成的突出部分40(#b)。在下表面10(#a)上每个焊口40具有几乎圆形的形状。一般在下表面10(#a)中凹陷部分40(#a)的深度A为大约2μm。在下表面10(#a)上突出部分40(#b)的高度B为大约2μm。直径W,即沿着下表面10(#a)焊口40的最大宽度,为大约50μm。
对应凹陷部分40(#a)的深度A和突出部分40(#b)的高度B的表面粗糙度(A+B)很大地影响了下表面10(#a)的衬度。在1μm或更大的表面粗糙度,当用光辐照下表面10(#a)时,促进了漫反射,并且充分地抑制了下表面10(#a)的衬度。但是,当表面粗糙度的值变大时,切割带20焊接到凹陷部分40(#a)并逐渐变得难于去除。从切割带20的去除性观点出发,表面粗糙度优选为10μm。考虑上述观点,在该实施例中,表面粗糙度设置为1到10μm,最好是大约5μm。
参照图23和24,邻近焊口40不重叠。在这种情况下,在焊口40之间形成镜面。
图25是示出粗糙区14另一实例的放大平面图。参照图25,邻近焊口40重叠。为了促进在下表面10(#a)上对光辐照的漫反射和下表面衬度,在粗糙区14中形成尽可能多的焊口40。因此,能够应用这种配置。但是,为了如此高密度形成焊口40,增加激光辐照点数量。因此,粗糙区14的形成是费时的。优选以足够获得最小所需漫反射效果的密度形成焊口40。考虑到上述观点,在该实施例中,在邻近焊口40之间沿着下表面10(#a)的分离距离D设置为等于或小于直径W,即焊口40的最大宽度,优选等于或小于1/2最大宽度,如图24所示。
用粗糙区14,减小了下表面10(#a)的衬度。因此,光学测试设备(未示出)能够通过用光辐照下表面10(#a)从产品信息标记14(#a)或索引标记或测试标记14(#b或#c)识别产品信息。
当光学测试设备能够从产品信息标记14(#a)识别产品信息或识别索引标记或测试标记14(#b或#c)时,不特别限制将在下表面10(#a)上形成的粗糙区14的数量、尺寸、形状和配置位置。如图26所示,当能够通过把产品信息标记14(#a)制得很大从而充分减小下表面10(#a)上的衬度时,可以省略衬度调节标记14(#c)。
如图23和24所示,通过用激光辐照晶片的下表面10(#a)形成了围绕它们的凹陷部分40(#a)和突出部分40(#b)。此外,能够形成具有1到10μm表面粗糙度的焊口40以使邻近焊口40不重叠。
用通过由此形成焊口40形成的粗糙区14,能够容易和可靠地去除切割带20。此外,能够去除切割带20,而不在围绕凹陷部分40(#a)形成的突出部分40(#b)上留下丙烯酸树脂粘合剂作为残留物。
接着,如图27所示,为了沿着分割线25分割晶片10,通过加热加压使切割带20和具有标记14(#a、#b和#c)的晶片下表面10(#a)彼此粘结。切割带20通过在由先前粘结并固定到切割环42的氯乙烯树脂构成的基膜44上形成丙烯酸树脂基粘合剂层46制得切割带20。在切割设备中设置处于这种状态的晶片10。如图28所示,具有外壳17(#a)和外壳17(#b)的公知切割锯关于旋转轴R旋转。用这种工艺,晶片10切成矩阵形状。此后,通过从切割带20侧用射线辐照合成结构削弱丙烯酸树脂的粘合力。接着,如图29所示,拾取切开的半导体器件16。
在上述工艺中,切割之后进行拾取。作为替代,在通过使用已知的扩展方法执行切割之后,可以通过径向扩展切割带20进而分离半导体器件16。
图30示出具有上述标记的半导体器件16的封装结构。经外部连接端子36把半导体器件16焊接到在基板48上形成的电路互连50的预定位置。在基板48上的电路互连50可以具有另一个与半导体器件16不同的电子部件51。由凹陷部分40(#a)和环绕凹陷部分40(#a)的突出部分40(#b)构成上述标记14(#a、#b和#c),其通过激光辐照形成。此外,标记还包括具有1到10μm表面粗糙度的多个焊口40。因此,即使当由光学测试设备测试封装半导体器件16时,也能够准确地识别标记。
下面将介绍按照具有上述布置的该实施例半导体器件的功能。
在按照该实施例的半导体器件16中,通过研磨机等镜面磨光下表面10(#a)。此后,在部分下表面形成由激光标记打毛的粗糙区14。在粗糙区14中,形成例如产品信息标记14(#a)、索引标记或测试标记14(#b)和半导体器件16的衬度调节标记14(#c)之类的标记。通过几乎周期排列由用激光辐照下表面10(#a)形成的多个焊口40形成这些标记。
焊口40的表面粗糙度严重地影响了下表面10(#a)的衬度。在1μm或更大的表面粗糙度,当用光辐照下表面10(#a)时,促进了漫反射并充分地减小了下表面10(#a)的衬度。另一方面,当表面粗糙度的值变大时,切割带20与凹陷部分40(#a)焊接并逐渐变得难于去除。从切割带20去除性观点出发,表面粗糙度优选为10μm。
在该实施例中,焊口40的表面粗糙度设置为1到10μm,优选大约5μm。因此,当用光辐照下表面10(#a)时,促进了漫反射并充分地减小了下表面10(#a)的衬度。此外,还能够容易地去除切割带20。
从减小下表面10(#a)衬度的观点出发,优选在粗糙区14中焊口40的数量密度尽可能高。但是,为了以高密度形成焊口40,增加激光辐照点数量。因此,粗糙区14的形成是费时的。但是,在该实施例中,在邻近焊口40之间沿着下表面10(#a)的分离距离D设置为等于或小于直径,即焊口40的最大宽度,优选等于或小于1/2最大宽度。因此,能够实现最小所需漫反射效果,并能够缩短用激光标记形成粗糙区14所需的时间。
如上所述,在按照该实施例的半导体器件16中,当形成粗糙区14时,如上所述降低了下表面10(#a)的衬度。由于这个原因,当通过光学测试设备用光辐照下表面10(#a)时,从产品信息标记14(#a)能够准确地识别产品信息。此外,还能够准确地识别索引标记或测试标记14(#b)。因此,能够增加光学测试设备执行测试的效率。
当光学测试设备能够从产品信息标记14(#a)识别产品信息或识别索引标记或测试标记14(#b)时,不特别限制将在下表面10(#a)上形成的粗糙区14的数量、尺寸、形状和配置位置。如图26所示,当能够通过把产品信息标记14(#a)制得很大、充分减小下表面10(#a)上的衬度时,可以省略衬度调节标记14(#c)。在这种方法中,能够几乎无约束地灵活形成标记。
以最小所需密度在粗糙区14中形成焊口40。从而,能够缩短由激光标记形成粗糙区14所需的时间。还能够容易地去除切割带20。在该实施例中,已经介绍了WLCSP(晶片级CSP)的实例。但是,本发明不限于此。可以使用在基板表面48和外部连接端子36之间具有另一半导体器件的半导体器件,另一半导体器件例如像GaAs器件的有源元件或像埋置电阻、电容或电感的无源元件。
(第二实施例)
图31是示出按照该实施例半导体器件16的封装结构的纵向剖面图。
在按照该实施例的半导体器件16的封装结构中,在挠性基板52上形成例如Cu层的导电部件,通过铸造、层压或溅射镀由例如环氧聚酰亚胺、聚醚酰亚胺(PET)或液晶聚合物(LCP)塑料膜构成挠性基板52。构图侵蚀涂层,并蚀刻导电部件形成电路互连50。半导体器件16通过倒装芯片焊接经凸点电极54与挠性基板52连接。在挠性基板52中,除了连接焊盘之外的暴露区(未示出)具有由例如抗焊材料构成的表面保护膜(未示出)。通过侧面灌注用例如环氧树脂的密封树脂28填充由挠性基板52和半导体器件16形成的空间。
不仅在晶片下表面10(#a)上而且在构成挠性基板52的塑料膜上和与半导体器件16或电子部件51连接的电路互连50上形成粗糙区14。此外,形成例如像多个封装结构的产品信息标记14(#a)、索引标记或测试标记14(#b)和衬度调节标记14(#c)的标记,其由在第一实施例中介绍的焊口40构成。
如上所述,不仅在晶片下表面10(#a)上而且在挠性基板52上形成粗糙区14。因此,由于能够通过使用激光束识别标记14(#a、#b和#c),能够进行高速处理。此外,由于通过上述标记形成了信息块,能够在非常小的区域写入信息。
由塑料构成的挠性基板52是半透明的并具有高透光度。在光学识别设备中,光穿过挠性基板,由此不可能识别。但是,当使用本发明的标记时,即使使用光学识别设备时也发生光的漫反射。因此,能够获得大量反射光。由于这个原因,能够高速地读取在封装结构上写入的信息。还可以在为了稳定蚀刻电路互连50而形成的虚设互连上或在Cu表面上形成标记,留有Cu表面为了减小挠性基板52的翘曲,即Cu表面不会影响产品的特性和质量。
本领域技术人员将容易想到附加优点和改进。因此,在其较宽方面的发明不限于这里示出和介绍的特定细节和典型实施例。因此,不脱离所附权利要求和其等同限定的一般发明原理的精神和范围可以做出各种改进。

Claims (6)

1.一种半导体器件,其具有其上形成有外部连接电极的第一表面和与第一表面相对并处于镜面态的第二表面,该器件包括
第一粗糙区,通过激光标记设置多个焊口来打毛所述第二表面的一部分并形成包含在所述半导体器件的产品信息内一个或多个标记而形成,每个焊口包括凹陷部分和环绕凹陷部分的突出部分,并且焊口设置成沿着相邻焊口之间的所述第二表面的距离不大于沿着所述第二表面所述焊口的最大宽度;
第二粗糙区,通过激光标记设置多个焊口来打毛除所述第一粗糙区之外的所述第二表面的一部分而形成,每个焊口包括凹陷部分和环绕凹陷部分的突出部分,所述焊口设置成沿着相邻焊口之间的所述第二表面的距离不大于沿着所述第二表面所述焊口的最大宽度,
其中所述第一粗糙区用于识别产品信息,所述第二粗糙区用于与所述第一粗糙区一起通过调整所述焊口的数量、尺寸、形状与配置位置来降低所述第二表面上的衬度。
2.按照权利要求1的器件,其特征在于在多个焊口的每个中,凹陷部分的底部和突出部分的顶部之间的差是1到10μm。
3.按照权利要求1或2的器件,其特征在邻近焊口不重叠。
4.按照权利要求1或2的器件,其特征在于粗糙区包括由激光标记形成的半导体器件自身的索引标记。
5.如权利要求1所述的器件,
其中确定所述焊口的数量、尺寸、形状与配置位置以便在用光照射所述第二表面时读取形成在所述第一粗糙区上的所述一个或多个标记。
6.一种制造方法,其特征在于在制备包括权利要求4的多个半导体器件的半导体器件组之后,把半导体器件组分割成预定尺寸来制造半导体器件。
CN2004100447191A 2004-01-19 2004-05-17 半导体器件及其制造方法 Active CN1645597B (zh)

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Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7830011B2 (en) 2004-03-15 2010-11-09 Yamaha Corporation Semiconductor element and wafer level chip size package therefor
KR101161470B1 (ko) * 2006-05-25 2012-07-02 미쓰비시덴키 가부시키가이샤 회전 전기기기의 고정자
US8217514B2 (en) * 2008-04-07 2012-07-10 Stats Chippac Ltd. Integrated circuit packaging system with warpage control system and method of manufacture thereof
JP2011003828A (ja) * 2009-06-22 2011-01-06 Panasonic Corp 光半導体装置、及びそれを用いた光ピックアップ装置、並びに電子機器
JP2012038838A (ja) 2010-08-05 2012-02-23 Renesas Electronics Corp 半導体パッケージ及びその製造方法
JP5472275B2 (ja) * 2011-12-14 2014-04-16 株式会社村田製作所 エキスパンド装置及び部品の製造方法
DE112014002322T5 (de) * 2013-05-07 2016-04-07 Ps4 Luxco S.A.R.L. Halbleitervorrichtung und Halbleitervorrichtung-Herstellungsverfahren
JP6113019B2 (ja) * 2013-08-07 2017-04-12 株式会社ディスコ ウエーハの分割方法
CN107112250B (zh) * 2014-12-16 2019-11-05 德卡技术股份有限公司 标记半导体封装的方法
US9728508B2 (en) * 2015-09-18 2017-08-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
CN109417045B (zh) * 2016-06-28 2023-06-23 琳得科株式会社 调准夹具、调准方法及转移粘接方法
US20180005916A1 (en) * 2016-06-30 2018-01-04 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
JP6855955B2 (ja) * 2017-06-19 2021-04-07 株式会社Sumco レーザマークの印字方法、レーザマーク付きシリコンウェーハの製造方法
US10535812B2 (en) * 2017-09-04 2020-01-14 Rohm Co., Ltd. Semiconductor device
JP2019066750A (ja) * 2017-10-04 2019-04-25 株式会社ジャパンディスプレイ 表示装置
JP6866884B2 (ja) * 2018-10-04 2021-04-28 カシオ計算機株式会社 ケース、時計、ケースの製造方法及び時計の製造方法
JP6795019B2 (ja) * 2018-10-04 2020-12-02 カシオ計算機株式会社 ケース及び時計
JP7151906B2 (ja) * 2019-09-12 2022-10-12 株式会社村田製作所 電子部品モジュール、および、電子部品モジュールの製造方法
US20210233867A1 (en) * 2020-01-24 2021-07-29 Intel Corporation Keep out zone with hydrophobic surface for integrated circuit (ic) package
CN114121898B (zh) * 2022-01-28 2022-07-08 甬矽电子(宁波)股份有限公司 晶圆级芯片封装结构、封装方法和电子设备

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4522656A (en) * 1983-07-07 1985-06-11 Wacker-Chemitronic Gesellschaft Fur Elektronik-Grundstoffe Mbh Method of making reference surface markings on semiconductor wafers by laser beam
US6218199B1 (en) * 1998-02-20 2001-04-17 Kazuo Sato Silicon substrate with identification data

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60377A (ja) 1983-06-17 1985-01-05 Taiyo Musen Kk 方向探知機の空中線装置
JPH04106960A (ja) 1990-08-27 1992-04-08 Nec Corp Icチップ
JPH08191038A (ja) 1995-01-11 1996-07-23 Kawasaki Steel Corp 半導体基板へのマーキング方法
JPH10106905A (ja) 1996-09-27 1998-04-24 Sanyo Electric Co Ltd 半導体装置
JPH11214299A (ja) 1998-01-27 1999-08-06 Komatsu Ltd ドットマークの読み取り装置と読み取り方法
JP2000114129A (ja) 1998-10-09 2000-04-21 Toshiba Corp 半導体装置及びその製造方法
JP2001068390A (ja) 1999-08-25 2001-03-16 Hitachi Cable Ltd 半導体ウエハ
JP2001085285A (ja) 1999-09-13 2001-03-30 Toshiba Corp 半導体装置及びその製造方法
JP3502800B2 (ja) * 1999-12-15 2004-03-02 新光電気工業株式会社 半導体装置の製造方法
JP3642765B2 (ja) 2002-04-19 2005-04-27 沖電気工業株式会社 半導体装置、その製造方法、及び半導体装置の位置測定方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4522656A (en) * 1983-07-07 1985-06-11 Wacker-Chemitronic Gesellschaft Fur Elektronik-Grundstoffe Mbh Method of making reference surface markings on semiconductor wafers by laser beam
US6218199B1 (en) * 1998-02-20 2001-04-17 Kazuo Sato Silicon substrate with identification data

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
JP特开2001-68390A 2001.03.16

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