TW507200B - Improved programming method for a memory cell - Google Patents

Improved programming method for a memory cell Download PDF

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Publication number
TW507200B
TW507200B TW090106762A TW90106762A TW507200B TW 507200 B TW507200 B TW 507200B TW 090106762 A TW090106762 A TW 090106762A TW 90106762 A TW90106762 A TW 90106762A TW 507200 B TW507200 B TW 507200B
Authority
TW
Taiwan
Prior art keywords
cells
voltage
memory
unselected
group
Prior art date
Application number
TW090106762A
Other languages
English (en)
Inventor
Donald S Gerber
Kent D Hewitt
David M Davies
Jeffrey A Shields
Original Assignee
Microchip Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/617,280 external-priority patent/US6236595B1/en
Application filed by Microchip Tech Inc filed Critical Microchip Tech Inc
Application granted granted Critical
Publication of TW507200B publication Critical patent/TW507200B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
    • G11C2216/28—Floating gate memory programmed by reverse programming, e.g. programmed with negative gate voltage and erased with positive gate voltage or programmed with high source or drain voltage and erased with high gate voltage

Landscapes

  • Non-Volatile Memory (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)

Description

D8 /、、申凊專利範圍 第―電壓提供給該第一群單元的該等位元線； 將—第四電壓提供給該第二井； 第五電塵提供.給該第二群單元的該等位元線； 其中該等第—及第四電壓實質是相同，而且該等第 及第_電壓貫質是相同，而且該第五電壓是從該第一 電壓到該第二電壓的範圍選取。 申咐專利範圍第8項之在一記憶體中寫入一第一群記憶 體單7L之方法，其申該第一電壓是大於該第二電壓。 申請專利範圍第9項之在一記憶體中寫入一第一群記憶 體單元之方法，其中該第一電壓是正電壓。 U，一種消除在一井中形成的記憶體單元之方法，該等單元的 一第一群是耦合到一字線，該等單元的一第二群是耦合到 該字線，該方法包含： 將一第一電壓提供給該字線； 將第二電壓提供給該井； 將選擇的電壓提供給該第一群單元的該等位元線； 經濟部智慧財產局員工消費合作社印製 將該第四電壓提供給該第二群單元的該等位元線； 其中該等第一及第二電麼是不同，該第四電壓是從 該第一電壓到該第二電壓的範圍選取，而且該選取的電 壓是從該等第二及第四電壓選取。 1 2 .如申請專利範圍第1 1項之消除在—記憶體中的一第一群 記憶體單元之方法，其中該第一電壓是小於孩第二電壓。 .'1 3 ·如申請專利範圍第1 2.項之消除在.一記憶體中的一第一群 -26- 507200 A8B8C8D8 六、申請專利範圍 記憶體單元之方法’其中第二電壓是正電壓。 (請先閱讀背面之注音？事項再填寫本頁) ,11^— 訂-------—線¾ 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）
TW090106762A 2000-03-22 2001-03-22 Improved programming method for a memory cell TW507200B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US19122500P 2000-03-22 2000-03-22
US09/617,280 US6236595B1 (en) 2000-07-17 2000-07-17 Programming method for a memory cell

Publications (1)

Publication Number Publication Date
TW507200B true TW507200B (en) 2002-10-21

Family

ID=26886871

Family Applications (1)

Application Number Title Priority Date Filing Date
TW090106762A TW507200B (en) 2000-03-22 2001-03-22 Improved programming method for a memory cell

Country Status (7)

Country Link
EP (1) EP1137012B1 (zh)
JP (1) JP2001319487A (zh)
KR (1) KR100523529B1 (zh)
CN (1) CN1317800A (zh)
AT (1) ATE337602T1 (zh)
DE (1) DE60122412T2 (zh)
TW (1) TW507200B (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6771536B2 (en) 2002-02-27 2004-08-03 Sandisk Corporation Operating techniques for reducing program and read disturbs of a non-volatile memory
US7317116B2 (en) 2004-12-10 2008-01-08 Archer-Daniels-Midland-Company Processes for the preparation and purification of hydroxymethylfuraldehyde and derivatives
CN101091223B (zh) * 2004-12-24 2011-06-08 斯班逊有限公司 施加偏压至储存器件的方法与装置
DE102005004107A1 (de) 2005-01-28 2006-08-17 Infineon Technologies Ag Integrierter Halbleiterspeicher mit einer Anordnung nichtflüchtiger Speicherzellen und Verfahren
TWI449045B (zh) * 2010-07-16 2014-08-11 Yield Microelectronics Corp Low cost electronic erasure can be rewritten read only memory array
CN102376718B (zh) * 2010-08-05 2013-09-11 亿而得微电子股份有限公司 低成本电可擦可编程只读存储器阵列
US8837219B2 (en) 2011-09-30 2014-09-16 Ememory Technology Inc. Method of programming nonvolatile memory
CN103137181B (zh) * 2013-02-25 2017-06-06 上海华虹宏力半导体制造有限公司 存储器、存储阵列的编程方法及电压提供系统
CN110619910B (zh) * 2019-08-30 2021-08-03 长江存储科技有限责任公司 存储器的控制方法、装置、存储介质

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR910004166B1 (ko) * 1988-12-27 1991-06-22 삼성전자주식회사 낸드쎌들을 가지는 전기적으로 소거 및 프로그램 가능한 반도체 메모리장치
KR100206709B1 (ko) * 1996-09-21 1999-07-01 윤종용 멀티비트 불휘발성 반도체 메모리의 셀 어레이의 구조 및 그의 구동방법
KR100232190B1 (ko) * 1996-10-01 1999-12-01 김영환 비휘발성 메모리장치
US5986931A (en) * 1997-01-02 1999-11-16 Caywood; John M. Low voltage single CMOS electrically erasable read-only memory
JP3951443B2 (ja) * 1997-09-02 2007-08-01 ソニー株式会社 不揮発性半導体記憶装置及びその書き込み方法
JP3198998B2 (ja) * 1997-09-11 2001-08-13 日本電気株式会社 半導体不揮発性メモリ
US6300183B1 (en) * 1999-03-19 2001-10-09 Microchip Technology Incorporated Independently programmable memory segments within a PMOS electrically erasable programmable read only memory array achieved by N-well separation and method therefor

Also Published As

Publication number Publication date
DE60122412T2 (de) 2007-05-03
ATE337602T1 (de) 2006-09-15
EP1137012B1 (en) 2006-08-23
KR20010100834A (ko) 2001-11-14
KR100523529B1 (ko) 2005-10-24
JP2001319487A (ja) 2001-11-16
CN1317800A (zh) 2001-10-17
DE60122412D1 (de) 2006-10-05
EP1137012A3 (en) 2003-09-03
EP1137012A2 (en) 2001-09-26

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