DE60122412D1 - Verbessertes Programmierungsverfahren für eine Speicherzelle - Google Patents
Verbessertes Programmierungsverfahren für eine SpeicherzelleInfo
- Publication number
- DE60122412D1 DE60122412D1 DE60122412T DE60122412T DE60122412D1 DE 60122412 D1 DE60122412 D1 DE 60122412D1 DE 60122412 T DE60122412 T DE 60122412T DE 60122412 T DE60122412 T DE 60122412T DE 60122412 D1 DE60122412 D1 DE 60122412D1
- Authority
- DE
- Germany
- Prior art keywords
- cells
- unselected
- memory cell
- programming procedure
- improved programming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 title abstract 4
- 238000002955 isolation Methods 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
- G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
- G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
- G11C2216/28—Floating gate memory programmed by reverse programming, e.g. programmed with negative gate voltage and erased with positive gate voltage or programmed with high source or drain voltage and erased with high gate voltage
Landscapes
- Non-Volatile Memory (AREA)
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US19122500P | 2000-03-22 | 2000-03-22 | |
US191225P | 2000-03-22 | ||
US617280 | 2000-07-17 | ||
US09/617,280 US6236595B1 (en) | 2000-07-17 | 2000-07-17 | Programming method for a memory cell |
Publications (2)
Publication Number | Publication Date |
---|---|
DE60122412D1 true DE60122412D1 (de) | 2006-10-05 |
DE60122412T2 DE60122412T2 (de) | 2007-05-03 |
Family
ID=26886871
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60122412T Expired - Lifetime DE60122412T2 (de) | 2000-03-22 | 2001-03-12 | Verbessertes Programmierungsverfahren für eine Speicherzelle |
Country Status (7)
Country | Link |
---|---|
EP (1) | EP1137012B1 (de) |
JP (1) | JP2001319487A (de) |
KR (1) | KR100523529B1 (de) |
CN (1) | CN1317800A (de) |
AT (1) | ATE337602T1 (de) |
DE (1) | DE60122412T2 (de) |
TW (1) | TW507200B (de) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6771536B2 (en) * | 2002-02-27 | 2004-08-03 | Sandisk Corporation | Operating techniques for reducing program and read disturbs of a non-volatile memory |
US7317116B2 (en) | 2004-12-10 | 2008-01-08 | Archer-Daniels-Midland-Company | Processes for the preparation and purification of hydroxymethylfuraldehyde and derivatives |
EP1830366B1 (de) * | 2004-12-24 | 2011-07-13 | Spansion Japan Limited | Bias-anwendungsverfahren für speicherung und speicherung |
DE102005004107A1 (de) | 2005-01-28 | 2006-08-17 | Infineon Technologies Ag | Integrierter Halbleiterspeicher mit einer Anordnung nichtflüchtiger Speicherzellen und Verfahren |
TWI449045B (zh) * | 2010-07-16 | 2014-08-11 | Yield Microelectronics Corp | Low cost electronic erasure can be rewritten read only memory array |
CN102376718B (zh) * | 2010-08-05 | 2013-09-11 | 亿而得微电子股份有限公司 | 低成本电可擦可编程只读存储器阵列 |
US8837219B2 (en) * | 2011-09-30 | 2014-09-16 | Ememory Technology Inc. | Method of programming nonvolatile memory |
CN103137181B (zh) * | 2013-02-25 | 2017-06-06 | 上海华虹宏力半导体制造有限公司 | 存储器、存储阵列的编程方法及电压提供系统 |
CN110619910B (zh) * | 2019-08-30 | 2021-08-03 | 长江存储科技有限责任公司 | 存储器的控制方法、装置、存储介质 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR910004166B1 (ko) * | 1988-12-27 | 1991-06-22 | 삼성전자주식회사 | 낸드쎌들을 가지는 전기적으로 소거 및 프로그램 가능한 반도체 메모리장치 |
KR100206709B1 (ko) * | 1996-09-21 | 1999-07-01 | 윤종용 | 멀티비트 불휘발성 반도체 메모리의 셀 어레이의 구조 및 그의 구동방법 |
KR100232190B1 (ko) * | 1996-10-01 | 1999-12-01 | 김영환 | 비휘발성 메모리장치 |
US5986931A (en) * | 1997-01-02 | 1999-11-16 | Caywood; John M. | Low voltage single CMOS electrically erasable read-only memory |
JP3951443B2 (ja) * | 1997-09-02 | 2007-08-01 | ソニー株式会社 | 不揮発性半導体記憶装置及びその書き込み方法 |
JP3198998B2 (ja) * | 1997-09-11 | 2001-08-13 | 日本電気株式会社 | 半導体不揮発性メモリ |
US6300183B1 (en) * | 1999-03-19 | 2001-10-09 | Microchip Technology Incorporated | Independently programmable memory segments within a PMOS electrically erasable programmable read only memory array achieved by N-well separation and method therefor |
-
2001
- 2001-03-12 AT AT01106031T patent/ATE337602T1/de not_active IP Right Cessation
- 2001-03-12 EP EP01106031A patent/EP1137012B1/de not_active Expired - Lifetime
- 2001-03-12 DE DE60122412T patent/DE60122412T2/de not_active Expired - Lifetime
- 2001-03-22 CN CN01111740A patent/CN1317800A/zh active Pending
- 2001-03-22 TW TW090106762A patent/TW507200B/zh not_active IP Right Cessation
- 2001-03-22 KR KR10-2001-0014926A patent/KR100523529B1/ko active IP Right Grant
- 2001-03-22 JP JP2001083671A patent/JP2001319487A/ja not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
JP2001319487A (ja) | 2001-11-16 |
KR100523529B1 (ko) | 2005-10-24 |
CN1317800A (zh) | 2001-10-17 |
KR20010100834A (ko) | 2001-11-14 |
TW507200B (en) | 2002-10-21 |
ATE337602T1 (de) | 2006-09-15 |
EP1137012A3 (de) | 2003-09-03 |
EP1137012A2 (de) | 2001-09-26 |
EP1137012B1 (de) | 2006-08-23 |
DE60122412T2 (de) | 2007-05-03 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |