TW498514B - An integrated circuit package - Google Patents

An integrated circuit package Download PDF

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Publication number
TW498514B
TW498514B TW090117908A TW90117908A TW498514B TW 498514 B TW498514 B TW 498514B TW 090117908 A TW090117908 A TW 090117908A TW 90117908 A TW90117908 A TW 90117908A TW 498514 B TW498514 B TW 498514B
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TW
Taiwan
Prior art keywords
integrated circuit
heat sink
conductive
package
patent application
Prior art date
Application number
TW090117908A
Other languages
English (en)
Inventor
Charles Cohn
Original Assignee
Agere Syst Guardian Corp
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Publication date
Application filed by Agere Syst Guardian Corp filed Critical Agere Syst Guardian Corp
Application granted granted Critical
Publication of TW498514B publication Critical patent/TW498514B/zh

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    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

498514 A7 _ ____ B7 五、發明説明（1 ) 發明範缚 本發明係有關積體電路’特別指封裝式的積體電路。 發明背景 傳統上，積體電路封裝提供積體電路晶片與外部導體之 間的電路連接，同時也保護晶片不致受到外界環境的破 壞。一些大型積體電路，例如電信業及其他應用上所採用 的 ASICs (Application Specific Integrated Circuits)可消耗數 瓦的電力。因此，需發展一種其内部積體電路晶片與具有 消散熱量功能之外露表面的熱傳導性金屬或合金導體基材 接觸之具散熱器積體電路封裝。 目前’一種名爲BGA (Ball Grid Array)之封裝在高接腳 數（high lead count)積體電路，例如電信業使用的ASICs， 封裝上受到廣泛的應用。其接腳以踢球矩陣（arrayS 〇f solder balls)的方式呈現。錫球藉由迴銲（s〇ider refl〇w)焊 錫而固定夺基材的塾（pad )上，可提供高密度（high density ) 的緊密（compact)及可信賴 （reliable)之連接 (interconnections )。BGA封裝本體由聚化物，例如聚醯亞 胺（polyimide )或陶資絕緣體（ceramic dielectric body )所構 成。另外’ B G A封裝亦可具有一散熱器，例如以銅或其他 熱傳導金屬/合金所製成的散熱片。 圖3所示爲常見的積體電路Bga封裝示意圖。積體電路 12的封裝1〇具有一熱傳導性散熱器14，通常爲一金屬 層。此金屬通常爲數個薄層或一厚的銅材質散熱塊（slug) -4- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 498514 A7 B7 五、發明説明（2 所構成。積體電路1 2以具熱傳導性之模片黏著媒介（die attach adhesive medium) 13 黏附在散熱器 14 之上。 積體電路的銲墊16經由導電接腳18 ( leads )連接到封裝 基材上由導電層16、20及22所構成的導電路徑。基材具 有類似印刷電路技術上所採用之電介質層2 4、2 6及2 7結 構。在基材的另一面上，具有一其上將配置錫球陣列 30，構成導電路徑的導電層28。導電導通孔（through holes) 31延伸穿過構成基材的電介質層24、26及27，以 提供錫球3 0與積體電路晶片接觸墊（contact pads) 1 6之間 的電流連接（electrical interconnections )。封裝材料32封住 並保護積體電路晶片1 2與銲線（bonding wires ) 1 8。 封裝藉由錫球30熱迴銲（thermal reflow)所形成的球鮮點 (ball bonds )與基材1 〇上各個對應的接觸墊3 6連接，以產 生和主機板3 8之間的連接。此封裝具有一或多個金屬連 接層（one or more levels of metal interconnections)，例如由 16、20及22所形成的向下穴狀結構（cavity down configuration)。在此種結構中，不同的層分別作爲提供電 源（power )、接地（ground )與信號連接（signal connections ) 之用。基材中每增加一層，將增加封裝上的成本。因此， 減少層數是封裝技術上追求的目標。 發明摘要 本發明提供一種將内部積體電路晶片裝置在一導電性散 熱塊上並與之電轉合（electrically coupled)的積體電路封 裝。此導電性散熱塊除了作爲散熱器之外，同時也具有接 -5- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 498514 A7 B7 五、發明説明（3 ) 地功能。如此，可減少額外的導電層以及用來產生電路連 接至（例如）接地端的電鍍導通孔之需求。因此，内部接地 端（internal ground planes ) 6令導電路徑（conductive paths )艮P 可不需被用來互連接地連接（interconnecting ground connections )之電鍍導通孔所切斷（cut off)，也就可以避 免如先前技藝中電路效能降低（electrical performance degradation)之缺點。此外，本發明允許增加更多之信號 (allows more signals to be added )、以及 / 或是減小積體電 路晶片之尺寸，以增進電路效能。上述及下列關於本發明 之説明皆爲示範性（exemplary)描述，而非限定性 (restrictive) 0 圖式之簡單描述 閱讀下列之詳細説明時配合相對應之圖示將有助於了解 本發明之内容。另外，爲了説明上之方便，圖示中許多物 件的尺寸辟任意放大或縮小，而不依照半導體工業實際情 況之比例繪製。圖示包含下列附圖： 圖1爲依據本發明原理之具體實施例中，一積體電路裝 置（mounted)在一積體電路封裝内之示意圖； 圖2a及2b爲依據本發明原理之具體實施例中，積體電 路封裝之導電性散熱塊上視圖； 圖2c爲圖2a中之導電性散熱塊之2a-2a截面示意圖；及 圖3爲依據先前技藝，積體電路晶片裝置於積體電路上 之示意圖。 發明之詳細説明 -6- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 498514 A7 B7 五、發明説明（4 ) 附圖上所標示之類似的數字代表類似之元件。圖1爲依 據本發明原理之具體實施例中，一積體電路晶片裝置在封 裝本體内之示意圖。圖2a及2b爲依據本發明原理之具體 實施例之導電性散熱塊1 1 4之上視圖。積體電路晶片1 1 2 之封裝100具有一可作爲熱傳導（heat spreader)/散熱（heat sink)，以及/或導電物質之導電性散熱塊1 1 4(爲一導電性 物體）。 簡言之，積體電路晶片1 1 2可藉由銲線（wire bonds)或 其他合適之機制，以直接和導電性散熱塊耦合。如此，可 減少額外的導電層（conductive layers )以及用來產生連接到 (例如）接地端之電鍍導通孔連接之需求。因此，内部平面 (internal planes )的導電路徑即不需被用來形成互連接地連 接之電鍍導通孔所切斷；也就可以避免如先前技藝中某些 電路效能降低之缺點。此外，本發明允許增加更多之信 號、以及/或是減小積體電路晶片之尺寸，以增進電路效 能。 導電性散熱塊1 1 4之材質需具有良好的熱傳導以及/或 電流特性，例如包含金屬合金以及銅材質等。導電性散熱 塊114可由一或多層金屬或金屬合金所形成。導電性散熱 塊1 1 4也可由一具有導電物質塗層之熱傳導性材質所構 成。導電性散熱塊1 1 4可包含一低傳導性（reduced conductive)或非導體材質之保護塗層（protective coating) 或外層114b與114d。 舉例而言，假如導電性散熱塊1 1 4由銅所構成，即可在 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 498514 A7 B7 五、發明説明（5 ) 導電性散熱塊1 1 4的表面上產生一氧化銅（c〇pper 〇xide， black oxide)外層U4b及114d。或是只在内側表面114c上 產生氧化銅114d。在第二種作法上，外層11扑可爲（例如） 一電鍍鎳（N i )層。在此兩種作法中的氧化銅可用來增加 積體電路晶片黏著到導電基材時之結合度（b〇nding)。 藉由去除外層114d之某些部份，可以在導電性散熱塊 114心底部形成一接觸區U4.a。此接觸區U4a可用來提供 積體電路晶片1 1 2與導電性散熱塊丨丨4之間的電耦合。接 觸區114a可產生在固定積體電路晶片〗12之區域114c的 一 一或更多邊上。接觸區114a可如圖2a中所示圍 繞住區域114c，或如圖2b中所示將整個區域114c都包含 在範圍内。 接觸區114a可採常用之技藝製作，例如，於產生外層 114bi前先遮罩區域114a。接觸區U4a可包含一或多個額 外層，以作爲積體電路晶片112與接觸區114&之間銲線及 電耦合足用途。這些額外層可爲導電材質，像是金屬及金 屬合金、。例如，在接觸區114&之上先產生一鎳（mckei)層 14〇之後再產生一金層（a layer of gold) 145。各層可採 電鍍方式製作。在電鍍期間，鎳與金將不會黏附到外層 114b之上。因此，不需要另一額外的遮罩層。 積體電路晶片U 2可藉由熱傳導性晶元黏著媒介1 1 3固 定在導電性散熱塊的區域114(：上。導電性散熱塊ιΐ4則詳 接到基材的一個表面。基材具有電介質層124及126。導 電性散熱塊114與基材之黏合材料可包含黏著劑、坪锡或 -8 -
A7 B7 6 五、發明説明（ /、他可提仏導％性散熱塊〗丨4與一或多個導電層之間電耦 口 I材質。在此具體實施例中，導電性散熱塊採用焊錫 150黏附。在此例中，焊錫15〇黏附到導電性散熱塊η# 及導％層116的一區段（segment) 1 5 5 〇 導電性散熱塊1 1 4可固定到基材上以提供導電性散熱塊 114與一或多個錫球13〇之間經由電鍍導通孔之電耦合。 在此具體實施例中，焊錫i 5 〇作爲導電性散熱塊丨丨4與區 段1 5 5足間的電流連接。接著，區段丨5 5則經由導電層 1 1 6和一或多個電鍍導通孔i 3 1而耦合到一或多個錫球 130 〇 積體電路晶片之銲墊117藉由導電線（electrically conductive wires ) 1 1 8連接到封裝基材中各個不同之導電 層116、120及122。這些導電層可用來作爲電源、接地· 端及k號之互連。此外，導電層的數量可依照積體電路晶 片與封裝所^產生之互連數量（number of interconnections )多 寡而增加或減少。 導電線1 1 8也同時銲接到導電性散熱塊丨丨4以提供導電 性散熱塊1 1 4與錫球1 4 0之間經由電鍍導通孔1 3 1之電耦 合。如此可減少額外的導電層以及導電層與導電層之間額 外的電鍍導通孔之需求。因此，内部接地端的導體路徑即 可不需被電鍍導通孔所切斷，也就可以避免如先前技藝中 電路效能降低之缺點。此外，本發明允許增加更多之信號 以及/或是減小積體電路晶片之尺寸，以增進電路效能。 基材之另一表面具有一其上將配置錫球陣列130，構成 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)
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498514 A7 B7 五、發明説明 導電路徑之導電層116。同時也提供一焊錫遮罩136。如 前所述，導電導通孔131延伸穿過構成基材的電介質層 1 2 4及1 2 6，以提供錫球1 3 0與導電層1丨6之間的電流連 接。一環氧化物封裝材料1 3 2封住並保護積體電路晶片 1 1 2與銲線1 1 8。 之後，此封裝可藉由熱迴銲錫球〗3 〇所產生之焊錫而連 接到主機板上各個對應之接觸墊。此處所指的主機板爲 (例如）一印刷電路板。 本發明雖然以參照具體實施例之方式加以説明，但並非 只侷限於這些具體實施例。文後所附之申請專利範圍内容 將包含其他不超出本發明之精神及範圍，技藝上之修改及 具體實施例。 -10- 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐)

Claims (1)

  1. 498514 A8 B8 C8
    1· 一種積體電路封裝 一導電性散熱塊； 一與導電性散熱塊辑合之積體電路晶片；以及 一由積體電路晶片延伸至導電性散熱塊之導電性元 件0 包含 2. 3. 如申請專利範圍第1項之積體電路封裝， 與導電性散熱塊耦合之基材封裝。 如申请專利範圍第2項之積體電路封裝， 裝包含至少一第一導電層，該積體電路晶 第一導電層。 進一步包含一 其中該基材封 片電耦合至該 4.如申請專利範圍第3項之積體電路封裝，其中該基材告 裝包含-第二導電層’該導電性散熱塊電耦合工該第二 導電層。 5. 如申請專利範圍第4項之積體電路封裝，並中咳基材封 裝内之第-導電層與該第二導電層之間爲電隔：狀態。 6. 如申請專利範圍第4項之積體電路封裝，其中該基材封 裝包含至少二個導電層’ 1¾時該積體電路晶片電耦合至 該第三導電層。 7. 如申請專利範圍第2項之積體電路封装，其中該基材封 裝用以裝置在一主機板上。 8·如申請專利範圍第7項之積體電路封裝，其中該基材爲 一電路板。 9.如申請專利範圍第2項之積體電路封裳，其中核基材封 裝具電鍍導通孔，且該導電性散熱塊電轉合至該導通孔 -11- 本紙張尺度適用中國國家標準(CNS) Α4規格(210X297公釐)
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    498514 A B c D 六、申請專利範圍 之至少其中之一。 10. 如申請專利範圍第1項之積體電路封裝，其中該積體電 路晶片同時以機械（mechanically)及電方式搞合至該導 電性散熱塊。 11. 如申請專利範圍第1項之積體電路封裝，其中一外層形 成於該導電性散熱塊之上，該外層具有一開口露出該導 電性散熱塊之一區段，且該積體電路晶片電耦合至該區 段。 12. 如申請專利範圍第1項之積體電路封裝，其中該導電性 散熱塊構成一散熱器。 13. —種積體電路封裝，包含： 一導電性散熱塊； 一與導電性散熱塊電耦合之積體電路晶片；以及 一具複數個導電層之基材封裝，該複數個導電層之至 少其中之一電耦合至該積體電路晶片。 14. 如申請專利範圍第1 3項之積體電路封裝，其中該基材 封裝用以裝置於一主機板上。 15. 如申請專利範圍第1 4項之積體電路封裝，其中該基材 爲一電路板。 16. 如申請專利範圍第1 3項之積體電路封裝，其中該基材 封裝具導通孔，且該導電性散熱塊電耦合至該電鍍導通 孔之至少其中之一。 17. 如申請專利範圍第1 3項之積體電路封裝，其中該積體 電路晶片同時以機械（mechanically)及電方式搞合至該 -12- 本纸張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） A B c D 498514 々、申請專利範圍 導電性散熱塊。 18. 如申請專利範圍第1 3項之積體電路封裝，其中一外層 形成於該導電性散熱塊之上，該外層具有一開口露出該 導電性散熱塊之一區段，且該積體電路電耦合至該區 19. 如申請專利範圍第1 3項之積體電路封裝，其中該導電 性散熱塊構成一散熱器。 -13- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)
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US5894166A (en) 1997-09-17 1999-04-13 Northern Telecom Limited Chip mounting scheme

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JP2002057238A (ja) 2002-02-22
GB0117917D0 (en) 2001-09-12
US6509642B1 (en) 2003-01-21
KR20020010489A (ko) 2002-02-04
KR100675030B1 (ko) 2007-01-29
GB2370687B (en) 2005-03-23
GB2370687A (en) 2002-07-03

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