TW493236B - Method for manufacturing semiconductor devices - Google Patents

Method for manufacturing semiconductor devices Download PDF

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Publication number
TW493236B
TW493236B TW090117741A TW90117741A TW493236B TW 493236 B TW493236 B TW 493236B TW 090117741 A TW090117741 A TW 090117741A TW 90117741 A TW90117741 A TW 90117741A TW 493236 B TW493236 B TW 493236B
Authority
TW
Taiwan
Prior art keywords
adhesive layer
aforementioned
wafer
semiconductor device
manufacturing
Prior art date
Application number
TW090117741A
Other languages
English (en)
Inventor
Tsutomu Mimata
Original Assignee
Shinkawa Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinkawa Kk filed Critical Shinkawa Kk
Application granted granted Critical
Publication of TW493236B publication Critical patent/TW493236B/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
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    • H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H01L2221/68322—Auxiliary support including means facilitating the selective separation of some of a plurality of devices from the auxiliary support
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29005—Structure
    • H01L2224/29007—Layer connector smaller than the underlying bonding area
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    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/3201—Structure
    • H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32014—Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
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    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Dicing (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Description

493236 A7 ______B7 ____ 五、發明說明（/ ) [技術領域] ----------------- (請先閱讀背面之注意事項再填寫本頁) 本發明係關於半導體裝置之製造方法，特別係關於可 實現半導體裝置的小型化和製造步驟的效率化之方法。 [習知技術] 半導體裝置，係藉由在晶圓上形成多數個所望之積體 電路後，將每個積體電路藉由切割晶圓，而形成多數個晶 粒（半導體元件）來製造。積體電路，係藉由在使不純物質 從晶圓的表面到內部擴散之後，在晶圓上設置絕緣膜或導 電膜而形成的。 相對於晶圓之積體電路部分的厚度爲數，晶圓本 身的厚度爲數百// m。像這樣相對於積體電路部分，而大 幅度地將晶圓做厚是爲了加強晶簡的強度，以避免處理時 產生破損。但是，晶圓的厚度越厚，將會成爲半導體裝置 小型化的阻礙。因此，習知是用削薄晶圓或晶粒的背面（背 面硏磨法）之製造方法，來減少晶粒的厚度。而這種背面硏 磨法，若在硏磨後進行切割的話，會使被薄膜化的晶粒容 易產生破損，所以在硏磨之前進行切割的這種方法，也就 是所謂的DBG法(Dicing Before Grinding)是被期待爲一種 能以高良率製造薄型晶粒之技術。 關於這個DBG法的說明，如圖4(a)所示，首先在晶圓 上，於形成有所望電路之電路形成面的表面上（圖中上面) ，利用鑽石刀片等來切削而形成分離用的凹槽39(半切割 步驟）；接著如(b)所示，將其上下翻轉，在圖中下方的電 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 493236 A7 ^____B7___ 五、發明說明（Y ) 路形成面上貼上背面硏磨用膠片40(以下稱爲BG用膠片) ，如（c)所示從在圖中上面的背面以背面硏磨機硏削直到前 述的凹槽39露出爲止，進而再施以硏磨或是化學蝕刻。藉 此，晶圓就被分離成各晶粒43。其次，如(d)所示再將其上 下翻翻轉後貼於晶圓保持膠片45，然後如(e)所示除去BG 用膠片40。最後，如(f)所示利用由頂銷46挑取晶粒43， 然後送至基板或封裝體進行構裝作業。 此外，從晶粒和裝體(或是在將複數個晶粒予以積層之 所謂的疊層方式爲晶粒和晶粒）的黏著步驟之迅速化爲目的 而言，將在兩面形成有黏著層的黏著膠片貼於晶粒的方法 也廣泛地被使用（例如：特開平11 一204720號公報）。 在這個方法中，首先如圖5(a)所示，在被加熱的晶圓 51的非電路形成面之背面側貼上黏著膠片57，另一方面， 將晶圓保持膠片65貼於晶圓環64。另外也可以事先將黏 著膠片57貼在晶圓保持膠片65上，而非貼於晶圓51。接 下來如(b)所示，邊進行晶圓環64的對準，邊將晶圓51貼 上。接著如(c)所示，用切割裝置將晶圓51和黏著膠片57 完全切斷，最後如(d)所示用頂銷66挑取晶粒63。就這樣 藉由黏著膠片57的黏著力可使所形成的晶粒63與基板67 黏著，或是若有需要高密度化時，可將其積層於其他的晶 粒63上後再黏著也可以。 [發明欲解決之課題] 但是，在上述的DBG法中，若是考慮使用黏著膠片的 5 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公釐） ---------------- (請先閱讀背面之注意事項再填寫本頁) -laj. 493236 A7 _B7 _____ 五、發明說明（）） 情形，如圖4(a)乃至(c)的步驟中’既使將每個晶粒43和 BG用膠片40保持成一體的狀態’如(§)所示’把被背面硏 磨過的晶粒43的背面側貼在事先黏著有黏著膠片77之晶 圓保持膠片45的上面，然後如(h)所示，將BG用膠片4〇 除去，就會如⑴所示’形成以頂銷46將其挑起的結果’但 是這個方法，因爲並未對黏著膠片77進行切割（對應晶粒 的形狀而切割），所以無法獲得形成有由黏著膠片77獲得 所構成的黏著層之狀態的各個晶粒43 °因此加上上述之圖 4(a)的半切割步驟，更需要僅將黏著膠片77切割的步驟。 又，如圖4(h)的狀態，也就是對於在背面硏磨後形成 切割狀態的晶粒43來說’在非電路形成面的背面側（圖中 上面側）中，依晶粒43大小所貼的黏著膠片個片（未圖示) ，或是網版藉由網版版印刷在晶粒43的背面側形成由黏著 材料所構成之黏著層的話，可獲得形成有黏著層獲得的狀 態之各個晶粒43。但是在這種情況，由於要對切割後的晶 粒43進行貼附或印刷，因此會降低對各個晶粒43的定位 精度，而且會產生黏著膠片個片或黏著層的偏離或露出的 情況。 爲了獲得黏著層形成之定位精度，在切割爲各個晶粒 43、63之前，也就是背面硏磨前，較佳係能在晶圓31、51 上形成黏著層。可是上述習知的各方法中，都是於晶圓31 ' 51之非形成電路面之背面側形成黏著層的結構’另一方 面’硏磨同樣是在晶圓31、51的背面側進行，所以不管如 何黏著層之形成都是必須在上述之硏磨之後，也就是一定 6 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝 . 493236 A7 -----B7 __ 五、發明說明（矣） ----I---------- (請先閱讀背面之注意事項再填寫本頁) 要在晶圓31、51被切割爲各個晶粒43、63之後進行，結 果造成了無法同時兼顧黏著層之定位精度和藉由DBG法之 半導體裝置小型化的效果。 因此’本發明提供一個能兼顧黏著層之定位精度和半 導體裝置之小型化之方法。 [解決課題之手段] 第1本發明之半導體裝置之製造方法，其特徵在於具 有： 黏著層形成步驟，在晶圓之形成有所望電路的表面上 ’形成切割自晶圓的晶粒和其他構件黏著用的黏著層；及 薄膜化步驟，對從前述表面側分離用的凹槽且形成有 黏著層之前述晶圓，自其背面側實施薄膜化處理直到前述 凹槽露出爲止。 第1本發明，係使從晶圓所切割而成的晶粒和其他構 件黏著的黏著層，形成於晶圓之所望電路所形成的表面上( 黏著層形成步驟）；在前述表面側形成分離用的凹槽，並且 對形成有黏著層之前述晶圓，進行薄膜化處理直到前述凹 槽自晶圓之背面側露出爲止（薄膜化步驟）。。因此於第1 本發明，在切割成各個晶粒之前，也就是在背面硏磨之前 ，便已在晶圓上形成了黏著層，所以可以獲獲得黏著層形 成之定位精度，另一方面，黏著層是形成於晶圓上之所望 電路所形成的表面上，所以可以於非電路形成面之背面側 進行背面硏磨，因此黏著層之定位精度和半導體裝置之小 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 493236 A7 ________B7__ 五、發明說明（《） 型化兩者皆能兼顧。 第2本發明，係如第！本發明之半導體裝置之製造方 法’在前述黏著層形成步驟和前述薄膜化步驟之間，具有 半切割步驟，以形成前述分離用的凹槽。 於第2本發明，在黏著層形成後，進行形成分離用的 凹槽之半切割’然後進行薄膜化處理。因此，在半切割之 際’因爲電路形成面被黏著層所被覆，所以在半切割時不 會有異物附著於電路形成面之憂慮，也就能抑制不良品的 產生。另外，既使對應於各晶粒的黏著層互相連結，在半 切割時就會切斷其連結，因此，可在互相連結之狀態下形 成對應於各晶粒的黏著層，因此能更提高黏著層之定位精 度。 第3本發明，係如第1或第2本發明之半導體裝置之 製造方法’在前述黏著層形成步驟和前述薄膜化步驟之間 ，具有保持步驟，使必須將複數個前述晶粒保持成一體之 保持構件黏著於前述黏著層。 於第3本發明中，在黏著層形成後，使用來將複數個 前述晶粒保持成一體之保持構件黏著於前述黏著層(保持步 驟）’然後進丫了薄Μ化處理。因此在薄膜化處理前後，每個 晶粒保持成一體，具有較佳的處理性。 第4本發明，係如第1至第3本發明中任一之半導體 裝置之製造方法，前述黏著層係被覆於前述表面上除了金 屬突塊以外之部分。 於第4本發明中，由於黏著層係被覆於前述表面上除 8 ^紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐) "' " (請先閱讀背面之注意事項再填寫本頁) 」!· 裝 訂_ 493236 A7 _______B7__ 五、發明說明（& ) 了金屬突塊以外之部分，所以之後可順利地進行對金屬突 塊的打線。 弟5本發明’係如第1至第4本發明中任一之半導體 裝置之製造方法，其中，前述其他構件爲晶粒。 於弟5本發明中’由於述其他構件爲晶粒，因此藉 由晶粒之積層，能使半導體裝置高密度化。 [發明之實施形態] 本發明之實施形態將以由圖1至圖3說明之；在圖 1(a)中，晶圓1的圖中上面側之表面上形成未圖示未圖示 之積體電路。對於這個表面，首先用網版2及橡皮滾3將 黏著劑4a塗上。藉此，形成了（b)之黏著層4。 這個黏著層4是被覆在晶圓上所形成的積體電路部分 上，而且是被覆在除了形成於圖中符號5的位置之金屬突 塊以外的部分。 又，如圖1(d)所示，對金屬突塊5，可在晶粒之內側 及外側雙方形成黏著層4,也可以圍著金屬突塊5的全周 來形成黏著層4。更進一步地，雖未圖示，可使對應於各 晶粒13之黏著層4互相連結。 接下來如圖3(a)所示，用鑽石刀片從晶圓1的表面進 行切削加工，在約晶圓1之厚度的一半爲止形成分離用的 凹槽9(半切割步驟）。藉此，如圖2所示，在晶圓1的表面 上，於形成有多數個積體電路上，分別形成黏著層4和分 離用的凹槽9之狀態。 9 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁)
493236 A7 ____B7________ 五、發明說明（7) 接著，如圖3(b)所示，將晶圓1上下翻轉，於變成在 圖中下方之電路形成面對著BG用膠片10，利用黏著層4 的黏著力將其貼附。 接下來，如圖3(c)所不，利用未圖示之背面硏磨器從 變成在圖中上面的晶圓1之背面側進行硏削，直到凹槽9 露出爲止，進而進行硏磨或化學蝕刻。藉此，將晶圓1分 離成各個晶粒13。 接著，如圖3(d)所示，再將晶圓1上下翻轉後，將其 貼附於黏著有晶圓環14之晶圓保持膠片15，然後將BG 用膠片10除去，使其形成與(e)相同狀態。 最後，如圖3⑴所示，用頂銷16將晶粒13挑取，將 其送往未圖示的基板或封裝體進行構裝作業。被移送的晶 粒13，同圖5(d)，單獨與基板或封裝體等其他構件黏著， 或者積層於其他晶粒13上後予以黏著也可。 如以上所述，在本實施形態中，在晶圓1之形成有所 望電路的表面上，形成切割自晶圓1的晶粒13和其他構件 黏著用的黏著層4(黏著層形成步驟），對從表面側分離用的 凹槽9且形成有黏著層4之晶圓1，自其背面側實施薄膜 化處理直到前述凹槽9露出爲止(薄膜化步驟）。如此之本 實施形態，由於在切割成各個晶粒13之前，即在背面硏磨 之前在晶圓1上形成黏著層4，所以可以獲得黏著層4之 定位精度，另一方面，黏著層4是在晶圓1上之所望積體 電路所形成的表面上形成，所以可以於非電路形成面之背 面側進行背面硏磨，因此黏著層4之定位精度和半導體裝 10 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐) — "~* (請先閱讀背面之注意事項再填寫本頁) 訂* 493236 A7 ____;_ B7____ 五、發明說明（Y ) 置之小型化兩者皆能兼顧。 (請先閱讀背面之注意事項再填寫本頁) 另外，本實施形態中，在黏著層4形成後，進行形成 分離用的凹槽9之半切割，之後再進行薄膜化處理。又， 半切割加工於黏著層4形成前進行也可以，該構成也屬於 本發明之範疇。但是，特別是在本實施形態中，半切割加 工係於黏著層4形成後進行的，所以在半切割進行時，電 路形成面是被黏著層4被覆住的，所以半切割加工進彳了時 ，不會有異物附著於電路形成面上之顧慮，如此便可抑制 不良品的產生。另外，既使對應於晶粒13的黏著層4互相 連結，在半切割加工時就會切斷其連結，因此可在對應於 各晶粒13的黏著層4爲互相連結之狀態下而形成，因此能 更提高黏著層4之定位精度。 另外，本實施形態中，在黏著層4形成後，將作爲保 持構件(將前述複數個晶粒13保持成一體)之BG用膠片10 黏著於黏著層4之後(保持步驟），進行薄膜化處理。因此 ，在薄膜化處理前後，可將每個晶粒13保持成一體，具有 較佳的處理性。 另外，本實施形態中，由於黏著層4係被覆除了前述 在表面上的金屬突塊以外的部分，因此能使之後對金屬突 塊之打線容易進行。 又，在上述之實施形態中，雖是利用黏著劑4a的塗布 而形成黏著層4，但這樣的構成也可用以下方式代替’如 圖1(c)所示，利用覆蓋膠片6及黏著膠片7，將黏著膠片7 轉印，以使黏著膠片7被覆於晶圓1表面上的積體電路所 11 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 493236 A7 五、發明說明（？） 形成的部分上，但不被覆金屬突塊5的部分之構成也可， 或更進一步地用熱可塑性樹脂所形成之膠片或薄片取代黏 著膠片也可，藉由這些構成也可達到上述實施形態之同樣 效果。 一，？'、一 【圖式之簡單說 圖1之(a)至表示本發明之實施形態之黏著層形成 g理1 步驟之截面圖。 圖2係表示以形成黏著層及凹槽後之狀態之晶圓的俯 視圖。 圖3(a)爲半切割步驟、（b)爲利用BG用膠片付貼之保 持步驟、（c)爲利甩背面硏磨等之薄膜化步驟、（d)爲將晶圓 保持膠片貼於晶圓之貼附步驟、（e)爲BG用膠片除去步驟 、⑴爲挑取晶粒之步驟，之截面圖。 圖4(a)至⑴係利用DBG法之習知半導體裝置製造方法 之截面圖。 圖5(a)至(d)係使用黏著膠片之習知41導體裝置製造方 法之截面圖。 【符號之說明】 1、31、51 晶圓 4a 黏著劑 4 黏著層 5 金屬突塊 12 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁)
493236 A7 _ B7 五、發明說明（/ ° ) 6 覆蓋膠片 7、57、77 黏著膠片 9、 39 凹槽 10、 40 BG用膠片 13、 43、63 晶粒 14、 64 晶圓環 15、 45、65 晶圓保持膠片 (請先閱讀背面之注意事項再填寫本頁) 裝 訂·. 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）

Claims (1)

  1. 493236 經濟部智慧財產局員工消費合作社印製 A8 B8 C8 D8 六、申請專利範圍 1·一種半導體裝置之製造方法，其特徵在於具有： 黏著層形成步驟，在晶圓之形成有所望電路的表面上 ，形成切割自晶圓的晶粒和其他構件黏著用的黏著層；及 薄膜化步驟，對從前述表面側分離用的凹槽且形成有 黏著層之前述晶圓，自其背面側實施薄膜化處理直到前述 凹槽露出爲止。 2·如申請專利範圍第1項之半導體裝置之製造方法， 其中，在前述黏著層形成步驟和前述薄膜化步驟之間，具 有半切割步驟，以形成前述分離用的凹槽。 3·如申請專利範圍第1項之半導體裝置之製造方法， 其中，在前述黏著層形成步驟和前述薄膜化步驟之間，具 有保持步驟，使用來將複數個前述晶粒保持成一體之保持 構件黏著於前述黏著層。 4. 如申請專利範圍第2項之半導體裝置之製造方法， 其中，在前述黏著層形成步驟和前述薄膜化步驟之間，具 有保持步驟，使用來將複數個前述晶粒保持成一體之保持 構件黏著於前述黏著層。 5. 如申請專利範圍第1〜4項中任一項之半導體裝置之 製造方法，其中，前述黏著層係被覆於前述表面上除了金 屬突塊以外之部分。 6·如申請專利範圍第1〜4項中任一項之半導體裝置之 製造方法，其中，前述其他構件爲晶粒。 7·如申請專利範圍第5項之半導體裝置之製造方法， 其中，前述其他構件爲晶粒。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ----------------- (請先閱讀背面之注意事項再填寫本頁} 訂：
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