TW492172B - Method for making semiconductor device - Google Patents
Method for making semiconductor device Download PDFInfo
- Publication number
- TW492172B TW492172B TW090109250A TW90109250A TW492172B TW 492172 B TW492172 B TW 492172B TW 090109250 A TW090109250 A TW 090109250A TW 90109250 A TW90109250 A TW 90109250A TW 492172 B TW492172 B TW 492172B
- Authority
- TW
- Taiwan
- Prior art keywords
- semiconductor device
- semiconductor
- substrate
- manufacturing
- adhesive sheet
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 148
- 238000000034 method Methods 0.000 title claims abstract description 40
- 238000004519 manufacturing process Methods 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims description 64
- 235000012431 wafers Nutrition 0.000 claims description 41
- 229920005989 resin Polymers 0.000 claims description 38
- 239000011347 resin Substances 0.000 claims description 38
- 239000000853 adhesive Substances 0.000 claims description 34
- 230000001070 adhesive effect Effects 0.000 claims description 34
- 238000005520 cutting process Methods 0.000 claims description 31
- 238000005259 measurement Methods 0.000 claims description 17
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- 230000002079 cooperative effect Effects 0.000 claims description 8
- 238000013523 data management Methods 0.000 claims description 3
- 238000007726 management method Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 31
- 239000004020 conductor Substances 0.000 description 9
- 230000002950 deficient Effects 0.000 description 8
- 239000000523 sample Substances 0.000 description 8
- 238000001721 transfer moulding Methods 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 238000007789 sealing Methods 0.000 description 5
- 230000001149 cognitive effect Effects 0.000 description 4
- 229910000831 Steel Inorganic materials 0.000 description 3
- 230000000875 corresponding effect Effects 0.000 description 3
- 238000007689 inspection Methods 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 239000010959 steel Substances 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000004804 winding Methods 0.000 description 2
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 1
- 229910052779 Neodymium Inorganic materials 0.000 description 1
- 229910052770 Uranium Inorganic materials 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000013507 mapping Methods 0.000 description 1
- QEFYFXOXNSNQGX-UHFFFAOYSA-N neodymium atom Chemical compound [Nd] QEFYFXOXNSNQGX-UHFFFAOYSA-N 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
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- 239000004575 stone Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- JFALSRSLKYAFGM-UHFFFAOYSA-N uranium(0) Chemical compound [U] JFALSRSLKYAFGM-UHFFFAOYSA-N 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- Dicing (AREA)
Description
^172 ^172 經濟部智慧財產局員工消費合作社印製 A7 —_____B7 ____ — 五、發明說明(1 ) [發明所屬之技術領域] 本發明係有關一種半導體裝置之製造方法,尤指以減 夕¥線、縮小封裝體之外形、減少其安裝面積,可使成本 大幅度降低之半導體裝置之製造方法。 [習知之技術] 於半導體裝置之製造中,將經由晶圓切割(dicing)分離 之半導體晶片,固定於引線框架上,由於模具藉由以模具 之樹知之/主入之傳送模塑法(trasfer molding),密封固定於 引線框架上之半導體晶片後,進行將被密封之半導體晶片 分離到各個半導體裝置之工序。該引線框架是使用長方型 或疋環狀之框架,只要進行一次的封裝工程,可同時封裝 數個半導體裝置。 第15圖係表示形成於晶圓上之半導體晶片的檢查工 序。在此工序中,判定形成於晶圓上每一個半導體晶片之 良與不良。首先,確認晶圓之位置,然後探針14會依晶片 尺寸被分送,與各半導體晶片丨之電極墊接觸。於此狀態 中’將先前已被程式化之輸入信號波形從輸入電極塾輸 入’ 一定之信號波形會從輸出端子輸出,測試器會讀出此 信號波形,判定其良與不良。於此,被判定為不良之半導 體晶片1,會被加標記(marking)在半導體晶片1固定於引 線框架之時,辨視用之照像機會辨視被標記之不良半導體 晶片1,並將其挑除。 第16圖表示傳送模塑工序。於傳送模塑工序中,藉由 晶粒結合及引線搭接,將固定有半導體晶片1之引線框架 本紙張尺度適用中國國家標準(CNS)A4規格⑵Q χ 297公爱)' ----------- 1 312545 -----------I 裝---- (請先閱讀背面之注意事項再填寫本頁) 訂---- Φ 492172 A7 ____BZ__ 五、發明說明(2 ) 2’設置於以上下模具3A、3B所形成之模槽*之内部,於 模槽4内注人環氧樹脂,進行半導體晶片丨之封裝。於施 (請先閱讀背面之注意事項再填寫本頁) 以此傳送模塑工序後,在每一個半導俨 夂作耳干令體日日片1切斷引線框 架2以製造個別之半導體裝置。(例 、彳即㈡本特開平05-1294 73 號)。 此時,如第17圖所示,在模具35的表面上,設置有 多數個模槽4a至4f,及用以注入樹脂的樹脂源$和流道 (runner)6 ’和用以由流道6向各模槽4a至4f注入樹脂之 鬧門7。這些全部為設於模具3B表面的溝。若為長方=之 引線框架,則在一個引線框架上搭載例如1〇個半導體晶片 1,且對應此標準框,設置10個模槽4、1〇個閘門7及ι 條流道6。然後,於模具3表面設置例如2〇個引線框架分 的模槽4。 經濟部智慧財產局員工消費合作社印製 第1 8圖係表示由前述傳送模塑法所製成之半導體穿 置。以晶體管等元件所形成之半導體晶片1係以銲料等之 堪材9,固定安裝於引線框架之島部(island)8上,半導體 曰曰片1之電極塾及導線1 〇係以鋼線1 1相接,半導體晶片 1之周邊部分係由與前述模槽之形狀一致的樹脂12所覆 蓋,而在樹脂12之外部,導出導線端子1〇之前端部分。 繼之’形成於晶圓上之半導體晶片1係以前述之製造 方法’形成個別之半導體裝置,此等半導體裝置之電氣特 性(hfe等級別)係以測試器加以測定判別。此時,如第j 5 圖之說明,在晶圓檢查工序中之晶圓狀態下,對照未正確 測定之項目或是製品規袼,以更嚴密之測定項目,來進行 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 2 312545 u 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明(3 檢查。然後,於此半導體裝置之電氣性特性的測定,判定 工序中所有的半導體皆會朝向一定之方向,半導體裝置會 逐一被檢查。經此工序後,被判定為良品之半導體裝置, 經捲帶(taping)後出貨。 [發明所欲解決的問題] 由以往之傳送模塑法製造個別的半導體裝置之方法, 在其傳送模塑後,由於在各個半導體裝置分離且分散,因 此使各半導體裝置全部朝一定之方向,以個別進行電氣特 性(hfe等級別)之測定。然後,依判定之結果,半導體裝置 會依其特性被分類’然後再依其類別實施捲帶,因此,會 產生費時與費工序之缺點。 此外,依半導體裝置之電氣特性的測定,判定工序所 被判定電氣特性之半導體裝置,如未一次依阶等級加以 ,分而分接時,就必須準備複數個捲帶線。因此,不能簡 單地形成捲▼裝置,不僅產生佔用較多作業空間的缺點, 也產生以多等級判定優良半導體裝置有所限度的缺點。 [解決問題之方法] 本發明係鑑於前述各項缺失而開發者,其特徵在:將 半導體晶片固定在具有複數個搭载部之基板的各搭載部, 以共同之樹脂層I蓋固定於前述各搭載部上之各前述半導 體晶片後,使前述樹脂層抵接且將前述基板貼在黏著薄 板,由於是在貼附於前述黏著薄板之狀態下進行切割及測 定,所以不會在個別之半導體裝置分離,可在以黏著薄板 一體支持的狀態下進行測定。 ‘紙張尺度適用中國國家標準(CNS)A4規格⑵G X 297公爱)— 312545 I n ϋ i-ϋ 1_1 ϋ ·ϋ ϋ a— i ϋ I · ·ϋ H 1 ·ϋ ί an .1 、 n ϋ ϋ ϋ H (請先閱讀背面之注意事項再填寫本頁) 4 492172 A7 經濟部智慧財產局員工消費合作社印製 五、發明說明(4 ) 又,本發明之特徵在··將半導體晶片固定在具有複數 個搭載部之基板的各搭載部上,以共同之樹月旨層覆蓋固定 於前述各搭載部上之各前述半導體晶片後,使前述樹脂層 抵接且將前職板貼在黏㈣板,由於是在貼附於前述^ 著薄板之狀態下進行切割及測定,且將貼附於前述黏著薄 板之半導體裝置,直接收容於輸送帶(career tape)令,所以 到收容於輸送帶為止,不會在個別之半導體裝置分離,可 在以黏著薄板一體支持之狀態下進行作業。 再者,其特徵在:不僅可判別前述各個半導體裝置之 電氣特性之優良與否,而且可以判斷其良品之等級。此外, 形成於前述基板上之全部的半導體以,制形成於前述 基板之位置’電氣特性之等級等作為資料而加以儲存且選 擇性收集於捲帶時所需電氣性特性之半導體裝置,並加以 捲帶。 [發明之實施形態] 以下詳細說明本發明之實施形態。 本發明之第1工序係如第!圖至第3圖所示,準備具 有複數個搭載部之基板。 ^ 首先,如第丨圖所示,準備對應於一個半導體裝置之 搭載部20,以及複數個例如將100個個體以i〇rx ι〇列 配置之大型基板21。此基板21是以陶瓷或是玻璃環氧等 製成之絕緣基板,將基板一片或是數片相疊合,其合計厚 度為200至2150#m時,其板厚即可維持於製造工序中2 機械性強度。 ;裝 (請先閱讀背面之注意事項再填寫本頁) • n n 1 ----訂---- 羲· 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱) 4 312545 濟 部 智 慧 財 產 局 消 費 合 5 五、發明說明(5 ) 基板21上之各搭載部20的表面上’形成有以鎢等金 屬焊油之印刷及金的電解鍍金所成之導電圖案。另外,基 板21之背面側’形成有作為外部連接電極用之電極圖案: 第2圖(A)為形成於基板21表面之導電圖案的俯視 圖’第2圖(B)為基板21的剖視圖。 以虛線所圍之各搭載部2G,例如呈長邊i Gmmx短邊 〇.8_之矩形,將此矩形以20之間隔縱橫配 置。前述之間隔係後述工序中之切割線24。導電圖案在各 ,20内形成島㈣及導線部%,此等圖案在各搭載 :20内皆為同一形狀。島部25為搭載半導體晶片之處, ,電部26為半導體晶片之電極墊與線路相連接之處。從島 部25係有兩條第i連結部27以連續之圖案而延長。此線 之寬度比島部25窄,例如以〇.lmn之寬度而延長。第} 連結部27係越過切割線24而與相鄰之搭載❹的導線部 26連結。從導線部26係有各個第2連結部28在盥第^連 =平行之方向而延伸,越過切割線24與所相鄰之搭 =2〇之導線部24連結。第2連結部以更與圍繞於搭載 # 20群周圍之共通連結部29連結。藉由第^第2連结 部27、28之延伸,可共通電性連接各搭载部2〇之島部μ 此是為了於進行金等電解鍍金時,作為共通 參照第2圖(B),絕緣基板21之各個搭載部2〇上設女 ==貫穿孔3°之内部埋設有嫣等導電材料。而且 _對應各貫穿孔30 ’於其背面側形成外部電極3卜 1本紙張尺度適財關家^^NS)A4規格(21G χ 297公髮^- 312545
I /2 A7 經濟部智慧財產局員工消費合作社印製 五、發明說明(6 ) 第3圖為從背面側觀察基板2 1表示外部電極3丨a至 31d圖案的俯視圖。此等外部電極31a、31b ' 3le、3 $ 從搭栽部20之邊緣後退0 05至0.1mm左右,且各 立之w电 且以各自獨 立圖案而形成。雖然如此,藉由各貫穿孔30與共通連結 ^9作電性連結。藉此,以導電圖案作為_側電極之電二 鍍金法,可於全部的導電圖案上,形成鍛金層。另外,也 ^以線寬較窄之及第2的連結部27、28橫斷切割線 定半=9:Γ2工序係如第4圖所示,於各搭載部上固 牛導體日日片,並進行引線搭接。 7成鍍金之基板21的每—搭載部2G上,對半導體 日日母、進仃晶粒黏接及引線搭接。半導體晶片33係藉由 銀焊油等接黏劑固定於島部2 ; 導體…… 島丨25之表面,且以鋼線34與半 =…電極塾與導線部3一相連接。半導體 日曰片33疋形成有兩極晶體管、動力Μ_Ετ等3端子之 =:。搭載兩極性元件之情況下,連接於島部Μ之外 之外部電二/b'為集電極引線’連接續於各導線部26 之外邛電極31c、31d是為基礎發射電極。 声霜本發明之第3工序係如第5圖所示,以樹脂 =覆盍基板的上方,將固定於各搭载部之各個半導體晶 片’也以共同之樹脂層覆蓋。 如第5圖⑷所示,從移送於基板21±方之配料機 (disPenser)(未圖示),滴下預 / 枓機 m U m 、 之衣乳糸液體樹脂(結合 的何體晶片 Μ氏張尺度朝t _家鮮(^_4祕 6 312545 f靖先閱讀背面<注意事項再填寫本頁} •裝 ϋ I ϋ 一 θ、I ·ϋ ϋ ·ϋ 羲. 7 A7 __B7 五、發明說明(7 Ϊ ι::主基板21上搭載有100個半導體晶片33的情況 體樹r η 晶片33將會全部—起被覆蓋。前述之液 為使用CV576AN(松下電工製)。所滴下之液 =狀由於其黏黏性較高,具有表面張力之故,其表面 繼之,如第5圖(B)所示,將所滴下之樹脂層,施以 100至200度之數小時的熱處理(硬化),使之硬化後,藉由 磨削其彎曲面’使樹脂層35之表面加工成平坦面。磨削是 使用:割裝置’藉由切割板36將樹脂層35表面以高出基 板-定高度的同一之高度加以磨削。在此工序中,將樹脂 層35之膜厚成形為〇3至i 〇mm。平坦面係在將位於至少 最外侧之半導體晶片33分離成個別半導體裝置時,擴張至 其端部以構成規袼化之封裝尺寸樹脂外形。前述之切割板 係準備各種之厚度’而使用較厚之板,經數次反覆之切削, 使全體形成為平坦面。 另外’於硬化所滴下之樹脂層35之前,將平坦之成形 構件推壓於樹脂層3 5之表面,以形成平坦且水平之面,然 後亦可考慮使之硬化之方法。 繼之’本發明之第4工序係如第6圖所示,使樹脂層 35抵接且將基板21貼在黏著薄板5〇。 如第6圖(A)所示,將基板21翻轉,於樹脂層35之表 面上貼附黏著薄板5〇(例如,商品名稱:UV薄板,RINTEC 公司製造)。因在先前之工序_,施以加工使樹脂層之 表面平坦,且相對於基板2 1表面呈水平之面,所以即使貼 ______ ___ 本紙張尺度適用中國國家標準(CNS)A4規格(21〇 X 297公釐) 312545 裝--------訂------ (請先閱讀背面之注意事項再填寫本頁) Φ 492172 A7 ___B7 五、發明說明(8 於樹脂層35側,基板21也不會傾 之精度。 找斜’可維持其水平垂直 如第6圖(B)所示,於不銹鋼 μ (請先閱讀背面之注咅?事項再填寫本頁) 附黏著薄板50之月邊 ,. %狀金屬框51上貼 <周邊,而在黏著薄柘 設有間隔之ό個基板21。 之中央部分貼有 繼之,本發明之第5工序係如第 背面,在每個搭截邻.^ ^ . 圖所不,從基板之 你m部、切割基板與榭 半導體裝置。 曰曰,而为離在各個 如第7圖所示,在每個搭載部 n A八Μ 4 b π 2υ切斷基板及樹脂層 巧板36%由Λ導體裝置。切斷時係使用切割裝置之切 21 ml石著切割線24同時切割樹脂層35及基板 21,形成在每-個搭載部2G所分割之半導 經濟部智慧財產局員工消費合作社印製 工序中,上述切割板36係在到達切割薄板5。之表二 割,罙度切斷。此時,以切割裝置侧能自動認知從基板21 之背面侧也可觀測之對準記號(例如,形成於基板21周邊 部分之貫穿孔或是鍍金層之一部分),以此為位置基準進行 切割。另外’將電極圖案31a、31b、3U、3id或是島部 25,設計成不會與切割板36接觸之模式。這是由於鍍金層 之切斷性較差,因此以防止產生鍍金層之毛邊為目的。^ 此,與切割板36及鍍金層接觸者,只有以電性導通為目的 之第1及第2之連接部27、28。 312545 如第7圖(B)所示,黏著薄板5〇係將周邊貼附於金屬 框51 ’而貼於黏著薄板上之複數個基板21係認識每一條 切割線24 ’再以切割裝置,根據縱方向之各切割線24而 本紙張尺度適用中國國家標準(CNS)A4規格(21〇 X 297公^8 492172 A7 經濟部智慧財產局員工消費合作社印製 五、發明說明(9 ) 分離,然後,使金屬框51旋轉90度,根據模方向之各切 割線24而分離。藉由切割而分離之半導體裝置,仍然是保 持以黏著劑黏於黏著薄板50之狀態,並未個別分散;離'。、 ^繼之,本發明之第6工序為本發明之特徵的工序。如 第8圖(A)、(B)所示,將進行一體支持於黏著薄板⑽之切 割後之各半導體裝置的特性之測試。 如第8圖所示,使探針5〇碰觸將一體支持於黏著薄板 〇之各半導體裝置的基板21露出於背面側的外部電極 至3 1 d,個別測定各半導體裝置之特性參數等,判定其良 與不良及特性別(hfe等級別)。由於基板21 陶^ 或麵環氧等所成之絕緣基板,考量因製造工序中之= 所f成基板大小之參差不齊或是因以黏著薄板5〇支持之 T產生微小之位置偏移情況,檢測出外部電極3 1 a至 位置之偏移,在修正其偏移位置的同時,以探針W對 外部電極31a至31d進行測定。 ^如第8圖(B)所不,金屬框51貼有複數個基板21,由 口在切剎工序之原有狀態,支持個別之半導體裝置,因此 可不需要判別半導體裝置之正反面及外部電極之射極、基 =—集電極集等種類或方向。此測定於每一基板2!上,依 點、/向 行行依序進行,測定至最末端部後回到原 *八再往下行移動。金屬框5 1僅修正一個半導體裝置尺寸 1的位置之同時,往行方向節距式移動,移動至末端時往 方向私動,再往行方向節距式移動,因此相當簡易且能 大量進行。 +四哪標準(CNS)A4規格⑽ 9 312545 ;裝 (請先閱讀背面之注音心事項再填寫本頁) ----訂--- Φ 492172 A7 經濟部智慧財產局員工消費合作社印製 五、發明說明(10 ) 具體而言,如第9圖(A)及(B)所;^ , 乐 ^所不,認知用照像機54 係使半導體裝置40a進入照像機视野53之中心,以進行位 置認知。此時,除複數個半導體装置4〇a,其周邊之半導 體40b、4〇e等也會同時進入照像機視野53内。然而,此 認知用照像機54之鏡頭施有遮罩,使照像機視野'53之中 心只能容有一個半導體裝置的視野。因此,照像機視野Η 可確實捕捉半導體40a,使位置認知之精確度可提升。特 別是’半導體裝置40之尺寸大小’是形成為小而密集所 以位置之認知若稍有偏差’與周邊半導體裝置進行同時測 定時會產生干擾的情況,所以位置認知之精確度非常重 要。 首先’先認知半導體裝置40c之位置,再加以修正位 置後,以探針探測所接鄰之半導體裝置40b、4〇c、4〇d、 4〇e之電極墊,以測定此等半導體裝置之特性。此時,周 邊之半導體裝置4〇b、4〇d、4〇e之位置認知,被視為容許 範圍内之位置偏移而加以省略,只進行特性之測定,所以 有助於生產性之提高。 繼之,於半導體裝置40b、40c、40d、40e之測定中, 進行下一步驟之測定的半導體裝置40a會檢測出之位置認 知有若干之偏移。修正此位置之偏移,對於包括下一個半 導體裝置40a之鄰接其周邊之數個半導體裝置之電極塾, 以探針52探測、測定這些半導體裝置之特性。此作業於i 列反覆進行完畢後,跳過一列,而於下一列進行同樣之作 業。反覆進行此作業,可測定一個基板21上全部半導體裝 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 10 312545 C請先聞讀背面之涑意事頊存填寫本真) 装 訂--- 492172 經 濟 部 智 慧 財 產 局 消 費 合 作 社 印 製 A7 五、發明說明(11 ) 置40之特性。半導體裝置4〇之測定結果儲存於檢測器之 圮憶體中,此測定結果再轉存於磁片裏作為下一工序使 用〇 在此半導體裝置40特性之測定作業中,認知用照像機 54及探針52之位置是被固定的。然後,由於固定半導體 裝置40之金屬,匡51的移動,而進行此作業。於位置認知 作業中’認知i個半導體裝置4〇之電極墊,再從畫像處理 裝置讀取其距目標位置之偏移量,將此偏移部分存入後, 使下一個半導體裝置40移動。 於此,雖說明認知一個半導體裝置之位置,並對鄰接 此=導體裝置之4個半導體裝置進行特性之測定的情況, 但是並不特定於4個,最多可對10個半導體裴置進行特性 測定,而不需位置之認知。 本發明之標位(mopping)工序係與前述半導體裝置⑽ 之特性(hfe等級別)的測定,判定工程同時進行。 如第10圖(A)所示,在金屬框51内6個基板21貼附 於黏著薄板50。然後,!個基板21中,例如有1〇〇個半導 體裝置40,以10rx 10列之縱橫配置,而在標位工序中, 以測試器判定其特性之半導體裝置4〇係位於金屬框Η内 之那一個基板2丨上,然後形成於基板21内之那一個位置 上’其特性應屬於那一個等級,將此作為資料,儲存於測 定器之記憶體_ 〇 另外’於金屬板内,除了 6個基板21貼附黏著薄 板50外,還貼有條碼61。雖準備有複數個金屬框η,伯 本紙張尺度適用中國國家棵準(CNS)A4規袼咖χ 297公^^ --------- 11 3Ϊ2545 丨 II 丨!! ! i !丨丨!訂·!—丨 — (請先閲讀背面之注音?事項再填寫本頁) 492172 A7 B7 五、發明說明(12 ) (請先閱讀背面之注意事項再填寫本頁) 以條碼61分別加以區別。然後,將金屬板5 i内之各基板 21標上號碼,例如上段左端之基板21標為1,下段右端之 基板21標為6。對於形成於基板21内之各個半導體裝置 40也同樣標以號碼,例如上段左端之半導體裝置4〇標為 1,下段右端標為1〇〇。而關於半導體裝置40之特性(hfe 等級別),例如,1為良品且70S hfe<l 10之半導體裝置40, 2為良品且ll〇‘hfe<180之半導體裝置40,3為良品且18〇 -hfe<240之半導體裝置40,4為良品且240$hfe<300之 半導體裝置40, 5、6、7為不良品之半導體裝置4〇等之等 級區別。於此,由於對於不良品之半導體裝置4〇,亦可以 多種等級來判定,因此易於追查其形成不良品之原因。 具體而言,如第11圖所示,將前述之資料製成表儲存 於測試器内。然後在捲帶工程中,利用此資料進行作業。 於本發明之第7工序係如第12圖所示,將以黏著薄板 50 —體支持各個半導體裝置40,直接收容於輸送帶41中。 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 如第12圖(A)所示,以黏著薄板50 一體支持之測定完 畢的各個半導體裝置40,將識別之良品,藉由吸著夾套5 脫離黏著薄板50,收容於輸送帶41之收容孔。 在本發明中,關於將此半導體裝置4〇,直接收容至輸 送帶41之作業,並不是將所有之半導體裝置切以上度特 性(hfe等級別)區別,而是可選擇具有所需要的特性之=導 體裝置並將其收容。如上所述,此方法 乃凌之特徵是利用第11 圖所示之資料,將貼附於黏著薄板50上 工疋牛導體裝置40, 直接收容於輸送帶中。於收容半導體奘署士 本紙張尺度適用中國國家標準(CNS>A4規格(210 X 297公爱) 寸版装置40時,只選擇收 12 312545 492172 A7 五、發明說明(13 ) 集符合顧客需求的特性之半導體裝置4〇加以收集,因此以 一條作業線即可進行捲帶作業,而不會降低其作業效率。 而被判定為不良品之半導體裝置4〇,必然會被留置於黏著 薄板5 0上,因此可直接廢棄。此結果,可省略以往作業中, 處理不良品之多餘作業。 如第12圖(B)所示,金屬框51上貼有複數個基板21, 因為以切割工序之原有狀態,支持個別之半導體裝置4Q, 所以將其收容至輸送帶4丨時,只需將其移動至需要金屬框 5 1之半導體裝置40處即可,以最小限度的移動即可進行, 既間早且可大量進行。 第13圖(A)為本工序所使用之輸送帶之俯視圖、(b) 為AA線剖視圖、(C)為BB線剖視圖。膠帶本體41其膜厚 為〇·5至l.〇mm,寬度為6至15mm,長度為長達數十拉 之帶狀構件,材料為如互楞紙之紙質。膠帶本體Ο中,於 -定之間隙穿設有貫穿孔42。另外,為了將膠帶本體Ο 以一定間隔輸送’而形成有輸送孔43。貫通孔Ο與輸送 孔43是以模具等施以沖裁(Manking)加卫而形成。膠帶本 體4 1之膜厚及貫通孔42 ^ ^ ^ 具大小疋設計為可收容 所應梱包之電子零件4〇。 膠帶本體41之背面側,貼有透明薄膜狀之第一膠帶 =樣穿孔42之底部。膠帶本體41之表㈣,也 同樣貼有透明薄臈狀之第2膠帶45,以塞住 上部。第2膠帶45以側部附近 如垃人钕 强耆冲46與膠帶本體41 ._接〇。弟1膠帶44也與第2膠帶45於间接 W尺度適用中藏標準:CNS)A4規袼⑵。χ2—_ …’的地方與膠 312545 13 4yzi 經濟部智慧財產局員工消費合作社印製 A7
五、發明說明(U f本體41相接合。前述之接合是從薄臈之上部,藉由以具 有對應於接著部46之加熱部之構件,產生熱壓著而進行, 其兩者皆是以引拉薄膜而成為可剝離之狀態的接合。 取後’第14圖表示依前述之卫序所完成之各個半導體 裝置的立體圖。封獎雜夕 裝體之4個側面,是以樹脂層35及基板 21之切斷面所形成’封裝體之上面是以平坦化後之樹腊層 3的表面所形成,封裝體之下面是以絕緣基板μ之背面 側所形成。 此半導體裝置之長χ寬X高例如為1.0mmx〇.6mmx 〇 mm基板21上方覆蓋有〇 5随左右之樹脂層35,以 在封半導體晶片33。半導體晶片33之厚度約為15〇鋒左 右島^ 25與導線部26會從封褒體之端面向後移,所以 -有第1及第2連接部27、28之切斷部分露出於封裝體側 面0 外部電極31a至31d係以〇 2χ 〇.3nm左右之大小配置 於基板21的4個角隅,對於封裝體外形之中心線,以左右 (上下)對稱之圖案而配置。由於此種對稱之配置,很難判 別電極之極性,所以最好於樹脂層35之表面側形成或印刷 凹部,且刻印表示極性之記號。 以鈾述製造方法形成之半導體裝置,因將多數個元件 聚集一起再以樹脂封裝,所以與個別封裝之情況相比,可 減 > 樹脂材料之浪費,有助於材料成本之減低。另外因不 使用引線框架,故與以往之傳送模塑法相比較,可使封裝 體外形大幅縮小。另外,外部連接用之端子形成於基板21 張尺g中國國家標準㈣“規格⑽χ 297公楚) --------1 —|褒-------""訂— (請先閱讀背面之注意事項再填寫本頁) 312545 14 經濟部智慧財產局員工消費合作社印製 4^2172 五、發明說明(I5 ) 之背面’不突出於封裝體之外形,所以也可使裝置之安裝 面積大幅縮小。 另外’於刚述之製造方法,並不是將黏著薄板50貼附 於基板21側’而是貼附於樹脂層35上而進行切割。例如, 於貼附於基板21上之情況下,剝離元件時,黏著薄板50 之黏著劑會附著至電極圖案川至31d的表面。如果在殘 留此種黏著劑之狀態下,將元件投入自動安裝裝置的話, 會有使於安裝時中的電極圖案川至31(1 化之虞。另外’由於電極圖案3…1(1之表面有= 也會產生弊害,根據本發明,藉中將其貼附於樹脂 層3 5可消除前述之弊害。 再者’將黏著薄板5〇貼附於樹脂層 脂層35之表面加工屮u 丁 稽田將树 ,〇91 成水平且平坦面,可維持與將黏著薄板 、附於基板21側時相同的垂直水平精度。 另外,於前述實施例中已說明密封 4個外部電極之例,但例如於密封2個半導體曰 或是密封積體電路之情況,也可以同樣施^曰曰片的情況 [發明之功效] 依據本發明,第1,以樹脂層覆蓋後 貼附於將月邊目上a M '複數個基板 嫌寸於將周邊貼在金屬框之黏著薄板後,從切割 ▼工序,皆以此狀態進行,所以雖然是微小之 但是仍可實現大量生產之半導體裝置的製造方二體構造, 第2,由於在特定測定中,各個半 被記錄於測試器中,所以於收容至輸送帶時^置之資料會 公爱〉 此貝枓 312545 I——------·-裝--------訂---------蠢 (請先閱讀背面之注咅?事項再填寫本頁) 15 492172 經濟部智慧財產局員工消費合作社印製 ⑻為音 (B)為每 A7 五、發明說明Ο6 ) 可以只選擇所需特性之半導妒龄婆 ^ 千導體叙置,並且將其從黏著薄板 上直接收容於輸送帶41中,t τ因此對量產性有相當之助益, 另外,可實現在捲帶工序中 斤〒之機構形成簡單化之半導體奘 置之製造方法。 策 第3,於黏著薄板上形成 主冲半導體裝置之位置, 因其hfe等級與數量都列入資 』貝科管理,所以可實現以最少 之動作即可進行由黏著薄柘μ金4 專坂上直接收各於輸送帶41的作 業之半導體裝置之製造方法。 第4,由於全部半導體驻要 導體裝置之位置與特性皆列為資料 管理且利用於捲帶工序,所 M w 所以可將+導體裝置之特性(hfe 等級別),區分為多種等級,可眚 尬 ,, 了貝現只以一條作業線,將多 等級之半導體裝置依其特性別此交 行陘別收谷至輸送帶,而不會降低 作業效率之半導體裝置之製造方法。 一 第5’不良品之半導體梦著 菔裒置必然會留置於薄板上, 所以可不需加以區分種別,直接廢棄 ^ J貝現縮紐對於不 良品之多餘工序及時間之製造線。 [圖面之簡單說明] 第1圖為說明本發明製造方法的立體圖。 第2圖(A)為說明本發明製造方法的俯視圖 視圖。 第3圖為說明本發明製造方法的俯視圖。 第4圖為說明本發明製造方法的剖視圖。 第5圖(A)為說明本發明製造方法的剖視圖 視圖。 Μ氏張尺度適用中_家標準(CNS)A4規格⑽X 297公爱) 16 312545 -------1 —I 裝—I----丨訂-------丨· (請先閱讀背面之注咅?事項再填寫本頁) 492172 A7 B7 五、發明說明(Π ) 第6圖(A)為說明本發明製造方法 視圖。 的剖視圖、(B)為俯 視圖 第7圖(A)為說明本發明製造方法的剖視圖、(b)為 俯 第8圖(A)為說明本發明製造方法的剖視圖 視圖。 V )為俯第9圖⑷為說明本發明製造方法的俯視圖視圖。 為剖第10圖為說明本發明製造方法的俯視圖。第11圖為說明本發明製造方法的表。 弟12圖(Α)為說明本發明製造方土 。 个I 表仏万法的剖面圖、⑺)為 視圖 俯 視圖第本發明製造方法的俯視圖, 剖 體圖 第14圖⑷為說明本發明製造方法的立體圖、(B)為立 -1 --------訂---------. (請先閱讀背面之注音?事項再填寫本頁) 經 濟 部 智 慧財 產 局 第15圖為用以說明習知例之俯視圖 第16圖為用以說明習知例之刮視圖 第17圖為用以說明習知例之俯視圖 第18圖為用以說明習知例之剖視圖 [元件符號說明] 1 半導體晶片 3 模具 5 樹脂源 本紙張尺度適用中國國$標準(CNS)A4規格(210 X 297 2、31 線框架 4 模槽 6 流道 297 - 17 312545 492172 A7 B7 五、發明說明(18 ) 經濟部智慧財產局員工消費合作社印製 7 閘門 8 > 25 島部 9 堪材 10 導線 11 - 34 鋼線 12 樹脂 20 搭載部 21 基板 24 切割線 26 - 32a ^ 32b 導線部 27 第1連結部 28 第2連結部 29 共通連結部 30 > 42 貫穿孔 31a、31b 、31c 、 31d 外部電極 33 半導體晶片 35 樹脂層 36 切割板 40a ^ 40b ^ 40c ' 40d ' 40e 半導體裝置 41 輸送帶 43 輸送孔 44 膠帶 50 黏著薄板 51 金屬框 52 探針 53 照相機視野 54 認知用照相機 61 條碼 -裝· 訂----- "14 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 18 312545
Claims (1)
- 夂、申請專利範圍 種半導體裝置之製造方法,係將半導體晶片固定在具 有複數個搭載部之基板的各搭載部,以共同之樹脂層覆 蓋固定於前述各搭載部上之各前述半導體晶片後,使前 逑樹脂層抵接且將前述基板貼在黏著薄板,在貼附於前 述黏著薄板之狀態下進行切割及測定,且將貼附於前述 黏著薄板之半導體元件,直接收容於輸送帶,·其特徵在 該半導體裝置之製造方法中,前述半導體元件於測定 後,其各自之位置及特性會列入資料管理,前述半導體 元件會依其特性收容於輸送帶中。 2·如申請專利範圍第1項之半導體裝置之製造方法,其 中,韵述半導體元素係最少以一條輸送線,依其特性收 容於輸送帶中。 3·如申請專利範圍第丨項之半導體裝置之製造方法,其 t,固定前述黏著薄板的周圍之金屬框,各自具有條 碼,以該條碼進行資料管理。 4·如申請專利範圍第1項之半導體裝置之製造方法,其 中’前述黏著薄板上,貼有複數個前述基板,前述半導 體元件之複數資料會被列入管理。 請 先 閱 讀 背 面 之 注 意 I 再 填 寫 本 頁 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 19 312545
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US9937398B1 (en) * | 2017-01-09 | 2018-04-10 | Saver Products, Llc | Golf tee with at least two support surfaces |
US10535812B2 (en) * | 2017-09-04 | 2020-01-14 | Rohm Co., Ltd. | Semiconductor device |
JP7296835B2 (ja) | 2019-09-19 | 2023-06-23 | 株式会社ディスコ | ウェーハの処理方法、及び、チップ測定装置 |
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JP2833111B2 (ja) * | 1989-03-09 | 1998-12-09 | 日立化成工業株式会社 | 回路の接続方法及びそれに用いる接着剤フィルム |
JPH08335653A (ja) * | 1995-04-07 | 1996-12-17 | Nitto Denko Corp | 半導体装置およびその製法並びに上記半導体装置の製造に用いる半導体装置用テープキャリア |
JPH10144741A (ja) * | 1996-11-07 | 1998-05-29 | Rohm Co Ltd | Icチップの性能分類方法および装置 |
JP3813327B2 (ja) * | 1997-09-26 | 2006-08-23 | 三洋電機株式会社 | 半導体装置の製造方法 |
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- 2001-08-02 KR KR1020010046791A patent/KR100662690B1/ko active IP Right Grant
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US6528330B2 (en) | 2003-03-04 |
CN1184677C (zh) | 2005-01-12 |
US20020019066A1 (en) | 2002-02-14 |
KR100662690B1 (ko) | 2007-01-02 |
CN1337737A (zh) | 2002-02-27 |
JP3605009B2 (ja) | 2004-12-22 |
KR20020011909A (ko) | 2002-02-09 |
JP2002050645A (ja) | 2002-02-15 |
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