TW490834B - Improvements in or relating to integrated circuit dies - Google Patents

Improvements in or relating to integrated circuit dies Download PDF

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Publication number
TW490834B
TW490834B TW089111993A TW89111993A TW490834B TW 490834 B TW490834 B TW 490834B TW 089111993 A TW089111993 A TW 089111993A TW 89111993 A TW89111993 A TW 89111993A TW 490834 B TW490834 B TW 490834B
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Taiwan
Prior art keywords
pads
group
integrated circuit
scope
die
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TW089111993A
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English (en)
Inventor
Ross Addinall
Gareth Rhys Davies
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Lucent Technologies Inc
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Priority claimed from EP99306444A external-priority patent/EP1077489A1/en
Application filed by Lucent Technologies Inc filed Critical Lucent Technologies Inc
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Publication of TW490834B publication Critical patent/TW490834B/zh

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    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Semiconductor Integrated Circuits (AREA)

Description

A7 B7 五 經濟部智慧財產局員工消費合作社印製 、發明說明（ 本發明與積體電路晶粒有關。 當積體電路接近製造階段時，通常會製造一種樣本具有 測試與除錯料之㈣導«。於積體電路晶粒上使用傳 統打線技術製作墊之連接點，習慣上，提供一組導電墊至 所有用於測試及除錯用途的打線接點並且至一用於最後生 產時之打線接點副組。然而，在積體電路晶粒被作爲所謂 觸發晶片的情況下，導電塾之間中央_至—中央户斤需的間 隔，或間距，比必要的更大，其中打線是用來造成連接 的。更大的間隔使得具有額外i以作爲測試與除錯之用的 打線事例並不實際，因爲如此大的積體電路晶粒並不經 濟。 根據本發明，一種積體電路包含第一及第二組導電塾以 使外部連接至該積體電路，至少有一介於該第一組所有墊 與其鄰接墊之間或該第一組各蟄之間之第一預設中央—至 -中央間距，及比該第一間距小，至少有一介於該第二組 所有墊與其鄰接墊之間或該第一和第二組墊之間之第二預 設中央-至-中央間距，以及一只外露該第一組墊或外露 該第一與第二組墊之鈍化層。 該第一組墊之區域比該第二組的還大。該第一組每一個 墊的區域與該第一預設中央-至-中央間距適合於該晶粒 的觸發晶片組，且該第二組每一個蟄的區域與該第二預設 中央-至中-央間距適合於該晶粒的打線組。 該第一與第二組墊可置於該晶粒同軸鄰接之一或多個邊 緣。 -4- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 490834 A7 B7 五、發明說明（2 ) 該第一組墊可置於與該晶粒鄰接之一或多個邊緣之兩 列，該兩列之一的該第一組塾與該兩列之外的其它列之該 第一組墊交錯而置。該第二墊可置於該兩列之一。 該第一組墊可與該積體電路内之一組連接點連接，且該 第二組墊可與該積體電路内之另一組連接點連接。 本發明將於附圖以實例描述之，其中： 圖1是本發明一部份積體電路晶粒之橫切圖； 圖2是本發明一邵份積體電路晶粒之橫切圖；及 圖3是本發明一部份積體電路晶粒之平面圖； 在未照尺寸（not to scale)的不同圖裏，相同的參考表示相 同的部件。 參考圖1，一種積體電路晶粒包含圖示於1之多晶矽及 金屬層並組成内建於該積體電路之電路（未不）。沉積於1 之表面的爲第一組導電墊2與第二組導電蟄.3 。導電墊2 與3乃作爲内嵌於該積體電路内之電路與外部端子（未示） 之間的連接點。明顯大於第二組墊3之該一組墊2乃用於 如後述之觸發晶片組，並連接（藉由未示之工具）至電路裏 之一組連接點。提供第二組墊3以連接積體電路上之打 線，例如作爲測試及除錯之用，並且連接（藉由未示之工 具）至電路内之另一组連接點。打線連接點亦可製於該第 一組螯2 ，並且，如所示，所有的螯2及3有一打線連 接。傳統鈍化材質之鈍化層5覆蓋於積體電路晶粒表面並 於墊2與3之上留一未覆蓋區予打線連接點4。介於第一 組墊2與其鄰接墊之間或第一組墊2之間的間隔，或中央 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 請 先 閱 讀 背 Φ 之 注 再 填 本 頁 經濟部智慧財產局員工消費合作社印製 490834 A7
經濟部智慧財產局員工消費合作社印製
至-中央間距，至少需爲觸發晶片組所需之預設値。目 前該間隔爲200微米或250微米並依製造商而定。比所需 還小之間隔會導致製造問題及嚴重的退貨率（rejecti〇n rate)。以打線連接之最小間隔更小且目前爲9〇微米，儘管 目前的接線技術能使間隔小至50微米。因此，介於第二 組塾之塾3與其鄰接墊之間的中央—至—中央間距，或間 隔’不論其爲第一組墊之墊2或第二組墊之墊3，至少必 須等於打線所需之最小間距要求。 圖2表示與圖i所示相同基^的積體電路晶粒，但是， 不若圖1外露作爲打線連接之導電墊之鈍化層5，圖2表 示作爲觸發晶片組之積體電路晶粒。爲此目的，鈍化層6 製於晶粒表面之上並只外露第一組墊之墊2 ，如先前參考 之圖1，該墊之尺寸適合於觸發晶片組。須知鈍化層6外 路墊2 <區域並且比圖1中的打線組還大。每個墊2皆 於其上沉積導電材質之凸塊，如金或焊鍚，藉由熱的應用 導致各別墊2與外部端子(未示)之間的回流與影窝連接。 觸發曰θ片組（技術已廣爲人知，不於此處再加介紹。因爲 純化層6覆^第二組導電塾3之上，提供了每個導電執2 之間或與其鄭接塾之間觸發晶片組所需之最小間隔。若第 一 ^塾（塾3未以純化層6覆蓋，將用到觸發晶片組所需 取J間h，且攻種組（間的問題可能會伴隨著嚴重之組 曰口寿^*退貨率。 了知包含本發明之積體電路晶粒可同時符合觸發晶片組 與打線兩者所需之最小間隔而不使該晶粒之尺寸有任何'， (請先閱讀背面之注意事項再填寫本頁} -I --- ϋ ϋ I n _ . 4
本紙張尺度適用中@ ®^i^(CNS)A4規格⑵0 A7 A7 Lk 經濟部智慧財產局員工消費合作社印製 五、發明說明（4 或任何大巾田之増加。因此，可以只改變一層光罩，即純化 層，而於觸發晶片組製程或傳統的打線組製程使用相用的 晶粒。 本發明不侷限於其同軸墊之應用。例如，只要符合觸發 晶片組及打線所需之最小間隔，便可使用兩列墊。圖3表 示具有兩列墊之部份積體電路晶片之平面圖。如圖i及圖 2，示出兩組墊，第一組包含墊2，與2,，，且第二組包含墊 3居墊2和3’排成一列或鄰接示於圖3之晶粒邊緣之 列。孩墊2"排在另一列或與晶粒邊緣平行之列但進一步 由此延伸。該墊2”可與該第一組墊之其它墊2，交錯排列， 如所示。該第一組墊，墊2,與墊2，，比該第二組墊之墊3, 大，如圖1與2，該較大之墊可用於觸發晶片或打線組， 而該較小之墊3,則預備作爲打線組。如前，每個墊2，及2·· 白以觸發日曰片組所需之最小距離隔離，以虛線箭號線p標 示兩交錯之墊之該距離。每個第二組墊之墊3，皆與其鄰接 墊或墊3本身隔離，不論是第一組或第二組墊，皆爲打線 組所需之最小間距爲之。塾2，與塾2”有減少晶粒週邊的好 處，這些墊是用作打線組，且亦具有其有效間隔，即沿著 該晶粒邊緣量測之間隔，與預期封裝之引線框間隔極爲匹 配的好處。 可知介於圖1，2及3之内墊之間距不需均勻或對稱； 所需者爲每個墊與其鄰接墊之間或墊與墊之間的間距至少 須爲如本例觸發晶片或打線組所需之最小間隔。 本發明允許相同基本之積體電路用於觸發晶片產品。以 _尺度適財_標^^4規格（21G x 297公釐）__ (請先閱讀背面之注意事項再填寫本頁) I · I I-----訂-------- A7 五、發明說明（5 ) 及以权问的接針數製於打線。可製造如此的”雙目的，，晶粒 而不增加其尺寸。實際上，本發明能以最小的額外成本製 作兩個隔離的積體電路晶粒。另外，觸發晶片與打線組選 擇兩者的釦入/輸出路徑特性及晶粒之内部寄生特性實質 上疋相同的。如所體會，本發明允許於生產週期後段選擇 使用觸發晶片或是打線組。 ------------裝— (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 適 度 尺 張 一紙 本 釐 公 97 2 X 10 (2 格 規 A4 S)A N (C 準 標 家

Claims (1)

  1. 490834 A8 B8 C8 D8 - 六、申請專利範圍 (請先閱讀背面之注意事項再填寫本頁) 1. 一種積體電路晶粒，包含第一及第二組導電墊以使外 部連接能接至該積體電路，至少有一介於該第一組之 各墊與其鄰接墊之間或該第一組墊之間之第一預設中 央-至-中央間距，及至少一小於該第一間距之第二 預設中央-至-中央間距，介於該第二組之各墊與其 鄰接墊之間或該第一和第二組墊之間，以及一只外露 該第一組墊之鈍化層，或該第一和第二組之外露墊。 2. 如申請專利範圍第1項之晶粒，其中該第一組墊之區 域比該第二組蟄大。 3. 如申請專利範圍第2項之晶粒，其中該第一組各墊之 區域及該第一預設中央-至-中央間距合適於該晶粒 之觸發晶片，且該第二組各墊之區域及該第二預設中 央-至-中央間距合適於該晶粒之打線組。 4. 如申請專利範圍第1 ，2或3項之晶粒，其中該第一 與第二組墊同軸置於鄰接該粒子之一或多邊緣。 5. 如申請專利範圍第1 ，2或3項之晶粒，其中該第一 組墊置於鄰接該晶粒一或多邊緣之兩列，該兩列中之 一的該第一組塾與該兩列之外的第一組塾交錯放置。 經濟部智慧財產局員工消費合作社印製 6. 如申請專利範圍第5項之晶粒，其中該第二組墊置於 該兩列其中之一。 7. 如申請專利範圍第1 ，2或-3項之晶粒，其中該第一 組墊與一組連接點連接於該積體電路内，且該第二組 墊與另一組連接點連接於該積體電路内。 8. 如申請專利範圍第4項之晶粒，其中該第一組墊與一 -9- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 490834 A8 B8 C8 D8 — 六、申請專利範圍 組連接點連接於該積體電路内，且該第二組墊與另一 組連接點連接於該積體電路内。 9. 如申請專利範圍第5項之晶粒，其中該第一組墊與一 組連接點連接於該積體電路内，且該第二組墊與另一 組連接點連接於該積體電路内。 10. 如申請專利範圍第6項之晶粒，其中該第一組墊與一 組連接點連接於該積體電路内，且該第二組墊與另一 組連接點連接於該積體電路内。 — —------— I --------訂"-------. (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）
TW089111993A 1999-08-17 2000-06-19 Improvements in or relating to integrated circuit dies TW490834B (en)

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EP99306444A EP1077489A1 (en) 1999-08-17 1999-08-17 Integrated circuit die including conductive pads
EP99309842A EP1077490A1 (en) 1999-08-17 1999-12-07 Improvements in or relating to integrated circuit dies

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US7541674B2 (en) 2009-06-02
JP4130295B2 (ja) 2008-08-06
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US20050242431A1 (en) 2005-11-03
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