TW479369B - A process for fabricating integrated circuit devices having thin film transistors - Google Patents
A process for fabricating integrated circuit devices having thin film transistors Download PDFInfo
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- TW479369B TW479369B TW089125762A TW89125762A TW479369B TW 479369 B TW479369 B TW 479369B TW 089125762 A TW089125762 A TW 089125762A TW 89125762 A TW89125762 A TW 89125762A TW 479369 B TW479369 B TW 479369B
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/466—Lateral bottom-gate IGFETs comprising only a single gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78681—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
- H10K71/60—Forming conductive regions or layers, e.g. electrodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
- H10K85/10—Organic polymers or oligomers
- H10K85/111—Organic polymers or oligomers comprising aromatic, heteroaromatic, or aryl chains, e.g. polyaniline, polyphenylene or polyphenylene vinylene
- H10K85/113—Heteroaromatic compounds comprising sulfur or selene, e.g. polythiophene
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Description
五、發明說明(1) ' "" ------ 技術範轉 本發明關於一製造含許多薄膜電晶體(TFTs)及一内聯鲈 構之半導體裝置之製程。 、σ 技藝背景 =膜電晶體(TFTs)甚為知名,且具商業重要性。非晶石夕 ς溥膜電晶體使用於有源矩陣之液晶顯示器中。薄膜電晶 =ί i優點為,在所用材料上及製造技術上,均可以低成 八Τ=τ了儘可能以低成本製造各TFTs之外’以廉價方式製造 3 之積體電路裝置亦甚為理想。此不僅涉及製造tfTs =4身,且涉及操作積體電路之TFTs之内聯結構。準此, 具有TFTs之積體電路之廉價策略為眾 本造具有薄膜電晶體之積體電路之製程。在 構:’至少TFTS之一部份係在第一柔性基體上 積體笔路之内聯結構,至少在第二柔性基體上構 晉。ί 一柔性基體係疊層或接合一起以構成理想半導體裝 電質部TFT未在第一基體上構成(即TF丁閘極,閘極介、 否)、,半導體在第一基體上構成,但TFT源極與汲極則 成(即第一基體上構成之tft之一部份在第二基體上構 一部結構形成之第二基體)。在實施例中,WTFTs之 構i二炎τ一基體上構成,其餘部份之TFTs在第二基體上 T ’ TFTS則由疊層二基體於一起而裝配。
五、發明說明(2) 在TFTs及相關之内聯、纟 、 疊層:構成積體電路。本發明ίU:5:與第二基體 種用途。其特別合乎經濟挑7、,因其為 (如TFT源極,汲極及閉極 L技術挑哉及費時之 而較易之製程(如内聯結構之形成成))二-基體上實施, 施。在二不同基體上構成^,成可提供一 ^基體上實 科上,有較大選擇。本發 ^ =衣程條件與 理;第-部份在第一基體上份之平行處 此平行處理可節省時間。弟一4伤在第二基體上。如. —基體上形成之材料盘任 °理想處理步驟,與已在 體上實施。本發明之其:=相容,處理步驟可在第二基 _圖式簡略說ag 八 可為精於此技藝者所認定。 圖1為在第—基體上形成 上形成之内聯結構之剖面圖。#犋电日日體,及在第二基體 圖2為在一柔性基_ ° 圖。 成之疊層薄膜電晶體之平面 詳細說明 本發明之製程中,含 第-柔性基體上形成。積體兩=電路裝置之第_部份在 性基體上形成。在第二柔性二^1置之第二部份在第二柔 別TFTs與電路外部之裝=恭ς -上形成之基體電路内之個 及第二基體說明,使用三 。雖然本發明主要一第一 基體可提供更大彈性,G U多基體亦屬可行。使用多個 施。 乂夕之步驟在任一基體上實 479369
五、發明說明(3) 在一實施例中,TFTs之所有組成成份(例如:源極,汲 極’閘極介電質及閘極)在第一基體上形成。在第二實施 例中’ TFTs成份之一部份(例如TFT閘極、閘極介電質及半 導體)在第一基體上形成以&TFTs成份之剩餘部份(例如: 源極與汲極)是形成於第二基體上。 本發明中使用之基體為柔性基體。本發明内容中,柔性 基體為有彈性及不脆之基體。因此基體非玻璃或晶態(即 矽)基體。如晶體為彎曲並可製成甚薄(厚度小於丨毫米)為 一優點。如基體能與捲至捲製程相容,則更佳。例如基體 含塑料,如聚酯及聚亞硫銨亦甚佳。塑料基體現用以製 柔性電路,已久為此技藝人士所知,不予詳述。 在塑 知。此 TFTs ° 源與汲 極上形 另一實 基體10 極30區 導體及 姆接觸 料基體 技藝人 同時, 極係在 成,閘 施例中 上形成 在介電 源極25 形成TFTs為習知行為,已為此技蓺 士瞭解,冑許多不同材料及程序;用以开;成 不同之TFT構型亦屬可能。在一實施例中, 塑料基體上形成。一半導體材料在源極與汲 極介電質與閘極在半導體材料頂部形成。在 (圖1),TFT閘極(即金屬或聚合體)15在第一 暂:電材料層20在間極上形成。源極25與沒 盥材f 2〇上形成。一半導體材料35殿積在半 與波極3G之間,俾在二電極間構成良好ίί 金屬45在基體4〇之二側 利用傳統技術以澱積 内聯結構在第二基體40上形成。 及通過基體40中之通路5〇形成圖案 及構成圖案於基體上。
479369 五、發明說明(4) 、許多材料及權宜之計可用以構成本發明2TFTs。有機半 導體材料甚有吸引力’因其與塑料相容,及可以塑料提供 $成本’質輕及柔性裝置。具有傳導率載體機動性,而使 ^可用於薄膜半導體中之有源層之有機材料,曾揭示於美 =專利申請08/ 770,5 35,1 9 9 6年12月20日,由化6心11“^ H出,標題為"製造一有機薄膜電晶體之方法”該申請指定 一本叙明之受托人,並以參可方式併此間。一有機裝置曾 揭示於美國專利申請09/〇87, 2〇 1 , 1 998年5月29日,由 Z h e^i a η B a 〇提出,標題為”以有機光放射二極體單片統合 之4膜,私晶體”,其指定與本受托人,並以參考方式併入 此間。’、201申請中揭示一光放射二極體(LED)具有一有機 層為有源層,及一電晶體具有一有機層作為半導體層,盆 中之LED與電晶體係單片統合。 /、 無機半導體材料亦適用於本發明製程中。適於澱積於塑 料基體^之無機半導體材料之例,如多晶矽,其以非晶石夕 道化氣澱積)’再經閃光退火變為多晶⑪。其他無機半 ”材料之例為,非晶石夕,砸化録,石夕化鎘及蹄。半導體 +二ί ί二f或?—型,視構成之裝置而定。以CM0S(互補 -導體)裝置言,η-型與p_型半導體材料均可使用。 安:電子裝置之有機材料之研究,已擴展而涵蓋圖 术構成方法,其採取材料易於處理之優點。例#,輻射可 ㈣使光敏有機材料構成圖案’如IWy,(:.】.,發表於 4?3) 108 ^0998), 全聚合物積體電路π。非本^十丨 芦先餘刻方法提供一在成本及彈性
479369 五、發明說明(5) 製造半導體裝置之優點。此種技術包括油墨噴射印刷及螢 幕印刷’该技術層揭示於由Z · B a 〇等人所著之π以印刷技 術製造之南性能塑料電晶體π ,發表於C h e m · M a t e r之卷 9 ’頁1 2 9 9 [ 1 9 9 7 ]。此等技術適用於製造任務,其可提供 約35 μ m - 100 /zm或更高之清晰度。 為製造裝置具有小於35从m之特徵,需要高清晰度之技 術。於石夕基體上印製圖案之技術,已知有利用平面彈性體 沖壓法’並具有尺寸約1 〇 # m —8〇 # m之特徵,(Kumar,a. 等人所著之’'具有微米至公分大小之金特性,可由沖壓與 彈性體沖壓結合,及八11^1!61;1^〇1,油墨,及化學蝕刻法構 成”,)發表於APPL· LETT·,卷 63,2 0 0 2 頁[1 993 ]。此種 許多應用上需要之臨界尺寸(電晶體溝道長度)為低於1〇 # 1^。另一獲得高清晰度裝置之製造策略已於最近揭示。 此策略包含組合之微模造/螢刷技術方法,即,此方法组 合一高清晰度技術(毛細中微模製),以限定臨界特徵及建 方法(螢幕印刷),以供裝置之其他元件之圖 Ϊ 二二_R〇ger,J·,等人所著之非光姓刻製造具有微 較以往之盆#韭以此方法,有機電晶體可製成其溝道長為 提供-赶過大夕^刻方法之長度,小5◦倍(2,),因而 权仏起過大多應用需求之清晰度。 亦ii=ii:TTFFTTs:f 術並非獨有。其他技術表 另機1FTs之製造方法。 利用有機半導體材料受到缺乏一種相容性之限制,即,
五、發明說明(6) _ 蝕刻劑為強氧化媒介令:1如,在金屬電極上構成圖案之 發明計劃在各別基體上其;有體材料不相容。但本 劑,其係用以構成裝置之ί::(=理:…刻劑及溶 元件(有機半導體儿件(裝置電極)與裝置之另一 之二基體之製程區八相t不相容材料間之接觸,以正確 金屬㈣劑對免:=1以構成接觸之 觸,以有機半導體在:體3乂^刻劑與半導體之接 第二基體上構#。基體構成而避免。金屬接點在 不接觸有機半導體1要用:將金屬構成圖案之蝕刻劑永 導體槿:二 吉·,本發明之至程可在利用有機半 导體構成TFTs上之限制,得以減輕。 巾有我丰 -T:Tf第置一及及内第聯—结構形成後,第-基體與第二基體疊層 連接-起。可利,壓力,黏膠或其組合方式 利用導電黏劑導;2商購之轉。結果, 用以接合1-基體上之接= 選擇广成機械連接。二基體連接一起之方式為:設計 t發明已以實施例方式說明,其中 :f體’係與内聯結構形成其上之第二基體=上之第 認為適:ί4少!要第一基體與第二基體之叠層亦被 如^ 此種方法上之彈性為本發明之一值 ,° -實施例中,閘極’閘極介電f,及=:導
第9頁 479369 五、發明說明(7) 體層在第一基體上形成。TJ? 則在第二基體上形成。此二義::,與源極及汲極接點, 在第二實施例中,間 土體於疋疊層一起。 層在第一基體上形成。= Z質,及TFTs之半導體 上形成。内聯在苐三基體上極與汲極接點在第二基體 起。 /成,三個基體於是疊層一 在第三實施例中,閘極 “ 之源極與汲極接點,在第一 "包貝,半導體層及TFTs 體上形成。此外,内聯亦在^體^形成,内聯則在第二基. 是疊層一起。 基體上形成。三個基體於 在第四實施例中,閘極介恭 一基體上形成。TFT裝置之閑%極貝盘及TFT裝置之半導體在第 上形成。TFT裝置之源及汲極點某内聯裝置在第二基體 上形成。此等基體於是疊層〜起。’及内聯在第三個基體 在第五實施例中,閘極介 形成。内聯在第二基體上形成:::;接點在第二基體上 與沒極接點,在第一基體上形::體層及抓之源極 二基體上形成。更多内聯在第;:τ上%之;;極與内聯在第 於是疊層一起。 —土體上形成。此三個基體 上 -ί:i各實施例中,不論在有内聯電路之基體中,或在 。卜基體中,最後成中需要之其他電子裴置亦存在其 /、他電子裝置包括被動組件如電阻器,電感器,電容 479369 五、發明說明(8) 器,及無線組件中使用之天線。其他例包括顯示元件陣 列,如光射二極體,電泳顯示元件,及聚合體擴散液晶顯 示元件。其他例包括AC電照明裝置,鐵電液晶裝置及偵感 器等。此等最後成品中,在第一基體上形成之TFT,用以 驅動内聯基體,或所有基體均以疊層連接之其他基體中之 其他裝置。如隶後成品為一彳貞感器(即一具有光敏或化學 敏感材料)’基體及其他材料須加以選擇,以方便傳送刺 激源(即光或化學)。 在一 fc例實施例中,苓考圖2,一金層(厚度約丨〇 〇 nm) 澱積於一柔性亞硫銨基體上。利用傳統之鈦或鉻使金與基 體相黏合。金層11 〇利用傳統之光刻,以限定在原金層上 打成之一光阻材料層上(未示出)之圖案。光阻材料層中之 圖案,利用傳統蝕刻被轉移至金層之下。有圖案之金層為 裝置(T F T )之閘電極。 "电材料1 2 0之一層(亞硫氨,玻璃樹脂或苯環丁酮 (CYCLOTENE®,DOW化學公司之商標)),利用傳統方法(旋 轉塗層或自溶液模鑄)於有圖案之金層11〇。介電層12〇之 厚度為0 · 5 A m。其次,形成源極及汲極1 3 0及1 4 0。此等電 極為導體金屬(金),導電聚合體(聚苯銨),或導電螢幕可 印油墨。許多傳統手段(如螢幕印刷,經陰罩真空蒸發, 傳統敷層金屬化隨後以金數屬光刻及蝕刻),亦被用以作 為此等電極圖案構成之適當方法。源極及汲極1 3 0及1 4 0以 相當大之内聯墊丨5〇及丨6〇構成。此等墊可方便使源極,汲 極與第二基體上之源極與内聯結構之對齊與内聯。内聯基
第11頁 479369
體IΪ供圖2中分立元件與其他最後產品間之良好内聯。 二=成圖2中之裝置之構成,半導體材料層(二乙氨 =二土)1 70澱積在源極130及汲極1 40附近並與其接觸。半 f體及電極材料須加以選擇,以提供良好之歐姆接觸。能 提七、良好接觸之電極材料包括破基導電油墨,導電聚合 體,金或鍍金金屬。此階段時,基體100疊層於内聯基體 本發明製程之一優點為,至少FETS之一部份及内聯, 用平行處理順序,設計及製造分開。在二或更多基體上形 成可使每一基體之處理條件最佳。例如,在基體丨〇〇上形/ ^薄膜FETs,需要圖案構成技術,其可提供小至一微/之 斗寸性(分隔源極及汲極之距離)。對比下,基體1 〇 〇上之 ,FE丁連接之内聯結構之特性則不夠佳(在5〇 —25〇 範圍)。結果,所選擇之製造特殊基體之方法甚為適合。 即,較貴及費時之製造第一基體特性之方法,不 造第二基體。 灯用於衣 自此實施例可獲得另一優點,實施例中之裝置在一 體上形成,及内聯結構在第二基體上形成。因為内士二
獨立製造,在第一基體上之裝置陣列可以不同方式内^ (其提供裝置以不同功能)。 P 在另一實施例中,TFT以下列製程製造。第一基體 mylar®(mylar為杜邦公司之商標)基體,其上有導恭= 線。導電條為聚合體基導體’如含碳油墨。第二基1體'或 ITO(銦錫氧化物)塗層之Mylar,其上有5〇〇 nm厚 二 X < ώ硫
479369 五、發明說明(ίο) ' 氨閘極介電質。Regioregular聚(3 —乙四酸基)係自氯仿溶 液鑄造’成為IT0塗層之MYLAR®基體,其上形成亞硫氨閘 極介電層。此一基體再壓縮一起。聚合體基導體之導電條 之功此為,源極及沒極,亞硫氨為閘極介電質。I τ 〇為閘 極,聚四酸基為半導體。 、 在另一例中,第一基體由形成TFT裝置之閘極及閘極 點而製備。聚合體介電材料(亞硫氨)實加在基體區。例 如/介電質印刷在閘極上。有機半導體材料利用溶解鑄造 或蒸發,加在基體上。適當之有機半導體包括 k
Regi〇regular聚(乙四酸基),α,〇—乙二—α六赛吩及五 赛吩,戊省,銅過氟苯二甲藍素,及Ν,Ν,—雙(1Η,1Η〜五氟 辛基1鎳-1,4, 5, 8-四酸基二硫亞氨。第二基體以鎳"膠層" 及金薄膜,層。十六烷硫石蠟油圖案在金上構成,未以9硫
石蠟油覆蓋之金屬,以水溶性含氧⑶以“町供金用) L H2S04/、H2 02 /H3P04/NiS04(供鎳用)。其餘金屬圖案,包括源 極與汲極,與第一基體疊層完成一或多個FETs,及形成 關之内聯。 微述之第一基體與第二基體間之處理步驟之分配,可使 呢米尺寸之溝道長度,及理想頂部接點之幾何結構(包括 ^,與及極接點墊,其較實際之源極及汲極大許多)即可 ^侍。,如,在第二基體金屬中蝕刻圖案之試劑,可能化 ^ t使第一基體上之半導體退化。將製程在基體間分開, :W可使用’且可避免試劑與半導體間之接觸。此外,如 一類金屬與氟化有機半導體不黏接。將二基體之製程分
479369 五、發明說明(11) 開,疊層分離問題可避免。 另一例中,閘極,介電材料及半導體在一基體上形成, 導體碳圖案在第二基體上形成。二基體疊層一起以構成一 - 工作裝置。 上述之說明用以說明本發明之申請專利範圍之特例。但 其不會限制本發明。精於此技藝人士可瞭解,除所提供之 特例外,製成方法之廣泛範圍,將在本發明範圍之内。
第14頁 479369 圖式簡單說明
第15頁
Claims (1)
- 479369 六、申請專利範圍 1. 一種積體電路製造之製程包含: 在第一柔性基體上構成至少薄膜電晶體之一部份; 在第二柔性基體上構成一内聯結構; 將第一柔性基體與第二柔性基體疊層一起,因此將薄 膜電晶體與内聯結構成電内聯。 2. 如申請專利範圍第1項之製程,其申之薄膜電晶體包 含一閘極’閘極介電質’一半導體’ 一源極及一沒極。 3. 如申請專利範圍第2項之製程,其中之全部薄膜電晶 體係在第一體上形成。 4. 如申請專利範圍第2項之製程,其中之薄膜裝置之閘 極 > 閘極介電質’半導體’係在第一基體上形成,薄膜裝 置之源極及汲極在第二基體上形成。 5. 如申請專利範圍第4項之製程,其中之半導體係有機 半導體。 6. 如申請專利範圍第4項之製程,其中之半導體為一無 機半導體。
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KR20010097351A (ko) * | 2000-04-21 | 2001-11-08 | 구자홍 | 액티브 구동 유기 전계발광소자 제조방법 |
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JP4505036B2 (ja) | 2010-07-14 |
JP2001230421A (ja) | 2001-08-24 |
US6197663B1 (en) | 2001-03-06 |
JP4358430B2 (ja) | 2009-11-04 |
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