TW449881B - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- TW449881B TW449881B TW089103071A TW89103071A TW449881B TW 449881 B TW449881 B TW 449881B TW 089103071 A TW089103071 A TW 089103071A TW 89103071 A TW89103071 A TW 89103071A TW 449881 B TW449881 B TW 449881B
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Description
經濟部智慧財產局員工消費合作社印製 4 49 88» A7 _B7_ 五、發明說明(I ) 〔發明領域〕 本發明係有關半導體裝置,尤其有關配線基板與半導 體元件間之樹脂密封層之生產力高之半導體裝置° 〔相關技術之說明 習知|因應半導體裝置之小型化及薄型化之要求,進 行半導體晶片(裸晶片)之浮片晶片(flip Chip )連接》 浮片晶片連接,係將半導體晶片對於配線基板面朝下( face down )(將電極終端區域(bump )形成面朝下)搭載 ,安裝於電極終端區域之金,銲錫等之球狀之突起電極( 以下,稱爲凸塊(bump )),押壓於配線基板之連接終端 區域加以加熱,將銲錫等回銲(reflow )接合之方法,較 線結合(wire bonding)之連接相較,優於封裝密度。 像這樣實施浮片晶片連接之半導體裝置,係起因於矽 等半導體晶片與配線基板(例如,玻璃布環氧樹脂浸滲基 板)之熱膨脹率之不同之應力|會施加於半導體晶片與配 線基板之接合手段之凸塊,所以具有會損及接合部可靠性 之問題。 因此,結束銲錫等回銲之後,如第9圖所示,在半導 體晶片1 1與配線基板1 2之間隙部,將如摻混塡充材( filler )之環氧樹脂之液狀樹脂材料1 3利用毛細管作用加 以注入,塡充,進行稱爲向下塡充(under fill )之樹脂密 封層之形成。藉此樹脂密封層,不僅可緩和此配線基板 1 2與半導體晶片1 1間之熱膨脹率差異起因之熱應力, 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -4- --,---------裝--------訂----------線! (請先閱讀背面之注意事項再填寫本頁) A7 4 49 8 8 1 ____B7_ 五、發明說明?) 並且,進行浮片晶片連接部之補強及機械性保護。按’圖 中符號1 1 a ,係半導體晶片1 1之電極終端區域’ 1 2 a係表示配線基板1 2之配線層及連接終端區域’ 1 4係表示銲錫凸塊。符號1 5係朝下塡充用之液狀樹脂 材料1 3滴落,供給所用之分配器(despenser)。 然而,於習知之半導體裝置,係相當於銲錫凸塊1 4 高度之半導體晶片1 1與配線基板1 2間隙之大小(尺寸 ),爲與銲錫凸塊14之配設(連接)節距無關,因設定 有滿足連接製程或可靠性之要求,所以,花費於液狀樹脂 材料1 3之注入,塡充作業之許多時間。尤其,半導體晶 片1 1大小(面積)大,並且銲錫凸塊1 4之配設節距 2 5 0 /zm以下之精細裝置,到塡充結束爲止具有需要許 多時間之問題。 爲了提高液狀樹脂材料1 3之注入,塡充速度*雖然 可考慮到加熱樹脂材料以降低流動黏度之方法,但是依加 熱溫度,若經過一定時間時就會開始樹脂之硬化反應。並 且,由硬化反應之開始,樹脂材料之塡充速度會明顯地降 低,有時會發生塡充沒有完成之情形。 〔發明槪要〕 本發明係欲解決像這種問題所發明者,其目的係提供 一種半導體晶片與配線基板之浮片晶片連接部之可靠性高 ,並且朝下塡充形成所需之樹脂材料之塡充可在短時間結 束之半導體裝置。 本紙張尺度適用_國國家標準(CNS)A4規格(210 X 297公釐) ; 裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作杜印製 經濟部智慧財產局員工消費合作社印製 4 49 881 Α7 _____ Β7 五、發明說明(3 ) 本發明係一種半導體裝置,其特徵爲備有:在絕緣基 板之至少一方之主面形成配線層及連接端子之配線基板, 與在此配線基板之上述主面成面朝下所搭載之半導體元件 ,與在上述半導體元件之電極端子形成面配設複數列,連 接上述半導體元件與上述配線基板之凸塊,與塡充於上述 半導體元件與上述配線基板之間隙部之樹脂密封層,將上 述半導體元件與上述配線基板之間隙大小之平均(平均間 隙)視爲Η,上述凸塊之配設節距之平均(平均節距)視 爲Ρ,將上述間隙大小之偏差視爲D時|具有以下式(1 )所表示之平均間隙Η。 P/4-D/2 客 HSP/4 + D/ 2...... (1) 將本發明之半導體裝置之構造,於第1圖以模式表示 ,分別表示半導體元件與配線基板之間隙大小Η 〇,及凸 塊之配設節距Ρ0。於此圖,符號1係凸塊,2係半導體 元件(晶片),3係配線基板,4係表示樹脂密封層。 於本發明,作爲凸塊1係使用由Pb — Sn係,Sn -Ag系,Sn— Ag~Cu等之銲錫所成之凸塊。這些 凸塊1係在半導體元件2之電極終端區域形成面配設成複 數列(2列以上),但是|尤其區域狀,亦即配設成形成 配設領域(area )之半導體裝置時,縮短樹脂材料之塡充 時間之效果爲大。又,這種凸塊1之配設節距P 〇係成爲 6 0〜2 5 Ομιη較佳。若凸塊1之配設節距P0超過 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -0 - .-- ------------訂--------I <請先閱讀背面之注意事項再填寫本頁) 449 88 經濟部智慧財產局員工消費合作社印製 Α7 Β7 五、發明說明(4 ) 2 5 Ο μιη時,幾乎沒有縮短塡充時間之效果,又配設節 距Ρ 0爲未滿6 0 時,具有製造上之界限而有困難。 並且,作爲配線基板3,係在如玻璃布樹脂浸滲基板 之絕緣基板之至少一方主面(單面或兩面),可使用由銅 ,銅系合金,鎳系合金等所形成之配線層及連接用終端區 域之基板。 於本發明之半導體裝置,將配線基板3與半導體元件 2間隙之大小平均(平均間隙)Η,藉設定於上述(1 ) 式所示範圍|就可將朝下塡充形成所需之樹脂材料之塡充 作業,儘量在短時間結束,提高生產力。 按,凸塊1之配設節距係通常並非整個配設面爲一定 ,因依位置而節距相異,所以Ρ係表示配設節距之平均値 (平均節距)。並且,此平均節距Ρ,係如第2圖所示, 可視成沿著樹脂材料之塡充方向配設之凸塊列間之間隔 Pi之平均値。(Ρ=ΣΡ;/Ν,但是,Ν係凸塊數) ο 又,半導體元件2與配線基板3之間隙(尺寸),係 具有由於配線基板3之翹反,各個凸塊1之高度偏差,構 成半導體裝置之各零件之稱這些之偏差起因之偏差D(= 間隙最大値Η a X _間隙最小値H m , η )。所以,也考慮 此偏差D,就平均間隙値Η設定下式。 茲就導出上述(1 )式之過程表示於下。 如上述朝下塡充用之液狀樹脂材料,係在半導體元件 與配線基板之間隙部利用毛細管作用注入,塡充,所以, 本紙張尺度適用令國國家標準(CNS)A4規格(210* 297公釐) ;--------裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 4 498 8 1 Α„ Αί I--- B7 五、發明說明自) 樹脂材料之塡充所花之時間,係依存於間隙大小,凸塊之 配設(連接)節距,所塡充部分之長度,樹脂材料之流動 性(黏度),樹脂材料之接面張力等。 亦即,因係屬於毛細管作用之塡充,所以,若增大( 寬廣)間隙大小時,流動阻力就變小,塡充速度變快而可 縮短塡充所需之時間。同樣地,若凸塊徑相同時,凸塊之 配設節距變大時,由於凸塊之流動阻力就變小,塡充所需 之時間會變短。若將凸塊之配設節距變成一定時,凸塊徑 變小時,流動阻力就變小,塡充速度就變快。 第3圖係表示配線基板之電極終端區域徑A與間隙大 小Η之關係之圖表。此圖表係將凸塊徑定爲1 2 5 ( 亦即,凸塊體積爲一定),改變終端區域徑A時之間隙大 小Η之實測値爲依據製作。從此圖,即使是相同凸塊徑, 若將凸塊徑變小時,曉得可將凸塊高度變高,亦即可增大 間隙之大小Η。 但是,半導體元件及配線基板之電極終端區域徑A, 係由於製造程序上之問題,及對於連接部之應力集中,電 流密度增大引起之遷移(migration )等具有可靠性之問題 ,太小時並非佳,在現況下,終端區域徑A之實用性最小 値係成爲100/zm程度。 第4圖係表示終端區域徑A爲1 〇 0 /zm時|改變凸 塊之銲錫量,凸塊徑B與間隙之大小Η實際測定之結果之 圖表。從此圖就可淸楚,若欲增大間隙之大小Η時,也不 得不增大凸塊徑Β。 -----:---I----裝--------訂---------線! (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -8- 經濟部智慧財產局員工消費合作社印製 449881 _______B7____ 五、發明說明p ) 並且’間隙之大小Η與凸塊徑B,係從流動阻力之立 場具相反之因素,若依據液狀樹脂材料之流動解析之結果 ,在間隙之大小Η與凸塊徑Β,存在有因應凸塊之配設節 距Ρ之最佳値。 於第5圖表示考慮實驗及毛細管力與流動阻力均衡之 流動解析之結果。從此圖,就曉得在液狀樹脂材料之塡充 時間存在有最小値,塡充時間變成最小之間隙大小(最佳 間隙)Η,爲凸塊之配設節距ρ之1/4 (Η=Ρ/4) 。並且’此比例關係爲由解析及實驗之結果曉得,不由樹 脂材料之物性或塡充溫度就可成立。 並且,間隙之大小及凸塊之配設節距,位於一定範圍 時,將間隙之大小Η作爲平均値,將配設節距Ρ,沿著樹 脂材料之塡充方向所配設之凸塊列之間隙平均値,也可成 立上述之關係。 但是,以上所說明者,係半導體元件與配線基板之任 一,假定爲完全平坦之板狀體時之考察,實際上,爲半導 體元件與配線基板之各個存在有若干翹反。又,銲錫凸塊 ,係具有起因於製造程序之高度偏差,並且,由於製造程 度或材料等,因終端區域徑,半導體元件翹反量,配線基 板翹反量也會發生偏差,半導體元件與配線基板之間隙大 小,係在某幅度上將在上下搖動。在此上下搖動之幅度之 偏差量D,雖然依各個情形而異,但是通常係成爲1 〇〜 2 Ο V m。 因此,在配線基板半導體元件爲浮片晶片連接之半導 本紙張尺度適用中國國家標準(CNS)A4規格(2】0 X 297公釐) -9^ I I I I I ----it---------線 (請先閱讀背面之注音?事項再填寫本頁) 449 8 8 經濟部智慧財產局員工消費合作社印製 Α7 Β7 五、發明說明f ) 體裝置,相當於凸塊高度之半導體元件與配線基板之間隙 大小之平均(平均間隙)Η,藉成爲如下, P/4-D/2SH 客 P/4 + D/ 2 可將對於間隙部之樹脂材料之塡充在短時間完成,可形成 良好之朝下塡充。並且,將連接部之可靠性高之半導體裝 置,以高生產力並且低成本獲得。 又,若提高溫度時,在樹脂之硬化前,樹脂材料之黏 度會降低,所以,可縮短塡充所需之時間。於本發明之半 導體裝置,因塡充所需之時間會變極短,所以,在樹脂開 始硬化之前就可完成塡充。因此,也可提高溫度塡充,並 且,也可達成提高生產力。 尤其,凸塊之平均節距Ρ爲2 5 Ο Mm以下時,凸塊 之流動阻力將增大,塡充時間會明顯地增大。因此,若沒 有將間隙大小之設定成爲最佳時,對於半導體裝置之生產 力帶來重大障礙,但是,藉適用本發明所設定之平均間隙 Η,工業上可得到許多價値。 〔較佳實施例之詳細說明〕 茲就本發明之較佳實施例說明如下。 第6圖係將本發明之半導體裝置之第1實施例剖面地 表示者,第7圖係於此實施例表示凸塊之配設狀態之半導 體晶片之平面圖。 本纸張尺度適用中國國家標準(CNS)A4規格(210 x 297公釐) ---.--------^----I-----------^ I . ί請先閱讀背面之注意事項再填寫本頁) A7 449881 __B7__ 五、發明說明@ ) 於這些圖,符號5係表示矽等之半導體晶片,此半導 體晶片5之電極終端區域5 a形成面,有球狀之銲鍚終端 區域6排列2列所形成'•又,符號7係表示在兩面配線層 及連接於其之連接終端區域7 a所配設之玻璃一環氧配線 基板,在此配線基板7之單面,有半導體晶片5面朝下搭 載,經由此銲錫終端區域6以電氣方式連接。亦即,安裝 於半導體晶片5之電極終端區域5 a上之銲錫終端區域6 爲抵接於配線基板7之連接終端區域7a ,而由銲錫回銲 加以接合。並且,半導體晶片5與配線基板7之間隙部之 大小爲其平均値(平均間隙)Η係成爲滿足下式之數値。 P/4-D^H^P/4+D/2 (式中,P係銲錫凸塊之配設平均(平均節距),D係表 示間隙大小之偏差(=間隙最大値H m a x —間隙最小値 H m i η 0 ) 偏差D係例如,由剖面觀察法等,測定晶片之4角隅 與中心部之5處之凸塊高度,若Hmu爲5 8 ’ 1^1=1爲45^111時,將變成D=13vm。此時,若凸 塊之配設節距P爲2 0 0 //m時,凸塊之設計値亦即所有 凸塊之平均値爲位於56 . 5μιη與43 . 5ym間時’ 決定凸塊銲錫量,或銲錫凸塊徑及基板終端區域徑’靜錫 終端區域高度就可以= 亦即,對於銲錫終端區域6之平均節距P及間隙之偏 本紙張尺度適用令國國家標準(CNS)A4規格(210 X 297公发) (請先閱讀背面之注意事項再填寫本頁} 經濟部智慧財產局員工消費合作杜印製 -11 - I · I n I I I [ I 一5'* * ^ —— — — — — — illllltl — 1« I n — -—If — — — — —— — · 經濟部智慧財產局員工湞費合作社印製 449881 A7 ___B7_ 五、發明說明P ) 差D,能夠滿足上式,設定銲錫終端區域6與配線基板7 之平均間隙Η之最佳範圍,能夠獲得此設定範圍,來設定 銲錫終端區域6之直徑。 又,在配線基板7他方之面,形成有屬於外部連接端 子之外部連接終端區域7 b,此外部連接終端區域7 b與 銲錫終端區域6係經由設於配線基板7之通孔(via hole ) 等之內部配線(省略圖示)所導通。並且,在配線基板7 與半導體晶片5之間配置有銲錫終端區域6之空間部(具 有上述平均間隙Η ),形成有由環氧系樹脂所成之樹脂密 封(朝下塡充)8。在此,樹脂密封(朝下塡充)8之形 成爲將具有0.01〜2Pa·S黏度之液狀樹脂材料, 藉注入,塡充於配線基板7與銲錫終端區域6之間隙部進 行。並且,由此樹脂密封8,半導體晶片5與配線基板7 之實施連接部之機械性保護|及緩和兩者之熱膨脹不同起 因之熱應力。 於構成爲如此之第1實施例之半導體裝置,半導體晶 片5與配線基板7之平均間隙Η >由於成爲滿足P/4 — D/2SHSP/4+D/2(式中Ρ係凸塊之平均節距 ,D係表示間隙部大小之偏差)最佳値,所以,對於配線 基板7與半導體晶片5間隙部之樹脂材料之塡充,可在短 時間完成。因此,可獲得具有朝下塡充之浮片晶片連接部 之可靠性高,高生產力之半導體裝置。 按,於以上之實施例,在半導體晶片5之電極終端區 域5 a形成面,排列銲錫終端區域6所形成構造之半導體 本紙張尺度適用中國國家標準(CNS)A4規格(210 x 297公釐) 一 -----裝--------訂---------線 {請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 4^9 88 ^ A7 B7 五、發明說明(10 ) 裝置做了說明’但是終端區域之排列爲並非限於2列’也 可配設複數列之終端區域。並且’凸塊爲配設成區域( area )多數列之裝置時’縮短樹脂材料之塡充時間之效果 爲大,尤其第8圖所示’終端區域6係配置在半導體晶片 5之電極終端區域形成面之全面(總區域)之裝置時,具 有顯著之效果。 又,作爲配線基板7,係並非限於如玻璃_環氧配線 基板之樹脂系,也可以使用如氧化鋁系或氮化鋁系之陶瓷 系之配線基板。並且,在配線基板之連接終端區域上,也 可以設如銲錫之低熔點金屬之構造,並且,並非將銲錫終 端區域在半導體晶片側也可以形成於配線基板側。 由以上之說明就可淸楚,若依據本發明將對於半導體 元件與配線基板間隙部之樹脂材料之塡充,可在短時間結 束,由樹脂密封層(朝下塡充)緩和熱應力,將浮片晶片 連接部之可靠性高之半導體裝置,以高生產力及低成本獲 得。 又,本發明之半導體裝置,係因樹脂材料之塡充可在 短時間完成,所以,在樹脂開始硬化反應之前,塡充提高 溫度降低黏度之樹脂材料,並且,可達成提升生產力。 圖式之簡單說明 第1圖係將本發明之半導體裝置之構造以模式表示之 圖。 第2圖係於本發明之半導體裝置,爲了說明凸塊之平 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱) 13 --------------裝-----.—訂---------線 <請先閲讀背面之注意事項再填寫本頁> 經濟部智慧財產局員工消費合作社印製 449881 ΑΊ _________Β7_______ 五、發明說明(π ) 均節距所用之半導體元件之平面圖。 第3圖係於浮片晶片連接體,表示配線基板之終端區 域徑A與間隙之大小Η之關係之圖表。 第4圖係於浮片晶片連接體,表示凸塊徑β與間隙大 小Η之關係之圖表。 第5圖係於浮片晶片連接體之樹脂材料之填充,半導 體元件與配線基板之間隙大小Η,與塡充時間之關係之圖 表。 第6圖係表示有關本發明之半導體裝置之第1實施例 之剖面圖。 第7圖係於第1實施例,表示終端區域之配設狀態之 半導體晶片之平面圖。 第8圖係於第2實施例,表示終端區域之配設狀態之 半導體晶片之平面圖。 第9圖係將朝下塡充所需之液狀樹脂材料之注入,塡 充方法以模式表示之圖= 主要元件對照表 ---------------裝·-------訂·-------_線 (請先閱讀背面之注*Ϋ項再填寫本頁) 1,6,14 凸塊 5、1 1 半導體晶片 7、1 2、3 配線基板 7 b 外部連接終端區域 11a 電極終端區域 13 液狀樹脂材料 本紙張尺度適用中國國家標準(CNS)A4規格(210 x 297公釐) .14-
Claims (1)
- A8 B8 C8 D8 A4988 、申請專利範圍 1 . 一種半導體裝置,其係備有: (請先閱讀背面之注音?事項再填寫本頁) 在絕緣基板之至少一方之主面形成配線層及連接端子 之配線基板,與 在此配線基板之上述主面以面朝下搭載之半導體元件 ,與 上述半導體元件之電極端子彤成面配設成複數列,連 接上述半導體元件與上述配線基板之終端區域,與 上述半導體元件與上述配線基板之間隙部所塡充之樹 脂密封層, 將上述半導體元件與上述配線基板之間隙之大小之平 均(平均間隙)視爲Η,將上述終端區域之配設之配設節 距之平均(平均節距)視爲Ρ,將上述間隙之偏差視 爲D時,具有以(1 )式所表示之平均間隙 P/4-D/2SHSP/4 + D/ 2 經濟部智慧財產局員工消費合作社印製 .2.·. ·如申請專利範圍第1項之半導體裝置,其中上述 終端區域爲配設成區域狀》 3 .如申請專利範圍第1項之半導體裝置,其中上述 終端區域爲銲錫終端區域。 4 .如申請專利範圍第1項之半導體裝置,其中上述 終端區域之配設節距爲沿著構成上述樹脂密封層塡充樹脂 材料方配設之終端區域列間之間隔。 5 .如申請專利範圍第1項之半導體裝置,其中上述 -15- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) !^ ^49881 篮 1 C8 D8 六、申請專利範圍 終端區域之平均節距爲6 0〜2 5 0 。 經濟部智慧財產局員工消費合作社印製 ---------·*!.! --------訂---------線 (請先閱讀背面之ί£意事項再填寫本頁) -16- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)
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JP2001313314A (ja) * | 2000-04-28 | 2001-11-09 | Sony Corp | バンプを用いた半導体装置、その製造方法、および、バンプの形成方法 |
KR100398716B1 (ko) * | 2000-06-12 | 2003-09-19 | 가부시키가이샤 히타치세이사쿠쇼 | 반도체 모듈 및 반도체 장치를 접속한 회로 기판 |
US6417463B1 (en) * | 2000-10-02 | 2002-07-09 | Apple Computer, Inc. | Depopulation of a ball grid array to allow via placement |
JP2002184811A (ja) * | 2000-12-11 | 2002-06-28 | Sony Corp | 電子回路装置およびその製造方法 |
DE10204016A1 (de) * | 2002-01-31 | 2003-04-30 | Infineon Technologies Ag | Elektronisches Bauteil und Verfahren zu seiner Herstellung |
US7112882B2 (en) * | 2004-08-25 | 2006-09-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structures and methods for heat dissipation of semiconductor integrated circuits |
JP5028968B2 (ja) * | 2006-11-17 | 2012-09-19 | 日立電線株式会社 | 半導体装置、積層型半導体装置およびインターポーザ基板 |
JP5117371B2 (ja) * | 2008-12-24 | 2013-01-16 | 新光電気工業株式会社 | 半導体装置およびその製造方法 |
US9631065B2 (en) * | 2013-03-12 | 2017-04-25 | Intel Corporation | Methods of forming wafer level underfill materials and structures formed thereby |
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US5508561A (en) * | 1993-11-15 | 1996-04-16 | Nec Corporation | Apparatus for forming a double-bump structure used for flip-chip mounting |
JPH07153798A (ja) * | 1993-11-30 | 1995-06-16 | Sony Corp | 半導体製造方法及び半導体製造装置 |
JP3138159B2 (ja) * | 1994-11-22 | 2001-02-26 | シャープ株式会社 | 半導体装置、半導体装置実装体、及び半導体装置の交換方法 |
US5864178A (en) * | 1995-01-12 | 1999-01-26 | Kabushiki Kaisha Toshiba | Semiconductor device with improved encapsulating resin |
JP3311215B2 (ja) * | 1995-09-28 | 2002-08-05 | 株式会社東芝 | 半導体装置 |
JPH09134934A (ja) * | 1995-11-07 | 1997-05-20 | Sumitomo Metal Ind Ltd | 半導体パッケージ及び半導体装置 |
US5766982A (en) * | 1996-03-07 | 1998-06-16 | Micron Technology, Inc. | Method and apparatus for underfill of bumped or raised die |
JP3431406B2 (ja) * | 1996-07-30 | 2003-07-28 | 株式会社東芝 | 半導体パッケージ装置 |
JPH10163599A (ja) * | 1996-12-03 | 1998-06-19 | Nec Corp | プリント配線板 |
JP2982729B2 (ja) * | 1997-01-16 | 1999-11-29 | 日本電気株式会社 | 半導体装置 |
US5897335A (en) * | 1997-02-04 | 1999-04-27 | Integrated Device Technology, Inc. | Flip-chip bonding method |
JPH10313022A (ja) * | 1997-03-10 | 1998-11-24 | Toshiba Corp | 半導体装置 |
US6034427A (en) * | 1998-01-28 | 2000-03-07 | Prolinx Labs Corporation | Ball grid array structure and method for packaging an integrated circuit chip |
-
1999
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