TW412835B - Semiconductor device with decoupling capacitance and method thereof - Google Patents
Semiconductor device with decoupling capacitance and method thereof Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 17
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 239000007943 implant Substances 0.000 claims abstract description 37
- 238000002955 isolation Methods 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims description 25
- 238000002513 implantation Methods 0.000 claims description 13
- 239000003990 capacitor Substances 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims 1
- 238000009413 insulation Methods 0.000 claims 1
- 238000005516 engineering process Methods 0.000 description 9
- 239000002019 doping agent Substances 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000013459 approach Methods 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 235000012431 wafers Nutrition 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000875 corresponding effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- 101000708620 Homo sapiens Spermine oxidase Proteins 0.000 description 1
- 102100032800 Spermine oxidase Human genes 0.000 description 1
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000002079 cooperative effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 239000011593 sulfur Substances 0.000 description 1
- 238000005496 tempering Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- Semiconductor Integrated Circuits (AREA)
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
__412835_B7_ 五、發明説明（1 ) 發明背景 1. 技術範圍 本發明一般而言係關於半導體裝置，且更明確言之，係 關於在半導體裝置中之解耦合電容體系。 2. 背景技藝 絕緣體外延矽（SOI) CMOS技術，由於譬如較低接面電容之 因素，故提供比習用整體基材CMOS技術較高之性能=在 SOI技術中，較低接面電容係經由使有源電路與整體基材 以介電方式隔離而獲得。 經濟部中央標準局員工消费合作社印製 (請先閱讀背面之注意事項再填寫本頁 但是，與整體基材技術比較在SOI技術中有數項缺點。在 整體基材技術中’通常有南晶片解搞合電容’從電源Vdd 至地線，其主要是由於N-井對P基材接面電容所致。高晶 片解耦合電容係提供靜電排放（ESD)保護，及提供保護以防 止在晶片上之高切換噪音α很不幸地，ESD保護程度對於 在SOI上之輸入/輸出（V0)裝置，係被減退，此係由於較高 二極體電阻、不良熱傳導及極低晶片上解耦合電容，從電 源VDD至地線。再者，由於晶片上解耦合電容，故有高晶 片與I/O切換噪音。除非使用薄氧化物電容器，其不會被耗 盡，否則在SOI技術中之晶片對於噪音抑制具有極少解耦 合電容。 一種製造SOI裝置之常用方法，是在整體基材裝置中植入 氧原子，以形成埋置式氧化物層。此方法係被稱爲SMOX ( 藉植入氧隔離）。改良SOI技術中ESD保護程度之數種研究 途徑，已針對SIMOX提出。其中之一揭示蝕去氧化物層， _- 4 ~ _ 本纸張尺度適用中國國家標準i CNS ) Λ4規格（210X 297公釐） 412835 A7 B7 經濟部中央楳準局貝工消費合作社印製 -5- 五、發明説明（2 ) 因此I/O電晶體可建立於整體基材上。此途徑雖然証實esd 改良’但需要精密且昴貴之加工處理及處理控制（例如在 不同晶圓表面形態上蚀刻及形成電路）β另一種途徑係在 氧植入期間採用阻斷罩蓋，以保持整體基材中之ESD電路 區域。對此途徑而言’可獲得經改變之SIM〇x晶圓，其將 同時供南性能電路（S〇i)與可接受之ESD保護（整體基材） 。很不幸地，此途徑之缺失在於沒有供噪音抑制與適當 ESD+操作用之大的晶片上解核合電容器s 發明摘述 因此，本發明之優點係爲提供半導體裝置用之解耦合電 容’及其製造方法，其係排除上述缺陷。 本發月之優點係藉一種半導體裝置實現，此裝置包括第 -個電路區域’其具有第一個裝置層，位在隔離層上，及 鄰近第一個電路區域《第二個電路區_，其具有$二個裝 置層’位在一個井上。植入層係被植人第—個電路區域中 之隔離層下方，其係連接至第：個電路區域之井，形成* 接面電容，及因此是對半導體裝置可接受之解耦合電^广 本發明之前述及其他優點與特徵，將自下文本發 佳具體實施例之更特定説明而明瞭，其係如附圖 ：2 。 I ΤΓ 有 附圖簡述 本發明之較佳列舉具體實施例，將於後文搭配附圖加以 說明’其中類似名稱係表示類似元件，且： 圖1馬根據本發明較佳具體實施例之丰導體結構簡圖. 冬紙乐尺度適用中國囤家標辛·（ CNS) Λ4規格（2丨0)< 297公釐 (請先閲讀背命之注意事項再填寫本頁} *1Τ A7 B7 412835 — —— 五、發明説明（3) 圖2爲與圖i結構一起使用之舉例裝置；及 ' * hi -----衣--1 I ----訂 f請先聞磺背面之注意事項再填寫本頁j .圖3'4、5及6爲橫截面圓，説明根據本發明較佳具體 施例圖1之製造順序。 ' 附圖詳述 經濟部中央標準局員工消费合作社印製 參考圖1，其係以高度簡化形式顯示根據本發明積體電 路1〇您半導體結構。在此實例中，絕緣體外延矽（s〇i)結構 之第一個電路區域，係包含隔離氧化物層22、第一個裝置 層24、隔離層2〇及第一極性型之高劑量植入層乃，被植入 根據本發明具體實施例之隔離氧化物層22。第二個電路區 域（例如整體基材裝置區域），其係鄰近第一個電路區域， 其包含整體區域30，第一極性型之井幻與34，第二個裝置 區域，其包含第一與第二極性型之區域36, 38, π及料，以 及隔離層20。兩個電路區域係位於第二極性型之基材5〇中 ，第一個電路區域係覆蓋大部份晶片。雖然只顯示一個第 二個電路區域，但應明瞭的是，可在單一半導體基材上採 用多個此種區域，各描繪一裝1之後續作用區域。若需要 更夕$ 4 ’則在植入層25下方具第二極性型之選用摻雜劑 40，譬如例行性地使用於非表面技術中之〗_能量植入物 ，亦可使用，或基材水本身可爲具有ρ_磊晶層於頂部之ρ+ 水。 參考圖2 ’其係揭示！/0 ESD裝置U0作爲舉例裝置，其可 整合至本發明中。雖然於圖2中係顯示具有相應極性型區 域之P-型基材150，但亦可使用N_型基材，或具有藉由摻 雜所產生之P-區域之N-型基材等，其具有相應區域及對積 本纸張尺度適/种麵家標準（CNS) ^格（21GX;^ 412835 Α7 Β7 經濟部中央標準局員工消費合作、社印製 五、發明説明（4) 體電路110之修正。此I/O ESD裝置110係製自半導體基材， 此基材具有I/O墊片60連接至p+區域138與N+區域144 ;具 有N+區域136連接至Vdd，以形成第一個二極體；及具有p+ 區域142連接至地線’以形成第二個二極體。I/。ESD裝置或 類似裝置’亦可製自N-型基材，其具有適當連接與修正， 以提供適當性能。如前文所提及者，若需要更多電容，則 亦可使用在N-型植入層下方之選用p_型摻雜劑140 (或在N_ 型基材之情況中，爲在P-型植入層下方之N-型摻雜劑）。 正如可於圖2中所見及者，然後自Vdd至地線形成高接面 電容。Vdd係經由N-井132耦合至N-型植入層125，其係耦 合至N+區域136。P-型整體區域130係經由P+區域142連接 至地線。：P-型摻雜劑H0亦可用於增加電容。又另一項選擇 是使用簡併摻雜（在此實例中爲p+)水，其具有輕微摻雜之 #晶層（在此實例中爲P-) +，以提供高電容與低電阻。正如 將於後續圖中所顯示者，與典型上在SIM〇X方法中所使用 者比較’本發明之一項優點是從Vdd至地線之高接面電容 可以増加，而未使用任何特別罩蓋。 現在參考圖3_6，將討論本發明較佳具體實施例之製造。 正如在圖3中所見及者，係使用一種不重要之罩蓋7〇，以 界定第二極性型之基材5〇之第二個電路區域（整體區域）， 如在圖1中所述者。然後，將氧與第一極性型之摻雜劑植 入物7D ’實質上同時塗敷至基材5〇，以形成隔離氧化物層 22與第一極性型之植入層25，經埋置在隔離氧化物層22下 方’正如在圖4中所見及者。由於隔離氧化物層22回火溫 ^悄目 ---------- -I*. —II —II --，^!. - II - - -- (請先閲讀背面之注意事項再填寫本頁) 4 412835 at _____ B7 五、發明説明（5 ) 度相當高（大約攝氏1200-1300度），故植入層25將向外擴散（ 意即’擴散超過植入邊界），如圖5中所示。因此，如圖6 中所示，在SOI與整體區域之接著標準形成後，植入層25 將連接至整體區域中具第一極性型之井32與34。 因此’本發明係經由植入一植入層在隔離氧化物下方， 而提供從Vdd至地線之解耦合電容。再者，此植入物可與 隔離氧化物形成同時達成，而無需特別罩蓋。第二種植入 物（譬如P+或N+摻雜劑）亦可用於増加電容。 雖然本發明已經特別地參考其較佳具體實施例加以説明 與描述’但熟諳此藝者應明瞭的是，前述及其他在形式與 細節上之改變’在未偏離本發明之精神與範圍下均可於其 中施行s (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部中央橾準局員工消费合作社印製 -8- 本紙ί艮尺度適用中國國家標率（CN'S ) /U規格（2丨0><297公釐）
Claims (1)
- 412835 B8 C8 D8 六、申請專利範圍1. 羯’其包含： (請先閱讀背由之泣意事項再填寫本頁) 第5¾電路區域，其具有第一個裝置層，位在隔離 層上； 鄰近第一個電路區域之第二個電路區域，其具有第 二個裝置層，位在第一極性型之井上；及 第一極性型之植入層，被植入隔離層下方，並連接 至該井。 2. 如申請專利範圍第1項之裝置，其中該井爲N-井，且該 植入層爲N-型植入層3 3. 如申請專利範圍第1項之裝置，其中該井爲P-井，且該 植入層爲P-型植入層=> 4. 如申請專利範圍第2項之裝置，其進一步包含： P-型植入層，被植入該N-型植入層下方。 5. 如申請專利範圍第3項之裝置，其進一步包含： N-型植入層，被植入該P-型植入層下方。 6. —種在具有基材之半導體裝置中發展解耦合電容之方法 ，其包括以下步驟： 經濟部中央標隼局員工消费合作杜印製 a) 在基材上使用罩蓋界定第一個電路區域與第二 個電路區域； b) 在第一個電路區域中植入隔離層： c) 在第一個電路區域中-之隔離層下方植入一植入 層；及 其中該植入層係 d) 在第二個電路區域中形成井 電耦合至該井3 本紙張尺度適用中國國家標单（CNS ) A4規格（210X297公釐） AJ B8 C8 D8 412835 、申請專利範圍 7.如申請專利範圍第、 图弟6頁义方法，其中步騍b)與C)係實質 上同時達成。 8_如中請專利範圍第6谓之方法，其中該井爲N·井，且該 植入層爲N-型植入層。 9.如申請專利範圍第6嚷之方法，其中該井爲?_井，且該 植入層爲P-型植入層。 K)‘如申請專利範圍第6項 貝义万法’其進一步包括以下步驟 e)在第一個電路區域中乏傾^ 扭離層上万，形成第一 個裝置層；及 置層 f)在第二個電路區域中之井上方，形成第 二個裝 妓濟部中央標率局員工消费合作社印製 如申請專利1&圍第6项之方法，其進-步在步驟c)與步 驟㈣包括以下步骤：加熱第—個電路區域，以使隔 離層回火，其中植入層係從植人處向外擴散。 12. 如申請專利範圍第6項之方法，其中植入層係連接至該 井。 13. 如申請專利範圍第6項之方法，其進—步包括以下步驟 6)在第一個電路區域中之植入層下方，植入第二 個植入層。 一 14. 一種半導體裝置，其包含： 基材： 在基材中之第一個電路區域，其具有隔離層位在基 -10 本纸乐尺度適用中國國家標準（CNS ) A4現格（210X297公釐） 412835 --------、申請專利範圍 A8 B8 C8 D8 經濟部中央標辛局Κί工消Φ;合作社印製 材中形成之第一個裝置下方，及植入層位在該隔離層下 方；及 在基材中之第二個電路區域，其係鄰近該第一個電 路區域’並具有一個井，且於其中形成第二個裝置， 其中該植入層係電耦合至該井。 15. 如申請專利範圍第14項之裝置，其中該井爲N_井，且 該植入層爲N-型植入層D 16. 如申請專利範圍第14項之裝置，其中該井爲卜井 植入層爲p-型植入層。 17. 如申請專利範圍第15項之裝置，其進一步包含： P-型植入層，被植入該N_型植入層下方。 18. 如申請專利範園第16項之裝置，其進一步包含： N-型植入層，被植入該p_型植入層下方3 19. —種鄰近SOI裝置區域具有整體裝置區域之設備 良事項包括： 位於SOI裝置區域中之隔離層下方之植入層，係連接 至位於整體裝置區域下方之井。 m如申請專利範園第19項之設備 該植入層爲N-型植入層， 21.如申請專利範圍第19項之設備， 植入層爲P-型植入層3 .. 且該 其改 ’其中該丼爲N-井，ϋ 其中該井爲Ρ-井，且驾 (請先閱讀背面之注意事項再填寫本頁) 衣- 訂 -11 - 本纸張尺度適用中國國家標準（CNS ) Λ4現格（210X297公釐）
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| US5525531A (en) | 1995-06-05 | 1996-06-11 | International Business Machines Corporation | SOI DRAM with field-shield isolation |
| JPH0945912A (ja) * | 1995-07-31 | 1997-02-14 | Nec Corp | 半導体装置およびその製造方法 |
| JP3143592B2 (ja) * | 1995-09-14 | 2001-03-07 | キヤノン株式会社 | 表示装置 |
| JPH09115999A (ja) * | 1995-10-23 | 1997-05-02 | Denso Corp | 半導体集積回路装置 |
| JP3376204B2 (ja) * | 1996-02-15 | 2003-02-10 | 株式会社東芝 | 半導体装置 |
| US6191451B1 (en) * | 1998-01-30 | 2001-02-20 | International Business Machines Corporation | Semiconductor device with decoupling capacitance |
| US6020614A (en) * | 1998-03-25 | 2000-02-01 | Worley; Eugene Robert | Method of reducing substrate noise coupling in mixed signal integrated circuits |
-
1998
- 1998-01-30 US US09/016,026 patent/US6191451B1/en not_active Expired - Fee Related
-
1999
- 1999-01-26 JP JP01713999A patent/JP3254431B2/ja not_active Expired - Fee Related
- 1999-01-26 SG SG1999000172A patent/SG72919A1/en unknown
- 1999-01-27 TW TW088101226A patent/TW412835B/zh not_active IP Right Cessation
- 1999-01-29 KR KR1019990002838A patent/KR100329895B1/ko not_active IP Right Cessation
-
2000
- 2000-08-09 US US09/634,970 patent/US6365484B1/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH11260909A (ja) | 1999-09-24 |
| US6191451B1 (en) | 2001-02-20 |
| KR19990068200A (ko) | 1999-08-25 |
| JP3254431B2 (ja) | 2002-02-04 |
| KR100329895B1 (ko) | 2002-03-22 |
| SG72919A1 (en) | 2000-05-23 |
| US6365484B1 (en) | 2002-04-02 |
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| GD4A | Issue of patent certificate for granted invention patent | ||
| MM4A | Annulment or lapse of patent due to non-payment of fees |