582111 A7582111 A7
發明背景 發明領域 本，明相關於嵌人式去_合電容器，特別式絕緣物上的 :術，其可降低雜訊並有助於解決邊緣單元近似效 :1 I藉之，，肖除分開,耦合電容器與OPC結構的需 現今科學出現越來越多對微電子技術的▲需求。今天， 片^經工作在接近千兆赫範圍的速度Λ前的趨勢繼續 要曰曰片處理增加電子信號的數量，利用更少的空間與更 的時間。晶片廣泛的用在種類繁多的應用上，例如個人 回己L庫蜂巢笔活，以及热習本技藝的人所熟知的 他電子裝置。不考慮到實際的應用，晶片的結構控制晶 可以工作的速度以及晶片可以處理的電子信號數量。 每個晶片有上千個儲存並處理電子信號之電路的半導體 基質。要符合日益增加的高速及高信號量的微電子，晶片 上電路的數目要增加。然而，電路的數目，及因而的微電 子的進步，受限於晶片表面上可用空間。 晶片上的空間受限於晶片上電路的兩個次最佳運用特 色。首先’要降低高速資料傳輸造成的雜訊，電路區塊窝 要去_合電容器。去耦合電容器的結構相當大並且是用在 電源供應及地電位之間提供正常電路動作的足夠雜訊免 除。例如，圖1為顯示緩衝單元1 0的簡單圖，電源供應i 2 及電源綠上的雜訊1 1被大的去_合電容器1 4阻絕。 -5- 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 裝 訂 線 582111BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to embedded technology for embedded capacitors, special insulators, which can reduce noise and help to solve the approximate effect of edge cells: 1 I. The need for coupling capacitors and OPC structures is increasing in scientific demand for microelectronics. Today, the trend of working at speeds near the gigahertz range continues to be that film processing increases the number of electronic signals, making use of less space and more time. Chips are widely used in a wide variety of applications, such as personal hive library work, and other electronic devices that are well known to those skilled in the art. Regardless of the actual application, the structure of the wafer controls the speed at which the wafer can work and the number of electronic signals the wafer can process. Each wafer has thousands of semiconductor substrates that store and process electronic signals. To comply with the increasing number of high-speed and high-signal microelectronics, the number of circuits on the chip must increase. However, the number of circuits, and thus the advancement of microelectronics, is limited by the space available on the surface of the wafer. The space on the wafer is limited by the two sub-optimal characteristics of the circuitry on the wafer. First of all, to reduce the noise caused by high-speed data transmission, the circuit block must be closed. The structure of the decoupling capacitor is quite large and is used to provide sufficient noise immunity between the power supply and ground to provide normal circuit operation. For example, FIG. 1 is a simple diagram showing the buffer unit 10, and the noise 1 1 on the power supply i 2 and the power green is blocked by the large decoupling capacitor 14. -5- This paper size applies to China National Standard (CNS) A4 (210X297 mm) binding line 582111
第一，裝置品要至少兩個外部的光學近似修正（〇pC)結 構來降低在作用閘極線邊緣上近似環境中的改變造成的光 學繞射效應。此OPC結構由一處理配置來修正完整的晶片 佈局資料集。這個處理可以在晶片佈局由所謂的光學近似 修正技術產生的晶片佈局之後執行或是在設計處理期間， 此OPC結構可以放在電路中作用閘極線的任一端點。在這 個位置，OPC結構降低近似效應藉由提供作用閘極與在閘 極陣列中間的作用閘極相同的局部環境。結構的使用 在陣列周邊是可接收的解決方案對於單獨的陣列晶片或甚 至是應用指定積體電路（ASIC)晶片，其陣列元件形成整個 晶片面積的小部分，因為〇PC結構所佔的相對空間量很 訂 要最佳化晶片處理速度並增加資料處理的數量，需要有 效的使用晶片表面上的空間。結果，最好的整合去耦合電 客器與OPC結構而不增加雜訊或是繞射效應。 發明概要 線 因此，本發明的目的在提供一結構與方法來提供半導體 晶片，其包含有儲存及處理資料的第一單元的第一區域， 以及在第-區域外有OPC結構的第二區域，其中QPC結構包 含去耦合電答器。第一單元的作用閘極的線寬度與〇%結 構的大小相同或類似大小。此0PC結構降低第一單元中作 用裝置的近似效應，並包含N-型態FETs&p_型態FETs,其 位在第二區域中。此〇PC結構可以有大於第一單元的寬 度。第二區域可以是多個0PC結構，藉之第二區域包含多 -6-First, the device requires at least two external optical approximation correction (0pC) structures to reduce optical diffraction effects caused by changes in the approximate environment on the edge of the active gate line. This OPC structure has a processing configuration to modify the complete chip layout data set. This process can be performed after the wafer layout is produced by a so-called optical approximation correction technique, or during the design process, the OPC structure can be placed at any end of the circuit where the gate line is applied. At this location, the OPC structure reduces the approximate effect by providing the same local environment of the active gate as the active gate in the middle of the gate array. The use of structures is an acceptable solution around the array. For individual array wafers or even application-specific integrated circuit (ASIC) wafers, the array elements form a small part of the entire wafer area because the relative space occupied by the 0PC structure. The quantity is customized. To optimize the processing speed of the wafer and increase the amount of data processing, it is necessary to effectively use the space on the surface of the wafer. As a result, the best integration is to decouple the guest from the OPC structure without adding noise or diffraction effects. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a structure and a method for providing a semiconductor wafer including a first region including a first unit for storing and processing data, and a second region having an OPC structure outside the first region, The QPC structure includes a decoupling electro-responder. The line width of the active gate of the first unit is the same as or similar to that of the 0% structure. This OPC structure reduces the approximate effect of the active device in the first cell and contains N-type FETs & p-type FETs, which are located in the second region. The OPC structure may have a width larger than that of the first cell. The second area can be multiple 0PC structures, by which the second area contains multiple -6-
582111 A7 B7 五、發明説明（3 ) 個去耦合電容器。第一單元中的作用裝置分開第一距離而 此〇PC結構與此作用裝置分開第一距離。 本發明的進一步具體實例是半導體裝置，其包含一底 材，一有第一複數個平行延長閘極的第一電晶體，此第一 電晶體形成在此底材的區域中，以及至少一個0 P C結構形 成在第一複數個拉長閘極的最外圍閘極的相同平面並與之 平行的延伸，其中OPC結構是當作去耦合電容器以及光學 近似修正器。此第一複數個平行延長的閘極的線寬度與 OPC結構的相同，其中OPC結構降低第一單元的近似效應而 第一複數個平行延長閘極係用來儲存及處理資料。此OPC 結構的寬度大於第一複數個平行延長閘極的一個閘極。第 一電晶體包含多個OPC結構而此電晶體包含多個去耦合電 容器。第一單元的第一複數個平行延長閘極的每個閘極分 開第一距離，而OPC結構與此第一複數個平行延長閘極分 開第一距離。 本發明還以具體實例說明一包含有用來儲存及處理資料 之第一單元的第一區域的半導體裝置，其中每個第一單元 包含分開第一距離的裝置，以及在第一區域外有OPC結構 的第二區域，其中此OPC結構與第一單元中第一單元的最 外面裝置平行且共面，而OPC結構之一與最外面的第一單 元分開第一距離，其中此OPC結構包含去耦合電容器。此 第一單元包含與OPC結構相同或類似的線寬度。此OPC結構 降低第一單元的近似效應並還包含N -型態FET及P -型態 FET，其中的N -型態FE丁及P -型態FET每一個均包含第一區 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 域及第二區域。此0PC結構可八 、 的寬度，而楚- 的寬度大於第一單元 域包人射能包含多個⑽結構，藉之第二區 域包含多個去耦合電容器。 步u 圖示簡述 其中類似的號碼 本發明將參考下面的圖示做詳細說明 參考類似的元件且其中： 圖1為具有去耦合電容器之電路佈局； 圖2 A為傳統去耦合電容器的佈局； 圖2B為包含緩衝單元的_ 丁及败丁概要圖； 圖2C為對應在圖2A中所顯示結構的電路圖之概要圖； 圖3A為根據本發明有去核合電容器之緩衝單元的佈局； 圖3B為對應在圖3A中所顯示結構電路圖的概要圖；以 及 圖4為跨過裝置部分及去轉合電容器之橫切面的概要 圖。 本發明較佳具體實例的詳細說明 本發明提供一種結構給結合成為一個裝置的半導體裝置 表面有去耦合電容器及0PC結構。結果，僅需要較少的半 導體表面空間來降低與高速處理有關的雜訊及近似效應。 如圖1及2A-2C中描述的，本發明之前，需要兩個裝置來 控制這些次最佳運用特色的問題。圖丨中的去耦合電容器 14及圖2A及2C中的20消除雜訊，而〇pc結構（未顯示在圖 1中）降低近似效應。圖2 A為傳統去耦合電容器的圖，其 允許用在晶圓中來降低雜訊。每個〇pC結構p _型態場效電 -8-582111 A7 B7 V. Description of the invention (3) Decoupling capacitors. The acting device in the first unit is separated by a first distance and thus the OPC structure is separated from the acting device by a first distance. A further specific example of the present invention is a semiconductor device including a substrate, a first transistor having a first plurality of parallel extended gate electrodes, the first transistor is formed in a region of the substrate, and at least one 0 The PC structure is formed on the same plane of the outermost gate of the first plurality of elongated gates and extends parallel to it. The OPC structure is used as a decoupling capacitor and an optical approximation corrector. The line width of the first plurality of parallel extended gates is the same as that of the OPC structure. The OPC structure reduces the approximate effect of the first unit and the first plurality of parallel extended gates are used to store and process data. The width of this OPC structure is larger than one gate of the first plurality of parallel extended gates. The first transistor contains multiple OPC structures and the transistor contains multiple decoupling capacitors. Each gate of the first plurality of parallel extended gates of the first unit is separated by a first distance, and the OPC structure is separated from the first plurality of parallel extended gates by a first distance. The present invention also illustrates a specific example of a semiconductor device including a first area for storing and processing a first unit of data, wherein each first unit includes a device for separating a first distance, and an OPC structure outside the first area. The second area of the OPC structure, where the OPC structure is parallel and coplanar with the outermost device of the first unit in the first unit, and one of the OPC structures is separated by a first distance from the outermost first unit, where the OPC structure includes decoupling Capacitor. This first cell contains the same or similar line width as the OPC structure. This OPC structure reduces the approximate effect of the first cell and also includes N-type FETs and P-type FETs, where each of the N-type FE and P-type FETs includes the first region. China National Standard (CNS) A4 specification (210 X 297 mm) and the second area. This 0PC structure can have a width of 8 Å, and the width of Chu-is larger than the first unit. The package can contain multiple plutonium structures, and the second area contains multiple decoupling capacitors. Step u is a brief description of similar numbers. The present invention will be described in detail with reference to the following drawings and refer to similar components and among them: Figure 1 is a circuit layout with decoupling capacitors; Figure 2 A is a layout of traditional decoupling capacitors; FIG. 2B is a schematic diagram of a Ding and a Ding including a buffer unit; FIG. 2C is a schematic diagram of a circuit diagram corresponding to the structure shown in FIG. 2A; FIG. 3A is a layout of a buffer unit having a denucleating capacitor according to the present invention; 3B is a schematic diagram corresponding to the structural circuit diagram shown in FIG. 3A; and FIG. 4 is a schematic diagram of a cross section across the device portion and the decoupling capacitor. Detailed description of a preferred embodiment of the present invention The present invention provides a structure for a semiconductor device combined into a device with a decoupling capacitor and an OPC structure on the surface. As a result, less semiconductor surface space is required to reduce the noise and approximation effects associated with high-speed processing. As described in Figures 1 and 2A-2C, prior to the present invention, two devices were needed to control these sub-optimal features. The decoupling capacitors 14 in Figure 丨 and 20 in Figures 2A and 2C eliminate noise, while the 0pc structure (not shown in Figure 1) reduces the approximation effect. Figure 2A is a diagram of a conventional decoupling capacitor that allows it to be used in a wafer to reduce noise. Each 〇pC structure p _ type field effect electricity -8-
582111 A7 B7 五、發明説明（ 晶體（PFET) 100及N -型態場效電晶體（NFET) 110用一個去耦 合電容器20。如圖2C電路圖描述的，去耦合電容器接線 至在VDD橫軌3 8及地電位橫軌5 0間的PFET 100及NFET 110。 此去耦合電容器有一閘極2 2、一源汲極接觸2 4、一擴散區 域26及一 N-井28。 圖2B描述一組PFET 100及NFET 110。OPC結構3 0及40分別 在PFET 100及NFET 110的外面部份。PFET裝置100的整個結構 包含連串的閘極102，N -井區域104有源/汲極擴散區域1〇6及 OPC結構3 0位在源/汲極擴散區域1〇6的外面。源/汲極接觸 區域109同樣提供在源/汲極擴散區域1〇6内。閘極區域1〇2提 供在源/汲極擴散區域106及延伸的閘極部分1〇8從源/汲極擴 散區域106外延伸出來。多晶矽閘極延伸在擴散區域外，來 允許在遮罩不對齊或其他處理變易的條件下適當定義 PFET。 類似的，此NFET裝置110包含連串的閘極112、源/汲極擴 散區域114及位在源/汲極擴散區域114外的OPC結構4 0。此 NFET裝置11〇還包含源/汲極擴散接觸區域118以及在源/汲極 擴散區域114内的閘極區域112以及延伸的閘極部分116其延 伸到源/汲極擴散區域114外。 PFET裝置1〇〇與nfeT 110裝置的OPC結構30與40及連串的 閘極102與112的每一個是用傳導材料例如多晶碎做的。此 〇PC結構3 0與4 0也可以與個別閘極有相同的線寬度，大小 及形狀。然而，在OPC結構3 0與4 0及閘極102與112間有兩個 主要的差異。首先，此0PC結構3 〇與4 0為非作用中的而閘 -9 - 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐) 裝 訂 線 582111 A7 B7 五、發明説明（ 極102與112為作用中的。第二，此〇PC結構3〇與4〇整個位在 擴散區域106及114外，而只有閘極的最外面部分刚與n 6 位在擴散區域1〇6及1 η外。 金屬層（未顯示）連接PFET裝置1〇〇的源極區域與正電源丄6 並連接NFET裝置11〇的源極區域與地電位。每個裝置的汲極 區域連接在共同的輸出上。 圖2 C更特定的顯示PFET裝置1〇〇有連接到正電源3 8的源 極區域以及閘極區域1〇2連接（經由1〇3)到輸入端子5 2。此 NFET裝置11〇的閘極區域H2連接（經由1〇5)到輸入5 2端子而 其源極區域連接到地電位5 〇。NFET裝置11〇的汲極區域在 輸出端子5 4連接到PFET裝置100的沒極區域。去輕合電容器 2 0的閘極區域2 2連接到地電位5 0而其擴散區域2 6連接到 正電源3 8。根據這個傳統的設計，0PC結構及去耦合電容 為所利用晶片空間的總和等於作用中晶片面積的2 〇 〇/0。 本發明延伸NFE丁及PFET的擴散區域並將去耦合電容器嵌 入到OPC結構中。藉之，本發明可消除如圖2 a描述的分別 去镇合電容器2 0的需求。圖3 A描述本發明的簡化結構並 包含根據本發明的一組PFET 200及NFET 210的圖。 圖3 A包含類似於圖2 A所描述特色的特色，但是圖3 A已 經根據本發明加以修改。類似圖2 A，此PFET裝置200包含 字連的閘極202，OPC結構230，有源極/汲極擴散區域206的 N -井區域204。源極/汲極接觸區域208提供有源極/汲極擴 散區域206。閘極202提供在此源極/汲極擴散區域206中並且 有延伸部分203，其延伸到源極/汲極擴散區域206外。此擴 -10- 本紙張尺収用中關家標準(CNS) A4規格(210 X 297公董) 582111 A7 B7 五、發明説明（7 ) 散區域206還有兩個側面延伸207，相較於圖2 B中的NFET擴 散區域106。 同樣，類似圖2 A，NFE丁裝置210包含連串的閘極212， OPC結構240，在擴散區域216中源極/汲極接觸區域214。閘 極區域212提供在擴散區域216中並有一延伸部分213，其延 伸到擴散區域216之外。擴散區域216還有兩個側延伸217， 相較於圖2 B中的NFET擴散區域114。 本發明如圖3 A及3 B中描述的與圖2 A - C所顯示結構的關 键差異是使用嵌入式去耦合電容器來降低雜訊與近似效 應，而不是OPC結構及分開的去耦合電容器2 0。此去耦合 電容器係嵌入到OPC結構230與240中，藉由擴大此擴散區域 206與216，如此擴散區域206與216的側面部分207與217包含了 OPC結構230及240。擴散區域的擴大允許使得多晶矽OPC結 構的承受電容特性變為作用中的並提供去耦合電容。因 此，本發明可以只用OPC結構來降低雜訊及近似效應，而 最後的組合OPC結構及嵌入式去耦合電容器明顯的比圖2 A 的兩個分開裝置為小。 圖3 B顯示對應圖3 A裝置的電路圖。如示，此PFET裝置 200的源極區域連接到正電源供應120而其閘極區域202連接 到輸入端子122。此NFET裝置210的源極區域連接到地電位 124而其閘極區域212連接到輸入端子。此PFE丁裝置200的沒 極區域以及NFET 210的汲極區域共同的連接到輸出端子 128。圖3 B進一步顯示OPC結構230與240。此OPC結構之連接 如圖3 B所示。更特定的，OPC結構240連接到地電位，而 -11 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 582111 A7 B7 五、發明説明（8 ) 〇PC結構230連接到正電源供應。 雖然圖3 A描述每個OPC結構230及240最好能有與對應的閘 極區域相同的寬度，外面OPC結構230及240可以做得更寬或 是可以加進好幾個。就與圖2 A設計的相同空間而言，提供 了較好的電源供應去耦合。 圖4為經由部分晶片105及嵌入式去耦電容器6 6的部分橫 切面。上方電容器板6 8最好是用閘極多晶矽做的。電容器 的底板62為矽突塊，最好接地。電容器電介質是閘極電介 質。如此，電容器並不需用到分開之電介質。此電容器使 用與NFETs及PFETs相同的電介質層。圖4顯示兩個閘極區 域64而其中一個嵌入式電容器OPC結構66。如符號AA@ 指示的，此OPC結構維持相鄰閘極間相同的間隔。 將此電容器嵌入到多晶矽OPC結構中有好幾個益處。首 先，嵌入式電容器消除大型電容器的需求並只需要較少的 晶片上空間。空出來的空間可接著填入更多的單元而使得 晶片可以較快的速率處理更多數量的資料。其次，OPC結 構與去耦合電容器的整合使得設計方法學可以更容易，其 中去耦合電容器在裝置佈局時間點加入的，或是簡單的根 據裝置大小或是根據電路圖中設計者-特定的參數。這引 導最佳化的放置及密度，相較於稍後個別元件的放置。結 果，本發明提供在去耦合電容器與裝置間較少的串聯電 阻，比傳統的個別的去耦合電容器。這可以增加去耦合電 容器的效益特別是在高頻，藉由降低電阻/電容器（RC)延 遲並提升閘極的效能。最後，將電容器建造成陣列，可以 -12- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 582111582111 A7 B7 V. Description of the invention (PFET 100 and N-type field effect transistor (NFET) 110 uses a decoupling capacitor 20. As shown in the circuit diagram of FIG. 2C, the decoupling capacitor is connected to the VDD rail 3 PFET 100 and NFET 110 between 8 and ground potential rail 50. This decoupling capacitor has a gate 2 2, a source-drain contact 2 4, a diffusion region 26, and an N-well 28. Figure 2B depicts a group PFET 100 and NFET 110. OPC structures 30 and 40 are on the outside of PFET 100 and NFET 110, respectively. The entire structure of PFET device 100 includes a series of gates 102, N-well region 104, active / drain diffusion regions. The 10 and OPC structures 30 are located outside the source / drain diffusion region 106. The source / drain contact region 109 is also provided in the source / drain diffusion region 106. The gate region 102 provides The source / drain diffusion region 106 and the extended gate portion 108 extend from outside the source / drain diffusion region 106. The polysilicon gate extends outside the diffusion region to allow misalignment of the mask or other processing to be facilitated. The PFET is appropriately defined under conditions. Similarly, the NFET device 110 includes a series of gates 112, source / sink The diffusion region 114 and the OPC structure 40 located outside the source / drain diffusion region 114. The NFET device 110 also includes a source / drain diffusion contact region 118 and a gate region 112 within the source / drain diffusion region 114. And the extended gate portion 116 extends outside the source / drain diffusion region 114. The OPC structures 30 and 40 of the PFET device 100 and the nfeT 110 device and each of the series of gates 102 and 112 are made of conductive material For example, the polycrystalline chip is made. The PC structures 30 and 40 can also have the same line width, size and shape as the individual gates. However, there are between the OPC structures 30 and 40 and the gates 102 and 112. Two main differences. First, the 0PC structure 3 0 and 40 are non-active and the gate -9-This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) binding line 582111 A7 B7 5 2. Description of the invention (The poles 102 and 112 are active. Second, the 〇PC structures 30 and 40 are located outside the diffusion regions 106 and 114, and only the outermost part of the gate is just diffused with n 6. Regions 106 and 1 η outside. A metal layer (not shown) connects the source region of the PFET device 100 to the positive region. Source 6 connects the source region of the NFET device 11 to ground potential. The drain region of each device is connected to a common output. Figure 2C shows more specifically that the PFET device 100 is connected to a positive power source 3 8 The source region and gate region 102 are connected (via 103) to the input terminal 52. The gate region H2 of this NFET device 110 is connected (via 105) to the input 52 terminal and its source region is connected to the ground potential 50. The drain region of the NFET device 110 is connected to the non-polar region of the PFET device 100 at the output terminal 54. The gate region 22 of the de-lighting capacitor 20 is connected to the ground potential 50 and its diffusion region 26 is connected to the positive power source 38. According to this traditional design, the sum of the 0PC structure and the decoupling capacitor is equal to 2000/0 of the active chip area. The invention extends the diffusion regions of NFE and PFET and embeds a decoupling capacitor into the OPC structure. By this, the present invention can eliminate the need to separate the capacitors 20 separately as described in Fig. 2a. Figure 3 A depicts a simplified structure of the present invention and includes a diagram of a set of PFET 200 and NFET 210 according to the present invention. Figure 3A contains features similar to those described in Figure 2A, but Figure 3A has been modified in accordance with the present invention. Similar to FIG. 2A, the PFET device 200 includes a gate 202, an OPC structure 230, and an N-well region 204 of a source / drain diffusion region 206. The source / drain contact region 208 provides a source / drain diffusion region 206. The gate 202 is provided in this source / drain diffusion region 206 and has an extension portion 203 that extends outside the source / drain diffusion region 206. This expansion-10- This paper ruler adopts Zhongguanjia Standard (CNS) A4 specification (210 X 297 public directors) 582111 A7 B7 V. Description of the invention (7) There are two side extensions 207 in the scattered area 206, compared with the figure NFET diffusion region 106 in 2B. Similarly, similar to FIG. 2A, the NFE device 210 includes a series of gates 212, an OPC structure 240, and a source / drain contact region 214 in a diffusion region 216. The gate region 212 is provided in the diffusion region 216 and has an extension portion 213 that extends beyond the diffusion region 216. The diffusion region 216 also has two side extensions 217 compared to the NFET diffusion region 114 in FIG. 2B. The key difference between the structure of the present invention as shown in Figs. 3 A and 3 B and that shown in Figs. 2 A-C is the use of embedded decoupling capacitors to reduce noise and approximate effects, rather than the OPC structure and separate decoupling capacitors. 2 0. The decoupling capacitor is embedded in the OPC structures 230 and 240. By expanding the diffusion regions 206 and 216, the side portions 207 and 217 of the diffusion regions 206 and 216 include the OPC structures 230 and 240. The expansion of the diffusion region allows the capacitance-bearing characteristics of the polysilicon OPC structure to become active and provide decoupling capacitance. Therefore, the present invention can only use the OPC structure to reduce noise and approximate effects, and the final combined OPC structure and embedded decoupling capacitors are significantly smaller than the two separate devices of FIG. 2A. FIG. 3B shows a circuit diagram corresponding to the device of FIG. 3A. As shown, the source region of this PFET device 200 is connected to a positive power supply 120 and its gate region 202 is connected to an input terminal 122. The source region of this NFET device 210 is connected to the ground potential 124 and its gate region 212 is connected to the input terminal. The non-electrode region of the PFE device 200 and the drain region of the NFET 210 are connected to the output terminal 128 in common. Figure 3B further shows the OPC structures 230 and 240. The connection of this OPC structure is shown in Figure 3B. More specifically, the OPC structure 240 is connected to the ground potential, and -11-this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 582111 A7 B7 V. Description of the invention (8) 〇 PC structure 230 connection To positive power supply. Although FIG. 3A depicts that each of the OPC structures 230 and 240 preferably has the same width as the corresponding gate region, the outer OPC structures 230 and 240 can be made wider or several more can be added. For the same space as the design in Figure 2A, it provides better decoupling of the power supply. Fig. 4 is a partial cross-section through a part of the chip 105 and the embedded decoupling capacitor 66. The upper capacitor plate 68 is preferably made of gate polysilicon. The bottom plate 62 of the capacitor is a silicon bump and is preferably grounded. The capacitor dielectric is a gate dielectric. As such, capacitors do not require a separate dielectric. This capacitor uses the same dielectric layer as NFETs and PFETs. Figure 4 shows two gate regions 64 and one of the embedded capacitor OPC structures 66. As indicated by the symbol AA @, this OPC structure maintains the same spacing between adjacent gates. There are several benefits to embedding this capacitor in a polysilicon OPC structure. First, embedded capacitors eliminate the need for large capacitors and require less on-chip space. The vacated space can then be filled with more cells so that the chip can process a larger amount of data at a faster rate. Secondly, the integration of the OPC structure and decoupling capacitors makes the design methodology easier. The decoupling capacitors are added at the device layout time, either simply according to the size of the device or according to designer-specific parameters in the circuit diagram. This leads to optimized placement and density compared to placement of individual components later. As a result, the present invention provides less series resistance between the decoupling capacitor and the device than conventional individual decoupling capacitors. This can increase the benefits of decoupling capacitors, especially at high frequencies, by reducing the resistance / capacitor (RC) delay and improving the performance of the gate. Finally, the capacitors are built into an array, which can be -12- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 582111
讓去耦合電容器更緊密的符合陣列接近環境。 雖然本發明已經參考特定具體實例的說明， 為說明用途並且不是用來限制本發明的範疇。 修改及改變發生在熟習本技藝的人身上，而不 的精神與範疇。 圖式元件符號說明 此說明只做 不同的其他 令離本發曰月 10 緩衝單元 11 雜訊 12 電源供應 14 去耦合電容器 20 去耦合電容器 22 閘極 24 源洩極接觸 26 擴散區域 28 N-井 30 〇pc結構 38 正電源 40 〇pc結構 50 地電位 52 輸入端子 54 輸出端子 62 電容器底板 64 閘極區域 6 6 嵌入式電容器 -13-Allow the decoupling capacitors to fit the array closer to the environment. Although the invention has been described with reference to specific examples, it is for illustrative purposes and is not intended to limit the scope of the invention. Modifications and changes occur to those skilled in the art, but not to the spirit and scope. Symbol description of the graphic elements This description only makes other instructions from the original month 10 Buffer unit 11 Noise 12 Power supply 14 Decoupling capacitor 20 Decoupling capacitor 22 Gate 24 Source drain contact 26 Diffusion area 28 N-well 30 〇pc structure 38 positive power supply 40 〇pc structure 50 ground potential 52 input terminal 54 output terminal 62 capacitor base plate 64 gate area 6 6 embedded capacitor-13-
裝 訂 線 582111 A7 B7 五、發明説明（ 10 ) 68 電容器上板 100 P型場效電晶體 102 連串的閘極 103 連接線 104 N -井區域 105 連接線 106 源/汲極擴散區域 108 延伸閘極部分 109 源/沒極接觸區域 110 NFET裝置 112 N -型態場效電晶體 114 源/汲極擴散區域 116 延伸閘極部分 118 源/汲極接觸區域 120 正電源 122 輸入端子 124 地電位 200 PFET裝置 202 閘極區域 204 N-井區域 206 源/汲極擴散區域 207 側面延伸 208 源/汲極接觸區域 2 10 NFET裝置 -14- 本紙張尺度適用中國國家標準(CNS) A4規格(210 x 297公釐） 582111 A7 B7 五、發明説明（ 2 12 連串閘極 2 13 延伸部分 2 14 源/沒極接觸區域 2 16 擴散區域 2 17 側面延伸 23 0 〇P C結構 240 〇PC結構 -15- 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐） 裝 訂 線Binding line 582111 A7 B7 V. Description of the invention (10) 68 Capacitor top plate 100 P-type field effect transistor 102 Serial gate 103 Connection line 104 N-well area 105 Connection line 106 Source / drain diffusion area 108 Extension gate Electrode section 109 source / non-contact region 110 NFET device 112 N-type field effect transistor 114 source / drain diffusion region 116 extended gate portion 118 source / drain contact region 120 positive power source 122 input terminal 124 ground potential 200 PFET device 202 Gate area 204 N-well area 206 Source / drain diffusion area 207 Side extension 208 Source / drain contact area 2 10 NFET device -14- This paper size applies to China National Standard (CNS) A4 specifications (210 x 297 mm) 582111 A7 B7 V. Description of the invention (2 12 series of gates 2 13 extension 2 2 source / inverted contact area 2 16 diffusion area 2 17 side extension 23 0 〇PC structure 240 〇PC structure -15- This paper size applies to China National Standard (CNS) A4 (210X297mm) gutter