JP2001244267A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring structure in which delay in wiring is improved and in which a low power consumption and a high speed are made compatible, by a method wherein the circuit layout and the wiring structure of a conventional CMOS logic circuit are not changed and the lamination constitution of a wiring layer is not changed. SOLUTION: A logic wiring layer 1 and global wiring layers 2, 3 are laminated on a semiconductor substrate 10 from the lower part via an insulating film in the piling-up direction. The interval between the local wiring layer 1 and the global wiring layers 2, 3 is made larger than the layer interval between the global wiring layers 2, 3. In the provided semiconductor device, a driving voltage which drives the global wiring layers 2, 3 is made lower than a driving voltage which drives the local wiring layer 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor logic circuit having a multilayer wiring structure that achieves both low power consumption and high speed.

[0002]

2. Description of the Related Art Large-scale integrated semiconductor logic circuits composed of CMOS transistors have a finer semiconductor element. On the other hand, the chip size is increasing year by year, and the wiring length in the chip is getting longer.

As the length of wiring in a chip increases, the wiring resistance and wiring capacitance become larger than the channel resistance and diffusion layer capacitance of a transistor for driving wiring. Then, the operation speed of the circuit is determined by the product of the resistance of the wiring and the wiring capacitance, so that the operation speed of the device does not increase no matter how fast the semiconductor element such as a transistor becomes.

[0004] For this reason, the operating speed of the circuit can be improved by increasing the thickness and width of the wiring to reduce the resistance, and increasing the spacing between the wirings to reduce the capacitance of the wiring. However, simply increasing the film thickness of the wiring and widening the wiring interval are not suitable for wiring a logic circuit with a higher degree of integration.

Therefore, as a wiring structure suitable for a highly integrated logic circuit, there is a multilayer wiring structure having a plurality of wirings on a semiconductor chip. Of the logic circuits formed on the semiconductor chip, wiring between adjacent logic circuits is performed by a lower local wiring having a finer wiring pitch, and wiring between separated logic circuits is performed by an upper global wiring. In the global wiring, the wiring film thickness and the wiring width are made larger than the local wiring, and the wiring interval is widened.
No. 13590).

However, the clock frequency of a logic circuit increases with scaling of miniaturization, and the number of wirings in a wiring layer also increases. Therefore, even in the above-described multilayer wiring structure, the power required for charging and discharging the capacitance of the wiring layer greatly increases. There's a problem.

[0007] In the conventional multilayer wiring structure, it is difficult to reduce the power required for charging and discharging the wiring capacitance while improving the wiring delay without increasing the number of wiring layers.

[0008]

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned problems, and has been made without significant changes in the circuit layout and wiring structure of a CMOS logic circuit.
It is an object of the present invention to provide a semiconductor device which reduces wiring delay and achieves both low power consumption and high speed.

[0009]

According to a first aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; a semiconductor element circuit formed on the semiconductor substrate; and an insulating film on the semiconductor substrate. A first wiring layer electrically connected to the semiconductor element, a second wiring layer formed on the first wiring layer via an insulating film, and a second wiring layer formed on the second wiring layer. A third wiring layer formed with an insulating film interposed therebetween, wherein the wiring thickness of the first wiring layer is equal to the wiring thickness of the second wiring layer and the wiring thickness of the third wiring layer. Smaller than the film thickness,
A semiconductor device is provided, wherein a distance between the first wiring layer and the second wiring layer is larger than a distance between the second wiring layer and the third wiring layer.

In this case, it is preferable that the first wiring layer, the second wiring layer, and the third wiring layer are stacked in this order without any intervening other wiring layers.

At this time, if the distance between the first wiring layer and the second wiring layer is H1, and the distance between the second wiring layer and the third wiring layer is H2, H1 ≧ 1. It is preferable to be 7 × H2.

The distance between adjacent wirings in the first wiring layer is smaller than the distance between adjacent wirings in the second wiring layer and the distance between adjacent wirings in the third wiring layer. Is preferred.

Preferably, the wiring width of the first wiring layer is smaller than the wiring width of the second wiring layer and the wiring width of the third wiring layer.

Further, the wiring of the first wiring layer and the second
It is preferable that the wiring of the wiring layer has a relationship of crossover layout.

Further, the voltage amplitude of at least one pair of adjacent wires of the second wiring layer and the voltage amplitude of at least one pair of adjacent wires of the third wiring layer are at least one pair of adjacent wires of the first wiring layer. It is preferable that the voltage amplitude is smaller than the voltage amplitude of the adjacent wiring.

Further, when the power supply voltage of said semiconductor device is to V _DD, it is preferable voltage amplitude of the first wiring layer is also V _DD.

Further, the voltage amplitude of the second wiring layer is
V₁Then, the first wiring layer and the second wiring layer
The distance is a distance between the second wiring layer and the third wiring layer.
(V _DD/ V₁)^1.5Preferably, it is larger than twice.

Further, it is preferable that the first wiring layer is directly connected to the semiconductor element.

It is preferable that the voltage amplitude of at least one pair of adjacent wirings of the second wiring layer is 0.48 V _DD or less.

According to a second aspect of the present invention, a semiconductor substrate, a semiconductor element formed on the semiconductor substrate, and an insulating film formed on the semiconductor substrate via an insulating film and electrically connected to the semiconductor element A first wiring layer; a second wiring layer formed on the first wiring layer via an insulating film; and a third wiring formed on the second wiring layer via an insulating film. Layers and
A fourth wiring layer formed on the third wiring layer via an insulating film, wherein the first wiring layer has a wiring thickness of the second wiring layer, the third wiring And the distance between the first wiring layer and the second wiring layer is smaller than the third wiring layer and the fourth wiring layer.
The semiconductor device is characterized by being larger than the distance to the wiring layer.

At this time, it is preferable that the first wiring layer, the second wiring layer, and the third wiring layer are stacked in this order without any intervening other wiring layers.

At this time, if the distance between the first wiring layer and the second wiring layer is H1, and the distance between the third wiring layer and the fourth wiring layer is H2, H1 ≧ 1. It is preferable to be 7 × H2.

The distance between adjacent wirings in the first wiring layer is smaller than the distance between adjacent wirings in the second wiring layer and the distance between adjacent wirings in the third wiring layer. The semiconductor device according to claim 7, wherein:

Further, it is preferable that a distance between adjacent wirings in the first wiring layer is smaller than a distance between adjacent wirings in the fourth wiring layer.

The wiring of the first wiring layer and the second wiring
It is preferable that the wiring of the wiring layer has a relationship of crossover layout.

The voltage amplitude of at least one pair of adjacent wires in the second wiring layer, the voltage amplitude of at least one pair of adjacent wires in the third wiring layer, and the voltage amplitude of at least one pair of wires in the fourth wiring layer. The voltage amplitude of the adjacent wiring is
It is preferable that the voltage amplitude is smaller than a voltage amplitude of at least a pair of adjacent wires in the first wiring layer.

Further, when the power supply voltage of said semiconductor device is to V _DD, it is preferable voltage amplitude of the first wiring layer is also V _DD.

Further, the voltage amplitude of the second wiring layer is
V₁Then, the first wiring layer and the second wiring layer
The distance is the distance between the third wiring layer and the fourth wiring layer.
(V _DD/ V₁)^1.5Preferably, it is larger than twice.

Further, it is preferable that the first wiring layer is directly connected to the semiconductor element.

Further, it is preferable that the voltage amplitude of at least one pair of adjacent wirings of the second signal wiring layer is 0.48 V _DD or less.

In the present invention, the power supply voltage is set to V _DD and the second
The voltage amplitude of the global wiring composed of the first signal wiring layer and the third signal wiring layer is set to a voltage V ₁ smaller than V _DD, and the distance between the first signal wiring layer (local wiring layer) and the second signal wiring layer is set to be smaller.
H1, the distance between the second signal wiring layer and the third signal wiring layer is H
Assuming that H2 is larger than H2 so that H1> 0.4 × H2 (V _DD / V ₁ ), the voltage noise of the voltage amplitude V _DD in the local wiring layer is globally reduced by capacitive coupling. It is possible to prevent malfunction due to riding on the wiring.

Further, according to the present invention, the charge and discharge in the global wiring layer can be reduced by making the voltage amplitude in the global wiring layer smaller than the voltage amplitude in the local wiring layer, so that lower power consumption can be realized. .

Further, the present invention provides a semiconductor substrate, a semiconductor element formed on the semiconductor substrate, and a local wiring layer formed on the semiconductor substrate via an insulating film and electrically connecting the semiconductor element. A first wiring layer formed on the local wiring layer via an insulating film and electrically connected to the local wiring layer, and a second wiring layer formed on the first wiring layer.
Wherein the wiring thickness of the local wiring layer is smaller than the wiring thickness of the first wiring layer and the wiring thickness of the second wiring layer. A semiconductor device is provided, wherein a distance to a wiring layer is larger than a distance between the first wiring layer and the second wiring layer.

[0034]

Preferred embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a cross-sectional view of a semiconductor device according to Embodiment 1 of the present invention. FIG. 4 shows a plane layout of each layer when the internal structure of a wiring layer is viewed obliquely from above from above. . In FIG. 4, in order to make the wiring layer easier to understand, the semiconductor substrate region and the contact are omitted, and the connection relation between the contact and the wiring is indicated by a dotted line.

In this embodiment, the wiring layers are a local wiring layer (wiring layer 4 and first wiring layer 1) and a global wiring layer (second wiring layer 2 and third wiring layer 2) formed on the local wiring layer. Wiring layer 3). The distance between the global wiring layer and the local wiring layer should be wider than the distance between the global wiring layers, the wiring thickness of the global wiring layer should be larger than the wiring thickness of the local wiring layer, and the voltage amplitude of the global wiring layer should be smaller than that of the local wiring layer. It is lower than the voltage amplitude of the layer.
The wiring layer 1 is a first wiring layer, the wiring layer 2 is a second wiring layer, and the wiring layer 3 is a third wiring layer. The wiring layer 4 is formed below the first wiring layer 1 and functions together as a local wiring layer. This will be described in more detail below.

As shown in FIG. 1, the semiconductor substrate 10 is a boron or indium is formed in p-type semiconductor formed of impurity concentration 10 ¹⁴ to 10 ¹⁸ cm ^-3 doped for example silicon.

On the p-type semiconductor substrate 10, a source
An MISFET including a drain region 9, a channel region sandwiched between these regions, and a gate electrode 8 formed on the channel region via a gate insulating film is formed.
A plurality of these MISFETs are formed, and constitute the semiconductor logic circuit 100.

Of the MISFETs, an n-type MISFET
Is the impurity concentration 10¹⁹cm^-3From the following p-type impurity doped regions
Channel and a silicon oxide film with a thickness of 10 nm or less
A gate insulating film made of silicon nitride film and this gate insulating film
Impurity concentration formed on the edge film 10 ¹⁹cm^-3The above P (phosphorus)
Or a polysilicon gate electrode doped with As (arsenic)
8 and the impurity concentration formed on both sides of the gate electrode 8
Ten¹⁹cm^-3Above, P (phosphorus) or As (arsenic) was added.
A source comprising an n-type semiconductor region having a depth of less than 0.5 μm
And a drain region 9. Also p-type MISFE
T is also formed on the semiconductor substrate 10 in the same manner, and the n-type
Forming the switch element of the complementary semiconductor logic circuit with ET
I have.

These n-type MISFETs and p-type MISFE
An element isolation region 11 made of a silicon oxide film has a depth of 0.05 μm or less on the semiconductor substrate 10 where no T is formed.
It is formed with a thickness of 1 μm and separates the individual MISFETs 100.

MISFET1 constituting these logic circuits
The wiring layer 4 is formed on the upper portion of the semiconductor layer 00 via an interlayer insulating film 13. The first wiring layer 1 is formed on the wiring layer 4 via an interlayer insulating film 13. Wiring layer 4 and first
Wiring layer 1 constitutes a local wiring layer. The second wiring layer 2 is formed on the first wiring layer via an interlayer insulating film 13. A third wiring layer 3 is formed on the second wiring layer 2 via an interlayer insulating film 13. The second wiring layer 2 and the third wiring layer 3 constitute a global wiring layer. The interlayer insulating film 13 is made of, for example, a silicon oxide film or a silicon nitride film, and is also formed between the wirings of the wiring layer 4, the first wiring layer 1, the second wiring layer 2, and the third wiring layer 3.

Here, the local wiring layer is formed of the semiconductor substrate 10
Although the connection is made to the transistors forming the semiconductor logic circuit 100 above, if there are two or more wiring layers connected to the transistors making up the semiconductor logic circuit 100, the local wiring layers in the present invention are two layers from the bottom layer. Up to the target. The global wiring layer is formed on the local wiring layer, and is connected to the local wiring layer, but is formed on the local wiring,
When there are two or more wiring layers connected to the local wiring layer, the global wiring layer in the present invention covers two layers from the uppermost layer. Therefore, to apply the present invention, a multilayer wiring layer having at least one local wiring layer and two global wiring layers is required. Normally, in order to avoid the increase of the wiring capacitance and to provide a contact at an arbitrary position of an element or a wiring, if one layer is a wiring extending in the X direction, for example, the other layer is formed in the Y direction perpendicular to the X direction. Stretched wiring is performed. That is, in order to give each of the local wiring layer and the global wiring layer a degree of contact freedom, a multilayer wiring of four or more layers is required. Further, the distance between the local wiring layer and the global wiring layer described in the present invention is the distance between the uppermost local wiring layer and the lowermost global wiring layer.

Note that the wiring refers to a signal wiring used for signal transmission of a semiconductor logic circuit. W, Cu, Al, or AlCu can be used as the wiring material of each of the wiring layers 1, 2, 3, and 4.

A wiring contact 7 is formed on the source / drain region 9 of the MISFET on the semiconductor substrate 10 and is connected to the wiring layer 4 among the local wiring layers. This wiring contact 7 is made of W, Ru, TaN, T
i, TiN, Cu, Al or AlCu, having a height of 0.1 μm to 2 μm and a diameter of 0.03 μm to 1 μm.

The wiring width of the wiring layer 4 is set so that the diameter of the contact 7 is reduced by minimizing the misalignment with the MISFET formed on the semiconductor substrate 10. Thus, the integration density of the MISFET is improved. Wiring layers 1, 2,
The contacts 5 and 6 in 3 may be larger than this.

As described above, the wiring of the wiring layer 4 is used as a relatively short wiring connecting adjacent semiconductor logic circuits, and is a local wiring layer for improving the degree of integration.
Therefore, the minimum line width of the wiring layer 4 is 0.03 μm to 1 μm.
m, and the minimum distance between the wiring layers is 0.03 μm as in the case of the wiring width.
It is desirable that the thickness be 1 μm to improve the integration density.

A wiring contact 5 is formed on the wiring layer 4 and is connected to the first wiring layer 1 which is another local wiring layer. This wiring contact 5
W, Ru, TaN, Ti, TiN, Cu, Al or A
1 Cu, height 0.03 μm-1 μm, diameter 0.0
It is 3 μm to 1 μm. The diameter of this wiring contact 5 is
It is desirable to make the diameter equal to or larger than the diameter of the wiring contact 7 in order to reduce the resistance of the contact portion of the first wiring layer 1.

The first wiring layer 1 extends in a direction perpendicular to the wiring layer 4 so that the semiconductor logic circuit region 100 arranged at random positions on the semiconductor substrate 10 can be arbitrarily wired. The first wiring layer 1 is also formed with the same film thickness and line width as the wiring layer 4, so that the minimum layout width of the semiconductor logic circuit 100 is made equal in a two-dimensional direction parallel to the wiring lamination plane, and the circuit arrangement is reduced. This is desirable for facilitation and for improving the integration density of wiring.

On the first wiring layer 1, an interlayer insulating film 13 is entirely deposited so as to have a height H1, on which a second wiring layer 2 is formed. On the second wiring layer 2, an interlayer insulating film 13 is entirely deposited so as to have a height H2, and a third wiring layer 3 is formed thereon. Second wiring layer 2
The third wiring layer 3 and the third wiring layer 3 together constitute a global wiring layer. The global wiring layer performs wiring at a position relatively longer than the local wiring layer. Also, the second wiring layer 2
And the third wiring layer 3 extend in a direction orthogonal to each other, and arbitrarily wire the semiconductor logic circuit region 100 and local wires arranged at random positions.

On the second wiring layer 2, a wiring contact 6
Is formed and connected to the third wiring layer 3. The wiring contact 6 has a height H2 and a diameter of 0.05 μm to 3 μm.
Therefore, it is made of W, Ru, Ti, TiN, TaN, Cu, Al or AlCu so that the diameter is equal to or larger than the diameter of the wiring contact 5.

Although not shown in FIGS. 1 and 4,
Between the local wiring layer and the global wiring layer, that is, between the first wiring layer 1 and the second wiring layer 2, a height H1, a diameter of 0.05 μm to 3 μm, W, Ru, TaN, Ti, Ti
Wiring contacts made of N, Cu, Al or AlCu are formed, and the layers are connected to each other.

The first wiring layer 1 and the second wiring layer 2 are formed so as to extend in an orthogonal direction rather than in a parallel direction. Desirable to reduce crosstalk.

In the present invention, the wiring thickness T1 of the first wiring layer 1 and the wiring layer 4 which are local wiring layers is changed by the wiring thickness T2 of the second wiring layer 2 which is a global wiring layer and the third wiring layer. Smaller than the wiring thickness T3 of the layer 3 (T1 <T2, T1
3) Formed. The distance H1 between the local wiring layer and the global wiring layer, that is, the distance H1 between the wiring layer 1 and the wiring layer 2 is determined by the distance H2 between the second wiring layer 2 and the third wiring layer 3 in the global wiring layer. Larger than (H1> H2)
are doing. Also, the second wiring layer 2 in the global wiring layer
And the wiring distances S2 and S3 between the third wiring layer 3 and the wiring distance S between the first wiring layer 1 and the wiring layer 4 which are local wiring layers.
1 (S1 <S2, S3). The wiring interval at this time means the minimum wiring interval in the wiring layer.

The minimum line widths W2 and W3 of the second wiring layer 2 and the third wiring layer 3 which are global wirings are larger than the minimum wiring width W1 of the local wiring (W1 <W2).
W3) formed.

As described above, the wiring resistance per unit length in the global wiring layer is reduced and the wiring capacitance is further reduced. Therefore, the product of the wiring resistance and the wiring capacitance in the global wiring layer is reduced, and the clock signal is reduced. It is possible to reduce the amount of charge / discharge associated with the high-speed operation and reduce power consumption. Specifically, if the wiring width is doubled, the resistance is reduced by half. If the wiring layer interval is doubled, the capacitance is reduced by half. If the wiring interval is doubled, the capacitance is reduced by half. If the wiring film thickness is doubled, the resistance is reduced by half.

When Al or Cu is used as the wiring material of the wiring layers 1, 2, 3, and 4, and an insulating film having a dielectric constant of 4 or less is used as the interlayer insulating film 13, the delay time due to the wiring is optimized. In the structure in which the wirings are arranged with the highest integration density, 0.2 × S2 <W2 <5 × S2 and 0.2 × S2 <T
2 <5 × S2, 0.2 × S3 <W3 <5 × S3, 0.2 ×
The wiring structure is optimized in the range of S3 <T3 <5 × S3.

The distance H1 between the first wiring layer 1 and the second wiring layer 2 is larger than the distance H2 between the second wiring layer 2 and the third wiring layer 3 (H1> H2). So, the first
To prevent capacitive coupling between the first wiring layer 1 and the second wiring layer 2,
Crosstalk noise can be prevented from being generated in the wiring layer 2.

FIG. 2 shows that the distance H1 between the first wiring layer 1 and the second wiring layer 2 is smaller than the distance H2 between the second wiring layer 2 and the third wiring layer 3 (H1 <H2). FIG. 10 is a diagram showing a multilayer wiring structure according to a conventional comparative example in such a case. Figure 1 shows other structures
This is the same as the structure shown in FIG.

Also in the structure of the comparative example, the second wiring is required to reduce the wiring resistance per unit area of the global wiring layer.
The wiring film thickness T2 of the wiring layer 2 is larger than the wiring film thickness T1 of the first wiring layer 1 (T1 <T2). Further, in order to reduce the capacitance between wirings in the global wiring layer, the minimum wiring spacing in the wiring layer is made equal or larger as the structure becomes higher. The spacing between the wiring layers 1, 2, 3, and 4 is
By making the distance between the wiring layers 1, 2, 3, and 4 larger than the minimum distance between the wiring layers, the wiring capacitance caused between the wiring layers is reduced.

However, in this structure, crosstalk noise occurs in the second wiring layer 2 due to capacitive coupling between the first wiring layer 1 and the second wiring layer 2. In this structure, when the signal voltage of the second wiring layer 2 and the third wiring layer 3, which are global wiring layers, is reduced, noise is large and it is difficult to transmit a signal correctly.

FIG. 3 is a diagram for explaining a method of driving the multilayer wiring structure according to the present invention, and is a diagram for explaining a rise in voltage of the second wiring layer 2 due to a voltage pulse on the first wiring layer 1. FIG.
2 shows a structure above the first wiring layer.

Here, the first wiring layer 1 and the third wiring layer 3 are formed in the second wiring layer 3 in order to reduce the crosstalk as much as possible.
Is formed in a direction orthogonal to the wiring layer 2. Further, the first wiring layer 1 is densely formed with a wiring film thickness T1, a wiring width W1, and a wiring interval S1, and a step pulse of GND before a certain time and _VDD after a certain time is applied. Shall be.

In FIG. 4, all the wirings in the first wiring layer 1 are laid below the second wiring layer 2 so that the logic circuits operating at the amplitude V _DD simultaneously have the wiring voltage V _DD. Corresponds to the case of being driven. Further, the third wiring layer 3 includes:
The wirings are densely formed with a wiring film thickness T3, a wiring width W3, and a wiring interval S3, and each wiring is grounded. The second wiring layer 2 is formed with a wiring thickness T2, a wiring width W2, and a wiring interval S2. One wiring is in a floating state, and a voltmeter 14 is connected to one end. It is assumed that the ground is removed except for one of the wires.

In FIG. 3, first, 0 is added to the first wiring layer 1.
When a step pulse from V to V _DD is applied, the voltage of the second wiring layer 2 increases by ΔV due to capacitive coupling. Here, the present inventor newly found that ΔV / V _DD coincides with a value obtained by the following relational expression.

ΔV / V _DD = [{0.0261−0.0945 (T2 / S2)} (H2 / S2) + 0.3657−0.0541 (T2 / S2)] × (H1 / S2) ^{− {0.65 + 0.05 (T2 / S2) }} Formula (1) where 1 ≦ (H1 / S2) ≦ 3, 0.5 ≦ (T2 / S2) ≦ 3, and 1/4
≦ (S1 / S2) ≦ 1/2, and is obtained by the equation (1) within an error range of ± 20% in the range of W1 ≦ 2 × T1 and W3 ≦ 2 × T3.

Here, let us consider a case where the second wiring layer 2 and the third wiring layer 3 are formed with the same wiring width, wiring thickness, and wiring interval, and H2 = T2 = S2, and H1 = If H2,
From equation (1), ΔV / V _DD = 0.24, and by capacitive coupling,
A voltage rise of ΔV = 0.24 V _DD occurs in the wiring 2.

The signal applied to the first wiring layer 1 is applied to V _DD
When the step pulse is changed from 0 V to 0 V, a voltage drop of −0.24 V _DD occurs in the second wiring layer 2.

Therefore, the voltage amplitude of the second wiring layer 2 must be at least 2 × 0.24 V _DD = 0.48 V _DD . If the voltage of the wiring layer 2 is made to have a low voltage amplitude below this voltage, a malfunction occurs. I will.

[0069] Therefore the H1 larger than H2, in particular, <as V _DD, H1> the second signal amplitude of the wiring layer _{2 V 1 (V DD / V} 1)
^1.5 × H2. In this case, according to the equation (1), when H1 = H2 and S2 and T2 are the same, at least in the range of 0.5 ≦ (T2 / S2) ≦ 3, ΔV / V _DD ≦ 0.
It becomes 24 × (V ₁ / V _DD ).

Therefore, in the present invention, the voltage rise due to the capacitive coupling can be reduced from 0.24 V _DD to 0.24 V ₁ or less, and the crosstalk can be suppressed to (V ₁ / V _DD ) times or less as compared with the comparative example. it can. Further, suppressing the crosstalk to (V ₁ / V _DD ) times or less also holds true in a general wiring layout in which the wiring width and the wiring interval of the first wiring layer 1 are changed.

[0071] in the second wiring layer 2 in and third wiring layers 3 is a global wiring layer as described above, to the voltage amplitude of the signal lines of the minimum wiring interval contiguous in layers V ₁ or less in crosstalk voltage wiring adjacent second wiring layer within 2 the voltage amplitude of the signal lines of the minimum wiring interval contiguous in the layer compared to the case where the below V _DD, (V ₁ / V _DD ) times or less.

In these methods, it is necessary to change the wiring line width and the wiring interval of the second wiring layer 2 and the third wiring layer 3, and the distance between the second wiring layer 2 and the third wiring layer 3. There is no.

By using the above in combination, in the present invention, all the crosstalk voltages due to the capacitive coupling of the second wiring layer 2 and the third wiring layer 3 are reduced by the second wiring layer 2 and the third wiring layer 3 of the comparative example. Compared to the case where the wiring included in the wiring layer 3 is driven with the V _DD amplitude, it can be suppressed to (V ₁ / V _DD ) times or less. According to this method, the voltage amplitude of the wiring included in the second wiring layer 2 and the third wiring layer 3 in the in-chip wiring can be suppressed to (V ₁ / V _DD ) times or less of the comparative example.

Further, by applying the same idea to a wiring layer higher than the third wiring layer 3, the voltage amplitude of the wiring can be suppressed to (V ₁ / V _DD ) times or less for the wiring layer further above. Can be.

In the configuration shown in FIG. 1, when the voltage amplitude of the third wiring layer 3 is, for example, V _DD and the logic voltage amplitude of the second wiring layer 2 is, for example, V ₁ lower than V _DD , If the distance between the second wiring layer 2 and the third wiring layer 3 is kept at H2 which is smaller than H1, the crosstalk voltage amplitude from the third wiring layer 3 to the second wiring layer 2 is ± 0.24 V _DD Therefore, the receiver of the second wiring layer 2 malfunctions, and the effect is not sufficiently obtained. Therefore, a sufficient effect can be obtained by suppressing the voltage amplitude of the third wiring layer 3 facing the second wiring layer 2.

The second wiring layer 2 and the third wiring layer 3, which are global wiring layers, and the wiring layers above them,
Usually, an external input / output terminal driven by a voltage with a _VDD amplitude is often provided. The crosstalk from the terminal of the signal having the _VDD amplitude to the low-voltage wiring can be reduced by, for example, the wiring structure shown in FIG.

FIG. 5 is a bird's-eye view of a signal wiring structure having a _VDD amplitude passing through the second wiring layer 2 and the third wiring layer 3. The description of the same symbols as in FIG. 4 is omitted.

In the second wiring layer 2 and the third wiring layer 3,
Wirings driven by the V _DD amplitude are a wiring 15 and a wiring 16, which are connected to an input circuit and an output circuit of a wiring layer in a higher layer (not shown). These input circuits and output circuits to the outside can be formed by elements arranged very close to each other, and the wiring in the chip can be sufficiently realized by using a local wiring layer.

Therefore, as shown in FIG. 5, the area of wiring 15 and wiring 16 penetrating through second wiring layer 2 and third wiring layer 3 has a minimum area sufficient to form a contact to a further upper wiring. Is fine. Therefore, the capacitive coupling to the adjacent wiring in the second wiring layer 2 or the third wiring layer 3 is also caused by the wiring 15,
Since the cross-sectional area of the wiring 16 is small, it can be reduced. As a result, the crosstalk can be kept very small almost in proportion to the cross-sectional area of the wiring, as compared with the case where the wirings 15 and 16 are formed long in parallel in the global wiring layer.

In FIG. 5, the wirings 15 and 16
A wiring 17 having a constant potential such as GND or _VDD is formed adjacent to the wiring 15 and the wiring 1.
6 is shielded. It is desirable that the distance between the wiring 17 and the wirings 15 and 16 in the plane be the minimum wiring interval.

Further, for example, when the distance between the wiring 16 and the wiring 18 is constant, the wiring 17 included in the same layer as the wiring 16 is connected to the low-voltage amplitude wiring 18 in the same layer by the capacitive coupling of the wiring 16. Crosstalk is 1 when there is no wiring 17
It has been found from experiments that the crosstalk can be reduced to / 10 or less, and that the crosstalk can be reduced while forming the wiring densely.

Similarly, when the distance between the wiring 17 and the wiring 18 included in the same layer as the wiring 15 is constant, the crosstalk due to the capacitive coupling from the wiring 16 to the low-voltage amplitude wiring 18 in the same layer is obtained. Decrease. In this case, the distance between the wiring 15 and the wiring 18 is set to be k times larger than the minimum wiring spacing S2 of the wiring layer 2, so that the crosstalk generated in the wiring 18 is (1 / k) in the case where the wiring is arranged at the minimum wiring spacing. It was found that it can be reduced by a factor of two or less.

By using the above method, the crosstalk from the terminal of the signal having the _VDD amplitude to the low voltage wiring can be reduced.

The number of external input / output terminals is 1.9 × N ^0.5 [number] at most in the gate array as compared with the number of transistors, where N is the number of transistor gates. Incidentally, the gate array has the largest number of external input / output terminals with respect to the number of gates among the microprocessor, the static RAM, the dynamic RAM, and the gate array. In this case, compared to the chip total route number to 3 × N using a transistor, not more than 0.07% in 10 ⁶ or more transistors, N as the ratio for the total wiring number of transistors increases ^- Decrease by ^0.5 .

Here, the wiring area of the global wiring layer according to the bit line shielding method shown in FIG. 5 increases only at most about four times as much as the wiring area without the bit line shielding. Is the minimum wiring pitch of 2F,
36F ² about the area only occupies. So, for example,
If the wiring pitch is 2 μm, the area increase due to the bit line shield shown in FIG. 5 is 36F ² × (4-1) times to 1
In 00μm ² about, 10 ⁶ × be in accordance with all input and output pins
0.07% × 100μm ² ~0.07mm ² than the area is small, the VLSI circuit chip is usually 10 mm ² or more percentage increase chip area is very small.

Further, in order to reduce the crosstalk from the terminal of the signal having the V _DD amplitude to the low voltage wiring, the signal having the V _DD amplitude is passed through the first wiring layer 1 and the wiring layer 4 and the low voltage signal is passed through the second wiring layer 2. The same arrangement as that of FIG. 5 can be used for the first wiring layer 1 and the wiring layer 4 also when transmitting to the first wiring layer 2 and the third wiring layer 3.

Since this low-voltage wiring does not need to be connected to the first wiring layer 1 and the wiring layer 4 having other V _DD voltage amplitudes, the first wiring layer is similar to the wirings 15 and 16 in FIG. 1
In addition, in the wiring layer 4, the wiring can be formed in a rectangular shape having a small cross-sectional area.

Therefore, the capacitance coupling of the V _DD voltage amplitude in the first wiring layer 1 and the wiring layer 4 from the adjacent wiring is also reduced by the cross-sectional area of the low voltage wiring in the first wiring layer 1 and the wiring layer 4. Because it is small, it can be made smaller. As a result, the crosstalk can be kept very small almost in proportion to the wiring cross-sectional area as compared with the case where the wiring is formed long in parallel.

Next, FIG. 6 shows an example of a wiring drive circuit having a _VDD amplitude. 7 to 12 show examples of a low voltage amplitude circuit for driving a global wiring layer according to the present invention.

In FIG. 6 to FIG.
To INV11, for example, when the power supply voltage is V _DDCMOS inverter
From NAND1 to NAND2 and from NOR1 to N
Up to OR2, for example, if the power supply voltage is V_DDNAND circuit and NOR
The circuit is shown. Here, Cint indicates the wiring capacitance, and Ci
The part where nt is connected is the wiring, the wiring layer
Reference numerals corresponding to 1, 2, 3, and 4 are assigned.

In FIG. 6, the output of the CMOS inverter INV1 as the wiring driver is connected to one end of the wiring layer 1 or 4 having a capacitance of Cint, and the other end of the wiring is connected to the inverter INV2 as the wiring receiver. Connected to input.
As a result, the input voltage of V _IN is output to V _OUT through the wiring layer 1 or 4.

In the present invention, the _VDD wiring drive circuit shown in FIG. 6 may be used to drive the wiring layers 1 and 4 as local wiring layers, and there is no need to change the CMOS circuit from the wiring drive circuit.

The second wiring layer 2 and the third wiring layer 3, which are global wiring layers, use, for example, the low voltage amplitude circuit shown in FIG. FIG. 7 shows a so-called static sense amplifier circuit. For example, "Basics of VLSI System Design Circuit and Implementation", written by H. Bakoglu, translated by Kisaburo Nakazawa and Hiroshi Nakamura,
This is a circuit described in Maruzen Co., Ltd., published on March 30, 1995, pp. 184-198.

In this circuit, the n-type MISFET Qn1 serves as a wiring driver, and the p-type MISFET Qp1 and the inverter INV
3, INV4 and INV5 become wiring receivers.

When the n-type MISFET Qn1 is off, the wiring of the wiring layer 2 is charged by the p-type MISFET Qp1, but the inverter INV
When the voltage becomes slightly higher than the logical inversion voltage of 3, Qp1 turns off, charging stops, and the voltage of the wiring layer 2 remains at a value smaller than V _DD . When the n-type MISFET Qn1 is on, n
The voltage of the wiring layer 2 is clamped to a voltage determined by the channel resistance ratio of the p-type MISFET Qp1 and the p-type MISFET Qn1, and does not drop to 0V.

As described above, the voltage amplitude of the second wiring layer 2 is V _DD
Be a smaller V _1, it is possible to reduce the power for charging the second wiring layer 2 (V ₁ / V _DD) ^twice.

Here, this circuit uses V _DD as the power supply voltage.
In spite of using only the voltage, the voltage of the second wiring layer 2 can be suppressed higher than 0 V and lower than V _DD . In the circuit of FIG. 6 having a signal amplitude of V _DD , the threshold value of the n-type MISFET forming the inverter INV2 of the first stage of the wiring receiver is set to Vth
Assuming that the threshold voltage of the p-type MISFET is n and that the threshold voltage of the p-type MISFET is Vthp, the n-type MISFET and the p-type MISFET do not turn on when the input voltage of the inverter INV2 is equal to or lower than Vthn and equal to or higher than (V _DD -Vthp).
Even if the input voltage changes within this voltage range, the output voltage does not change, and an output delay occurs for the input signal.

For this reason, in FIG. 7, the transistor width of Qn1 and Qp1 is adjusted so that the voltage range of second wiring layer 2 is changed to n-type MISFET forming inverter INV3.
Pth which forms the inverter INV3
By setting the threshold value of the MISFET of Vthp to be equal to or less than (V _DD -Vthp), the delay of input / output caused by the dead zone caused by the threshold value of the transistor generated in the inverter of FIG. It can be reduced and can operate at higher speed. In fact,
The circuit of Fig. 7 is designed to have a voltage amplitude of 0.4V _DD ,
The delay time between _IN and V _OUT was examined. Set the transistor threshold to 0.2V _DD and set the transistor resistance at the end of the wiring driver to
Assuming that the delay time of the inverter with F / O = 1 is τ ₀ , V _IN
The delay time from _VOUT to _VOUT is 0.5 × Cint × R + 3 × τ ₀ or less, which is smaller than the 50% delay time 0.7 × Cint × R when the wiring layer 2 is driven by the CMOS inverter in FIG. It turned out that the speed can be increased in the area where the capacity Cint is dominant.

When the second wiring layer 2 is driven by the circuit of FIG. 7, the power consumption associated with charging and discharging of the wiring layer can be reduced to 16% of that of the CMOS inverter of FIG. Further, one long wire for transmitting a signal may be used as in the case of the circuit of FIG.
There is no increase in the number of wires in the global wiring layer. Of course, only the power supply voltage V _DD is required, so that a new power supply voltage line is not required.

In particular, the receivers shown in FIGS.
Now, a receiver transistor like the receiver shown in FIG.
Star threshold V_thnAnd V_thpOf dead zone due to
No voltage range. Therefore, this dead zone corresponds to the second wiring layer.
Even if the voltage amplitude of No. 2 is reduced, the wiring delay does not increase.
Where V_thnAnd V_thpIs 0.15 × V_DDAbove
The receiver using the CMOS inverter shown in Fig. 6
Desirable to reduce. Therefore, without increasing the wiring delay
And V₁≤V_DD-V_thp-V_thn≦ 0.7 × V_DDCan be
Thus, power consumption due to wiring charge / discharge can be reduced. this
Is, that is, H₁≧ (V _DD/ V₁)^1.5× H_Two≧ 1.7 × H_TwoIn the structure
Can be realized.

The drive circuit shown in FIG. 8 has an n-type MI instead of Qp1.
This is an example in which the SFET Qn2 is used, and Qn1 and Qn2 are transistors of the same conductivity, which facilitates matching.

The driving circuit shown in FIG.
_{The DD} / 2 precharge circuit has a driver for the second wiring layer 2 or the third wiring layer 3 on the left side of the second wiring layer 2 or the third wiring layer 3. The receiver for the wiring is on the right side of the second wiring layer 2 or the third wiring layer 3, and the voltage of the second wiring layer 2 or the third wiring layer 3 is V _DD / V _DD / 2. _{Operates with a} voltage amplitude smaller than _DD .

Here, Φ1 and Φ2 are two-phase non-overlapping clocks as shown in FIG.
At the time of igh, a precharge period for charging the wiring layer to approximately V _DD / 2 is performed, and when Φ2 is high, signal transmission is performed. By doing so, it is possible to reduce the direct current that exists when the transistor Qn1 is in the conductive state in the circuits of FIGS.

The circuit shown in FIG. 10 is a sense amplifier with a clock obtained by adding a clock to the static sense amplifier circuit shown in FIG. Even in this circuit, the transistor Qn
The DC current consumption that was present when 1 was conducting can be reduced.

The circuits shown in FIG. 9 and FIG.
It requires wiring for external clock inputs 1 and Φ2. When the high period of the V _IN input is long and wiring power consumption is a problem due to the turning on of the transistor Qn1 in the circuit of FIG. 7, for example, as shown in the circuit of FIG. What is necessary is just to use the circuit which becomes a pattern.

As described above, when the low voltage amplitude circuits shown in FIGS. 7 to 11 are used to drive the global wiring layer, the wiring delay time is reduced, and the long wiring for transmitting signals uses the drive circuit of FIG. In the same manner as in the case where the number of wirings is one, the number of wirings does not increase. Further, since only the power supply voltage is required to be _VDD , a new power supply voltage line is not required. Further, the increase in the circuit area is twice or less as compared with the case where the drive circuit of FIG. 6 is used for the global wiring layer.

Further, as in the driving circuit shown in FIG.
The signal delay can be improved by forming a repeater having a low voltage amplitude by dividing the long wiring into a plurality of parts and connecting the low voltage amplitude circuits of FIGS. 7 to 12 in series. If the wiring capacitance is more important than the wiring resistance, inverters INV10 and INV11 connected in series at the stage before the low-voltage swing circuit so that the size gradually increases
To form a cascade driver, the delay time can be improved. This cascade driver can be formed by a very close transistor arrangement, and the global layer can be formed as a low voltage swing circuit without increasing the number of global wiring layers of the low voltage swing circuit.

The configuration described above has the following features.

First, it is possible to simultaneously reduce power consumption and improve delay time due to wiring delay without adding the number of wiring layers. The power consumption is reduced because the wiring voltage amplitude of the global wiring layer is smaller than V _DD , the amplitude is V ₁ , the total capacity of the global wiring is Cu, the total capacity of the local wiring layer, the total junction capacity of the transistor, and the gate. the sum of the capacity as Cd, at the same clock frequency ^{_{(Cu × V 1 2 + Cd}} × V DD 2) / (Cu × V DD 2 + Cd
× V _DD ² ) power can be reduced. On this occasion,
At the same time, as described in detail using the drive circuit of FIG. 7, the wiring delay time is reduced to a maximum of 71%. Therefore, the circuit skew due to the wiring delay can be reduced, and a circuit with higher speed and less malfunction can be realized.

The operating voltage of the global wiring layer is set to V _DD
Since the voltage can be lower than that of the CMOS inverter, the current associated with switching can be smaller than that of the CMOS inverter, so that the current density of the global wiring layer can be reduced and the reliability problems such as electromigration and interlayer insulation can be reduced. .

Further, electromagnetic noise generated by the global wiring layer can be reduced, and power supply voltage fluctuation due to the electromagnetic noise and malfunction of the sense circuit can be prevented. Of course, with the reduction in power consumption, heat generation due to charge / discharge is reduced, thereby improving reliability due to reduced heat history of wiring, reducing the thickness of power wiring, reducing the proportion of power wiring, and reducing junction leakage of transistors. Can be reduced, and higher integration with higher reliability and lower leakage can be realized.

Further, since it is not necessary to add the number of wiring layers, there is no occurrence of defects due to additional layers such as defective interlayer connection, a decrease in reliability, and no significant layout change of wiring layers. There is no decline.

By simply replacing the wiring driver and the wiring receiver of the low logic voltage swing circuit, the conventional circuit design method and tool can be used as they are, and it is not necessary to deal with multiple power supply voltages and multiple signal amplitudes. That is, no change is required up to the logic design of the conventional circuit design, and even at the layout design level, if the design is performed according to the procedure shown in FIG. Yes, conventional CAD tools can be used.

FIG. 14 shows a method for realizing the circuit wiring of the present embodiment using a conventional layout design tool as it is. First, as indicated by reference numeral 20, a circuit layout is designed in which all the _VDD voltages are used without distinction between the global wiring layer and the local wiring layer.

First, a global wiring layer is selected, and wiring to be assigned to the global wiring layer is determined. Next, CA
The wiring belonging to the global wiring layer is extracted by using the D tool. Here, the wiring driver and the receiver used in the global wiring layer can be formed of adjacent elements, respectively, and the connection in the wiring driver and the receiver can be realized using only the local wiring layer.

When the local wiring layer has two or more wiring layers, the area increase of the low voltage amplitude wiring driver and receiver from the driver and receiver by the CMOS inverter is within twice, and the design rule is F. , 500F ² or less.

Further, in the case of forming a multilayer wiring in which the operation speed of the chip is limited by the wiring delay, the minimum area determined by the minimum dimension of the transistor is smaller than the chip area determined by the wiring, and the transistor arrangement has a margin. Is in a certain state. Therefore, when the global wiring layer and the local wiring layer extracted by the reference numeral 20 are allocated as the optimum arrangement, the layout of the local wiring layer near the low-voltage driver is maintained without changing the allocation between the global wiring layer and the local wiring layer. By correcting
Wiring delay can be speeded up.

Next, the dummy circuit arranged by reference numeral 22 is
If the wiring driver and the wiring receiver are replaced by the reference numeral 24, the layout is completed.

Further, in the static sense amplifier circuit shown in FIGS. 7 and 8, when the wiring capacity is 100 times or more the inverter capacity of the fan-out 1 as compared with the CMOS inverter circuit shown in FIG. 0.8 times or less. In this case, a wiring layout is designed by using the wiring driver and the wiring receiver formed by the CMOS circuit of FIG. 6, and the wiring driver and the receiver connected to the global wiring layer are changed in any layout of another wiring structure. Can be replaced with the present static sense amplifier circuit, and all can be easily designed for automation.
Of course, if the optimization shown in FIG. 14 is performed, the circuit area can be reduced as compared with the case where a wiring driver and a wiring receiver formed of a CMOS circuit are used. In this case, the lithography conditions and the mask of the global wiring layer can be used as they are, and if a conventional structural process is constructed, high speed and low power consumption can be realized at very low cost.

In the present invention, the change in the stacking direction of the wiring layers is only the interlayer film thickness between the global wiring layer and the local wiring layer as compared with the conventional method, and there is no increase in the number of manufacturing steps. . Also, between the global wiring layer and the local wiring layer, the conventional wiring line width, wiring interval, and interlayer film thickness can be kept as they are, and all crosstalk voltages generated from adjacent wiring in the vertical and horizontal directions (V ₁ / V _DD ) Can be scaled by a factor of two. Therefore, it is possible to use a wiring arrangement which has already undergone circuit verification and process verification in a circuit having a conventional structure.

The height of the wiring layer is the same as that of the first wiring layer 1 and the second wiring layer.
Only the height of the interlayer film between the wiring layer 2 and the
Since there is no need to increase the number of interlayer films in other wiring layers, the occurrence of defects due to film stress accompanying the increase in interlayer films can be reduced as compared with a case where the thickness of other wiring layers is also increased.

Next, when the low voltage swing circuit and the _VDD swing circuit are provided in the horizontal direction, it is necessary to suppress the logic voltage amplitude of the global wiring layer and the local wiring layer adjacent to the multilayer wiring of the low voltage swing circuit. Yes, for example, it is necessary to insert a layer of a constant voltage such as a power supply layer, but this method is not necessary, and the effective wiring area in the chip can be wider.

(Embodiment 2) FIG. 15 is a laminated sectional view of a wiring structure including a semiconductor substrate region of a semiconductor device according to Embodiment 2 of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

In the present embodiment, the third
A fourth wiring layer 12 is further formed on the third wiring layer 3 and the fourth wiring layer 12 is formed on the third wiring layer 3 and the fourth wiring layer 12. Is larger than the interval H2.

In FIG. 15, the portion below the second wiring layer 2 is the same as the structure described in the first embodiment, and a description thereof will be omitted.

On the second wiring layer 2, an insulating film 13 is entirely deposited so as to have a thickness larger than H1, and for example, a wiring layer made of W, Ru, Ti, TiN, Cu, Al and AlCu is formed. Contact 6 is formed. The diameter of the wiring contact 6 is equal to or larger than the diameter of the wiring contact 5.

Further, the wiring contact 6 is, for example,
A third wiring layer 3 made of W, Cu, Al, AlCu is formed. The film thickness of the third wiring layer 3 is larger than the film thickness of the first wiring layer 1, and lowers the wiring resistance per unit area on the laminated surface. Further, the wiring interval S3 in the third wiring layer 3 is formed to be larger than the wiring interval S1 in the first wiring layer 1, and the capacitance between the wirings included in the third wiring layer 3 is suppressed. The product of the wiring resistance and the wiring capacitance is reduced, and is used for wiring between circuit blocks farther than the first wiring layer 1. The wiring length of the third wiring layer 3 is longer than the wiring length of the first wiring layer 1. become longer.

Further, the minimum line width W3 of the third wiring layer 3 is made larger than the line width W1 of the first wiring layer 1 to reduce the wiring resistance. Second wiring layer 2 and third wiring layer 3
Are formed so as to extend in a direction orthogonal to each other and have the same film thickness and line width in order to increase the integration density of random block wirings.

Further, the second wiring layer 2 and the third wiring layer 3
It is preferable that the term “is formed to extend in the direction perpendicular to the direction parallel to the direction parallel to the direction in order to reduce crosstalk between wiring layers”.

Further, on the third wiring layer 3, the insulating film 1 is formed.
3 is deposited on the entire surface at the height of H2. For example, although not shown, W, Ru, Ti, TiN, TaN, Cu, A
1, wiring contacts between wiring layers made of AlCu are formed. The diameter of the wiring contact is equal to or larger than the diameter of the wiring contact 6.

Further, on the wiring contact, for example,
A fourth wiring layer 12 made of W, Cu, Al, or AlCu is formed. The film thickness of the fourth wiring layer 12 is larger than the film thickness of the first wiring layer 1 and lowers the wiring resistance per unit area on the laminated surface. Further, the fourth wiring layer 1
2 is the wiring interval S4 in the first wiring layer 1.
1, the capacitance between the wirings included in the fourth wiring layer 12 is suppressed, the product of the wiring resistance and the wiring capacitance is reduced, and the wiring between circuit blocks farther than the first wiring layer 1 is formed. The wiring length of the first wiring layer 12 is longer than the wiring length of the wiring 1.

The minimum line width W12 of the fourth wiring layer 12 is
Is larger than the minimum wiring width W1 of the first wiring layer 1,
Wiring resistance is reduced. It is preferable that the fourth wiring layer 12 and the third wiring layer 3 are formed so as to extend in a direction orthogonal to the direction in which the wiring layers are formed in parallel to each other in order to reduce crosstalk between the wiring layers. .

Here, in this embodiment, H2, which is one of the wiring layer intervals of the global wiring, is smaller than the distance H1 between the local wiring layer and the global wiring layer. Here, in particular, the second wiring layer 2 and the third wiring layer 3, the signal amplitude of the wiring layer 4 as _{V 1, H1> (V DD} / V 1) and ^1.5 × H2. Even with such a structure, the crosstalk from the first wiring layer 1 can be reduced to (V ₁ / V _DD ) times or less, and the logic voltage amplitude of the global wiring layer can be reduced to V ₁ . Of course, although not shown in FIG. 15, the fourth wiring layer 1
The minimum value of layer spacing further adjacent in the stacking direction in the upper layer than 2 as _{H2, H1> (V D D} / V 1) by satisfying ^1.5 × H2, all crosstalk due to capacitive coupling of the local interconnect layers ( (V ₁ / V _DD ) times or less, and the logic voltage amplitude of the global wiring layer can be reduced to V ₁ .

In the present embodiment, compared to the first embodiment,
Since the distance between the second wiring layer 2 and the third wiring layer 3 is large, the crosstalk between the second wiring layer 2 and the third wiring layer 3 can be further reduced.

In the present invention, the method of forming the element isolation film and the insulating film itself is not limited to the method of converting silicon into a silicon oxide film or a silicon nitride film, such as a method of implanting oxygen ions into deposited silicon or a method of depositing silicon. A method of oxidizing silicon may be used.

The gate insulating film and the interlayer insulating film 13 are
SiN film, amorphous carbon film, TiO ₂ or alumina, or tantalum oxide film, strontium titanate, barium titanate, lead zirconium titanate, HSQ (hydr
ogen silsesquioxane), MSQ (methyl silsesquioxan)
e), or PAE (poly arylene ether), polyimide,
Organic insulating films such as those described above, and a laminated film thereof may be used.

Although the p-type Si substrate is used as the semiconductor substrate 10, an n-type Si substrate or an SOI substrate SOI substrate may be used instead.
A silicon layer or a single crystal semiconductor substrate containing silicon such as a mixed crystal of SiGe and a mixed crystal of SiGeC may be used.

The gate electrode 8 is made of p-type polycrystalline Si or SiGe mixed crystal, or Al, TiN, TaN, Al, C
u or a laminated structure of these.

Although the example in which the trench element isolation 11 is formed has been described, for example, mesa etching or LOCOS element isolation may be used instead of the trench element isolation.

In addition, various modifications can be made without departing from the spirit of the present invention.

[0141]

According to the present invention, it is possible to provide a semiconductor device capable of reducing wiring delay and achieving both low power consumption and high speed without significantly changing the circuit layout and wiring structure of a CMOS logic circuit. it can.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of a semiconductor device of a comparative example.

FIG. 3 is a sectional view for explaining a method for driving the semiconductor device according to the first embodiment of the present invention;

FIG. 4 is a perspective view of the semiconductor device according to the first embodiment of the present invention;

FIG. 5 is a perspective view of the semiconductor device according to the first embodiment of the present invention;

FIG. 6 is a drive circuit diagram for driving a local wiring layer according to the present invention.

FIG. 7 shows a low-voltage drive circuit for driving a global wiring layer at a low voltage according to the present invention.

FIG. 8 shows a low-voltage driving circuit for driving a global wiring layer at a low voltage according to the present invention.

FIG. 9 shows a low-voltage driving circuit for driving a global wiring layer at a low voltage according to the present invention.

FIG. 10 shows a low-voltage driving circuit for driving a global wiring layer at a low voltage according to the present invention.

FIG. 11 shows a low-voltage driving circuit for driving a global wiring layer at a low voltage according to the present invention.

FIG. 12 shows a low-voltage driving circuit for driving a global wiring layer at a low voltage according to the present invention.

FIG. 13 illustrates a relationship between signal voltages for driving the semiconductor device of the present invention.

FIG. 14 is a flowchart illustrating a method for manufacturing a semiconductor device according to the present invention.

FIG. 15 is a sectional view of a semiconductor device according to a second embodiment of the present invention;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... 1st wiring layer 2 ... 2nd wiring layer 3 ... 3rd wiring layer 4 ... wiring layer 5 ... wiring contact 6 ... wiring contact 7 ... wiring contact 8 ... gate electrode 9 ... source / drain 10 ... semiconductor substrate 11: element isolation region 12: fourth wiring layer

Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat ゛ (Reference)

Claims (11)

[Claims] A semiconductor substrate, a semiconductor element formed on the semiconductor substrate, a first wiring layer formed on the semiconductor substrate via an insulating film, and electrically connected to the semiconductor element; A second wiring layer formed on the first wiring layer via an insulating film, and a third wiring layer formed on the second wiring layer via an insulating film; The wiring thickness of the first wiring layer is smaller than the wiring thickness of the second wiring layer and the wiring thickness of the third wiring layer. Wherein the distance is larger than the distance between the second wiring layer and the third wiring layer. 2. The semiconductor device according to claim 1, wherein said first wiring layer, said second wiring layer, and said third wiring layer are stacked in this order without intervening another wiring layer. Semiconductor device. 3. The distance between adjacent wirings in the first wiring layer is smaller than the distance between adjacent wirings in the second wiring layer and the distance between adjacent wirings in the third wiring layer. The semiconductor device according to claim 1, wherein: 4. The semiconductor device according to claim 1, wherein a wiring width of said first wiring layer is smaller than a wiring width of said second wiring layer and a wiring width of said third wiring layer. . 5. The voltage amplitude of at least one pair of adjacent wirings of the second wiring layer and the voltage amplitude of at least one pair of adjacent wirings of the third wiring layer are at least one pair of the first wiring layer. 2. The semiconductor device according to claim 1, wherein the voltage amplitude is smaller than a voltage amplitude of an adjacent wiring. 6. A semiconductor substrate, a semiconductor element formed on the semiconductor substrate, and a first wiring layer formed on the semiconductor substrate via an insulating film and electrically connected to the semiconductor element. A second wiring layer formed on the first wiring layer via an insulating film, a third wiring layer formed on the second wiring layer via an insulating film, A fourth wiring layer formed on the first wiring layer with an insulating film interposed therebetween, wherein the first wiring layer has a wiring thickness of the second wiring layer, the third wiring layer, and the third wiring layer. The distance between the first wiring layer and the second wiring layer is smaller than the wiring thickness of the fourth wiring layer, and the distance between the first wiring layer and the second wiring layer is larger than the distance between the third wiring layer and the fourth wiring layer. A semiconductor device characterized by the above-mentioned. 7. The semiconductor device according to claim 1, wherein the first wiring layer, the second wiring layer, the third wiring layer, and the fourth wiring layer are stacked in this order without any intervening other wiring layers. 7. The semiconductor device according to claim 6, wherein: 8. When a distance between the first wiring layer and the second wiring layer is H1, and a distance between the third wiring layer and the fourth wiring layer is H2, H1 ≧ 1.7. 7. The semiconductor device according to claim 6, wherein: XH2. 9. The space between adjacent wires in the first wiring layer is smaller than the space between adjacent wires in the second wiring layer and the space between adjacent wires in the third wiring layer. 7. The semiconductor device according to claim 6, wherein: 10. The voltage amplitude of at least one pair of adjacent wires in the second wiring layer, the voltage amplitude of at least one pair of adjacent wires in the third wiring layer, and at least one pair of voltage amplitudes in the fourth wiring layer. 7. The semiconductor device according to claim 6, wherein a voltage amplitude of the adjacent wiring is smaller than a voltage amplitude of at least a pair of adjacent wirings in the first wiring layer. 11. A semiconductor substrate, a semiconductor element formed on the semiconductor substrate, a local wiring layer formed on the semiconductor substrate via an insulating film, and electrically connected to the semiconductor element, A global wiring layer including a first wiring layer formed on the wiring layer via an insulating film and electrically connected to the local wiring layer and a second wiring layer formed thereon; The wiring thickness of the layer is smaller than the wiring thickness of the first wiring layer and the wiring thickness of the second wiring layer, and the distance between the local layer and the first wiring layer is the first wiring layer. A semiconductor device, wherein the distance is larger than the distance between the second wiring layer and the second wiring layer.