JP2000269319A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To effectively use the interiors of trench regions for a wiring, to contrive reduction in a chip size, to reduce the size of a cell pattern in the direction intersecting orthogonally a word line in the case where a semiconductor device is applied to the memory cell of a CMOS STRAM, and to enable the speedup of the STRAM in the device using a trench element isolation structure. SOLUTION: When trenches are formed on a semiconductor substrate 10 for selectively forming a plurality of trench isolation regions on the substrate 10, and an insulator 16 is buried in the trenches in the manufacturing method of a semiconductor device, the manufacturing method is provided with a first process for forming a cavity 17 on the insulator which is buried in the interior of at least the trench on one side of the trenches, a second process for opening a plurality of holes connected with the cavity 17 in the insulator, and a third process for burrying the insulator in the holes and the interior of the cavity 17.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a wiring formed in an isolation region of a trench structure and a method of forming the same, for example, a memory cell of a static semiconductor memory (SRAM). It is used for such purposes.

[0002]

2. Description of the Related Art FIG. 9 shows a CMOS (complementary insulated gate).
Having an array of static memory cells of the same type
2 shows an equivalent circuit of one memory cell in an S-type SRAM.

In the memory cell shown in FIG. 9, a first NMOS transistor TN1 for driving and a first NMOS transistor TN for load are used.
CMOS including the PMOS transistor TP1
Inverter and second NMOS transistor T for driving
N2 and second PMOS transistor TP2 for load
, The input nodes n1 and n2 and the output nodes n2 and n1 are cross-connected to each other.

The output nodes n2 and n1 of the two CMOS inverters are respectively connected to a pair of bit lines BL and / BL via transfer gate NMOS transistors TN3 and TN4. Each gate of the pair of transfer gate transistors TN3 and TN4 is commonly connected to a word line WL.

In FIG. 9, reference numeral 91 denotes the transistor T
N1 and TP1 gates and transistors TN2 and TP2
A first gate connection line connecting the respective drains.

Similarly, reference numeral 92 denotes the transistor TN2,
This is a second gate connection line connecting each gate of TP2 and each drain of transistors TN1 and TP1.

FIG. 10 shows an S using an STI (Shallow Trench Isolation) structure as an element isolation region.
10 schematically illustrates a conventional pattern of the memory cell of FIG. 9 in a RAM.

In FIG. 10, reference numerals 101 and 102 denote a first P-well region and a second P-well region selectively formed in a surface layer portion of a silicon substrate. Are formed in the first N-well region and the second N-well region. An element isolation region 105 having a trench structure is formed between these regions.

Reference numeral 106 denotes a first NMOS transistor TN
This is a first gate wiring serving as each gate electrode of the first and first PMOS transistors TP1, and is formed on the surface of the substrate via a gate insulating film (not shown).

Reference numeral 107 denotes a second NMOS transistor TN
A second gate wiring which becomes each gate electrode of the second and second PMOS transistors TP2, and is formed on the substrate surface via the gate insulating film.

Reference numeral 108 denotes a third gate wiring (a part of the word line WL) serving as each gate electrode of the pair of transfer gate transistors TN3 and TN4, which is formed on the substrate surface via the gate insulating film. I have.

In the first P-well region 101, below the first gate line 106 is a channel region of the first NMOS transistor TN1, and on both sides thereof are a drain region and a source of the first NMOS transistor TN1. An N + region serving as a region is formed.

In the second P-well region 102, below the second gate line 107 is a channel region of the second NMOS transistor TN2, and on both sides thereof, a drain region of the second NMOS transistor TN2. And an N @ + region serving as a source region is formed.

In the first P well region 101, below the third gate line 108 is a channel region of a third NMOS transistor TN3, and on both sides thereof, a drain region of the third NMOS transistor TN3. And an N @ + region serving as a source region is formed. in this case,
The N + region serving as the drain region of the first NMOS transistor TN1 is connected to one end region (N + region) of the third NMOS transistor TN3.

In the second P-well region 102, below the third gate line 108 is a channel region of the fourth NMOS transistor TN4, and on both sides thereof, a drain region of the fourth NMOS transistor TN4. And an N @ + region serving as a source region is formed. in this case,
The N + region serving as the drain region of the second NMOS transistor TN2 is connected to one end region (N + region) of the fourth NMOS transistor TN4.

In the first N-well region 103, below the first gate line 106 is a channel region of the first PMOS transistor TP1, and on both sides thereof, a drain region of the first PMOS transistor TP1. And a P + region serving as a source region is formed.

In the second N-well region 104, below the second gate line 107 is a channel region of the second PMOS transistor TP2, and on both sides thereof, a drain region of the second PMOS transistor TP2. And a P + region serving as a source region is formed.

Reference numeral 109 denotes a first NMOS transistor TN
A first drain wiring commonly connecting the drain regions of the first and first PMOS transistors TP1; this is a buried wiring in an interlayer insulating film (not shown) formed on the substrate including the gate wiring group It is formed as.

Similarly, reference numeral 110 denotes a second drain line commonly connecting the drain regions of the second NMOS transistor TN2 and the second PMOS transistor TP2, which is formed on the substrate including the group of gate lines. Is formed as a buried wiring in the formed interlayer insulating film (not shown).

Then, the first NMOS transistor TN
A first gate wiring 106 serving as each gate of the first and first PMOS transistors TP1, a second NMOS transistor TN2 and a second PMOS transistor TP
2nd drain wiring 1 which connects each drain of 2 in common
10 is connected by a first gate connection wiring 111 formed by a second layer wiring on an interlayer insulating film formed on the substrate including the gate wiring. Here, the contact portion between the first gate connection wiring 111 and the second drain wiring 110 is indicated by a.

Similarly, the second NMOS transistor TN
A second gate line 107 serving as each gate of the second and second PMOS transistors TP2, a first NMOS transistor TN1 and a first PMOS transistor TP
1st drain wiring 1 which connects each drain of 1 in common
09 is connected by a second gate connection wiring 112 formed by a second layer wiring on an interlayer insulating film formed on a substrate including the gate wiring. Here, a contact portion between the second gate connection wiring 112 and the first drain wiring 109 is indicated by b.

Reference numeral 113 denotes a first PMOS transistor TP
1 source region and second PMOS transistor TP
Power supply line (Vcc
Line), and the contact portion is indicated by c.

Reference numeral 114 denotes a first NMOS transistor TN
1 source region and second NMOS transistor TN
2 are connected to a reference potential line (V
ss line), and the contact portion is indicated by d.

Reference numeral 115 denotes a third NMOS transistor TN
3 is one bit line connection pattern connected to the other end region of the third bit line, and its contact portion is indicated by e. Similarly, the other bit line connection pattern 116 is connected to the other end region of the fourth NMOS transistor TN4, and its contact portion is indicated by f.

In the above structure, two gate connection lines (first gate connection line 111 and second gate connection line 112) are arranged on the interlayer insulating film in a direction parallel to the word line WL. Therefore, the interval between the wirings is narrowed, and processing and miniaturization are difficult. In other words, the word line W
The pattern size of the memory cell in the direction orthogonal to L (the direction parallel to the bit line and the direction of the bit line) is increased, and the reduction in cell size is restricted.

[0026]

As described above, the CMO
In a conventional SRAM having an array of S-type memory cells and using a trench-type element isolation structure, two gate connection wirings are arranged on an interlayer insulating film in a direction parallel to a word line. There is a problem that the pattern size of the memory cell in the direction parallel to the line becomes large, and reduction in the cell size is restricted.

The present invention has been made to solve the above problems, and effectively utilizes the inside of a trench region used as an element isolation region for wiring, to reduce the chip size, and to improve the CMOS type. It is an object of the present invention to provide a semiconductor device capable of reducing the cell pattern dimension in a direction orthogonal to a word line and realizing a high-speed SRAM, and a method of manufacturing the same, when the present invention is applied to an SRAM memory cell.

[0028]

According to a first aspect of the present invention, there is provided a semiconductor device comprising: a trench isolation region selectively formed in a semiconductor substrate; and a trench isolation region embedded in the trench isolation region; And embedded wiring in contact with the insulator formed in the same step.

According to a second semiconductor device of the present invention, the first semiconductor device has an array of static memory cells using complementary insulated gate field effect transistors,
A static semiconductor memory using a trench type element isolation structure, wherein P
It is characterized by using a wiring buried inside a trench-type isolation region between a channel transistor region and an N-channel transistor region.

The first method of manufacturing a semiconductor device according to the present invention comprises:
A first step of forming a cavity in the insulator to be embedded in at least a part of the trench when forming the trench and filling the insulator to selectively form the plurality of trench isolation regions in the semiconductor substrate; A second step of opening a plurality of holes connected to the cavity in the insulator; and a third step of embedding a conductive material inside the holes and the cavity.

According to a second method of manufacturing a semiconductor device of the present invention,
The method of manufacturing a first semiconductor device further comprises a fourth step of expanding the cavity by isotropic etching between the second step and the third step.

According to a third method of manufacturing a semiconductor device of the present invention,
An array of static memory cells using complementary insulated gate field effect transistors, and a plurality of trench isolation regions are selectively formed in a semiconductor substrate when manufacturing a static semiconductor memory using a trench element isolation structure. Forming a trench to form a first cavity, and forming a cavity in an insulator embedded in the trench between the P-channel transistor region and the N-channel transistor region of the memory cell in the trench. A second step of opening a plurality of holes connected to the cavity in the insulator, a third step of enlarging the cavity by isotropic etching, and a step of enlarging the hole and the cavity. A fourth step of embedding a conductive material therein;
Forming the memory cell by using the wiring buried in the step as a part of the wiring of the memory cell.

[0033]

Embodiments of the present invention will be described below in detail with reference to the drawings.

First, the features of the structure of the memory cell of the CMOS SRAM using the trench type element isolation structure according to the first embodiment of the present invention and the manufacturing method thereof will be described. In addition,
The equivalent circuit of this memory cell is as described above with reference to FIG.

In general, the width of a trench region for separating a PMOS region and an NMOS region of a CMOS memory cell using a trench-type device isolation structure must be larger than a processing limit in a design rule. . Therefore, a part of the wiring of the memory cell is buried in the inside of the trench region (in the insulator) to effectively utilize the trench region.

In this case, the trench is usually formed so that no void (void) is formed inside the trench region. However, in the present invention, a void is intentionally formed inside the trench region, and the void is buried using the void. Wiring is formed. Since it is difficult to flow a large current or reduce the resistance as the buried wiring, a wiring for voltage application (for example, the first gate connection wiring 91 or the second gate connection wiring 92 in FIG. 9) is used. It is desirable to form.

FIGS. 1A to 8A show an SRAM using a trench type element isolation structure according to the first embodiment.
, In particular, a pattern in a CMOS memory cell portion.

FIGS. 1B to 8B respectively show cross-sectional structures along the line BB in FIGS. 1A to 8A, and FIG. 3A to 3C respectively show cross-sectional structures along the line CC in FIGS. 1A to 3A, respectively.

First, as shown in FIGS. 1A to 1C, a first P-well region 11, a second P-well region 12, and a first N-well are selectively formed in a surface layer portion of a silicon substrate 10. A region 13, a second N-well region 14, and a trench-type element isolation region (trench region) 15 are formed. Of the trench regions, the width W of the trench region 15a for isolating the PMOS region and the NMOS region has a size larger than the processing limit in the design rule.

When forming the trench region 15a, after forming a trench having an equal depth, the trench in the region where the embedded wiring is to be formed is selectively deepened by using a resist as a mask by photolithography. in this case,
By appropriately controlling the depth, the shape of the trench depth and the taper angle, and the method of forming the buried oxide film,
A cavity (void) 17 for wiring embedding having a desired length and width is selectively formed in the buried oxide film 16 in the trench.

Next, as shown in FIGS. 2A to 2C, for example, RIE is performed so that the upper portion of any two places (for example, both ends) of the cavity 17 is connected to both ends of the cavity 17.
A hole 18 is opened in the buried oxide film 16 by using (reactive ion etching).

Next, as shown in FIGS. 3A to 3C, isotropic etching is performed to remove a coarse oxide film around the cavity 17 in the buried oxide film 16 and enlarge the cavity 17. I do. Then, for example, using a CVD (vapor phase growth) method,
A buried wiring 19 is formed by burying a high-melting point metal such as W in the cavity 17 and the hole 18.

Next, a gate insulating film 20 is formed on the surface of the substrate, a part thereof is opened (20a), and then gate wirings 21 to 23 are formed as shown in FIGS. 4 (a) and 4 (b). At the same time, a part of the gate wiring 22 is
To one end.

Here, reference numeral 21 denotes a first gate wiring serving as each gate electrode of the first NMOS transistor TN1 and the first PMOS transistor TP1, and 22 denotes a second NM.
A second gate wiring serving as a gate electrode of each of the OS transistor TN2 and the second PMOS transistor TP2;
3 is a pair of transfer gate transistors TN3 and TN3
4 (third gate wiring (word line W
L).

Thereafter, an N + region serving as a drain region and a source region of the NMOS transistor and a P + serving as a drain region and a source region of the PMOS transistor are formed.
+ Form a region.

That is, in the first P-well region 11, below the first gate line 21 is the channel region of the first NMOS transistor TN1, and on both sides thereof, the drain region of the first NMOS transistor TN1 and An N + region serving as a source region is formed.

In the second P-well region 12, below the second gate line 22 is a channel region of the second NMOS transistor TN2, and on both sides thereof, a drain region of the second NMOS transistor TN2. And an N @ + region serving as a source region is formed.

In the first P-well region 11, below the third gate line 23 is a channel region of the third NMOS transistor TN3, and on both sides thereof, a drain region of the third NMOS transistor TN3. And an N @ + region serving as a source region is formed. In this case, the one end region (N + region) of the third NMOS transistor TN3 and the N + region serving as the drain region of the first NMOS transistor TN1 are connected.

In the second P-well region 12, below the third gate line 23 is the channel region of the fourth NMOS transistor TN4, and on both sides thereof, the drain region of the fourth NMOS transistor TN4. And an N @ + region serving as a source region is formed. In this case, the one end region (N + region) of the fourth NMOS transistor TN4 and the N + region serving as the drain region of the second NMOS transistor TN2 are connected.

In the first N-well region 13, a portion below the first gate line 21 is a channel region of the first PMOS transistor P1.
A P + region serving as a drain region and a source region of the PMOS transistor P1 is formed.

In the second N-well region 14, below the second gate line 22 is a channel region of the second PMOS transistor TP2, and on both sides thereof, a drain region of the second PMOS transistor TP2. And a P + region serving as a source region is formed.

Next, as shown in FIGS. 5A and 5B, a first interlayer insulating film 24 is formed on the substrate including the gate wirings 21 to 23, and a buried wiring groove is formed in a part thereof. After the formation, the first drain wiring 25 and the second drain wiring 26 are buried in the trench.

Here, the first drain wiring 25 is formed of the first
The drain regions of the NMOS transistor TN1 and the first PMOS transistor TP1 are commonly connected, and a part thereof is in contact with the upper surface of the other end of the embedded wiring 19. That is, the first drain wiring 25 is connected to the second gate wiring 22 via the buried wiring 19.

The second drain wiring 26 has a second NMO
The drain regions of the S transistor TN2 and the second PMOS transistor TP2 are commonly connected.

Next, as shown in FIGS. 6A and 6B, a second interlayer insulating film 27 is formed on the substrate including the drain wirings 25 and 26, and the second drain wiring 26 is formed.
Contact hole 27a reaching the first gate wiring 21, contact hole 27b reaching the first gate wiring 21,
Source region of S transistor TP1 and second PMO
A contact hole 27c reaching the source region of the S transistor TP2; a contact hole 27d reaching the source region of the first NMOS transistor TN1 and the source region of the second NMOS transistor TN2;
The other end region of the OS transistor TN3 and the fourth NMO
A contact hole 27e reaching the other end region of the S transistor TN4 is formed.

Next, as shown in FIGS. 7A and 7B, a metal wiring layer such as Al or Cu is deposited on the second interlayer insulating film 27 and buried in the contact holes. Various wiring 29 by patterning
To 33 are formed.

Here, reference numeral 29 denotes a power supply line (Vcc line) commonly connected to the source region of the first PMOS transistor TP1 and the source region of the second PMOS transistor TP2. ing.

Reference numeral 30 denotes a reference potential line (Vss line) commonly connected to the source region of the first NMOS transistor TN1 and the source region of the second NMOS transistor TN2. ing.

Reference numeral 31 denotes a first bit line relay connection line connected to the other end region of the third NMOS transistor TN3, and reference numeral 32 denotes a fourth NMOS transistor T
This is a second bit line relay connection line connected to the other end region of N4, and each contact portion is indicated by e.

Reference numeral 33 denotes a second gate connection line for connecting the first gate line 21 and the second drain line 26. The contact portions are indicated by a and b.

Next, as shown in FIGS. 8A and 8B, a third interlayer insulating film 34 is formed on the substrate including the Vcc line 29 and the like.
Are formed, and the first bit line relay connection wiring 31 and the second bit line
The contact hole reaching the bit line relay connection wiring 32 is formed.

After the conductive plug 35 is buried in the contact hole, the third interlayer insulating film 34 is formed.
A metal wiring layer such as Al or Cu is deposited thereon, and is patterned to form a pair of bit lines BL and / BL as shown by a dashed line in FIGS. 8A and 8B.

In the above structure, the trench region 1
A buried wiring 19 corresponding to a first gate connection wiring is formed inside 5a.
Can be formed below the group of gate wirings 21 to 23,
The degree of freedom of the wiring layout on the second interlayer insulating film 27 increases.

On the second interlayer insulating film 27, a second gate connection wiring 33 is provided in a direction parallel to the word line 23 (WL), and the Vcc line 29 and the Vss line 30 are connected in the same wiring layer. Are arranged in a direction parallel to the word line WL.

Therefore, according to the above-described structure, it is possible to reduce the pattern size of the memory cell in the direction orthogonal to the word line WL (the direction parallel to the bit lines BL and / BL), thereby reducing the cell size. Will be possible.

In other words, when the pattern size of the memory cell in the direction orthogonal to the word line WL is made the same as that of the conventional example, or when the design rule of the previous generation is adopted, the Vcc line 29 and the Vss line Increase the width of 30,
By reducing the wiring resistance, it is possible to reduce the voltage drop due to the wiring resistance and increase the operation margin of the memory cell.

Alternatively, the Vcc line 29 and V
By increasing the width of the ss line 30 and reducing its wiring resistance, the installation interval of a short-circuit connection point with a main power supply line (not shown) and a main reference potential line (not shown) disposed further above , The number of short-circuit connection points can be reduced and the margin for pattern design can be increased, so that the speed of the SRAM can be increased.

The buried wiring 19 formed in the above embodiment has a different cross-sectional shape from a normal wiring, and for example, as shown by a dotted line in FIG. The peripheral surface is in contact with an insulator formed in the same step (in this example, the silicon oxide film 16 formed in the trench filling step).

In the method of forming the buried wiring 19 as described in the above embodiment, the step of forming an interlayer insulating film for covering the upper surface after the formation of the buried wiring is different from the method of forming a normal buried wiring. Not required.

The method of manufacturing a semiconductor device according to the present invention comprises:
Not limited to the above embodiment, in the semiconductor device, a trench isolation region having a margin inside (an isolation region larger than a processing limit such as an N well / P well isolation region)
A cavity is formed in the cavity.

By forming, for example, a buried wiring inside the cavity, the trench isolation region is effectively used, the degree of freedom in the wiring layout of the upper layer is increased, and a part of the wiring in the upper layer is replaced by the buried wiring. The design can be relaxed and the chip size can be reduced.

[0072]

As described above, according to the semiconductor device and the method for manufacturing the same of the present invention, in an integrated circuit using a trench type element isolation structure, the inside of a trench region is effectively utilized for wiring, and a circuit pattern is formed. A semiconductor device which can be reduced in size and a method for manufacturing the same can be provided.

Therefore, when the present invention is applied to an SRAM memory cell having an array of CMOS type memory cells using a trench type element isolation structure, the pattern size in the direction parallel to the bit line of the memory cell is reduced. Can be
The speeding up of the SRAM can be realized.

[Brief description of the drawings]

FIG. 1 is a view showing a pattern and a sectional structure in a part of a manufacturing process of an SRAM using a trench-type element isolation structure according to a first embodiment of the present invention.

FIG. 2 is a view showing a pattern and a cross-sectional structure in a step following the step of FIG. 1;

FIG. 3 is a view showing a pattern and a cross-sectional structure in a step following the step of FIG. 2;

FIG. 4 is a view showing a pattern and a cross-sectional structure in a step following the step of FIG. 3;

FIG. 5 is a view showing a pattern and a sectional structure in a step following the step of FIG. 4;

FIG. 6 is a view showing a pattern and a sectional structure in a step following the step of FIG. 5;

FIG. 7 is a view showing a pattern and a sectional structure in a step following the step of FIG. 6;

FIG. 8 is a view showing a pattern and a sectional structure in a step following the step of FIG. 7;

FIG. 9 is an equivalent circuit diagram showing one memory cell in a CMOS SRAM having an array of CMOS static memory cells.

FIG. 10 is a diagram schematically showing a conventional pattern of the memory cell of FIG. 9 in an SRAM using a trench-type element isolation structure.

[Explanation of symbols]

Reference Signs List 10: silicon substrate, 11, 12: P-well region, 13, 14: N-well region, 15, 15a: trench-type element isolation region (trench region), 16: silicon oxide film, 17: cavity for wiring embedding ( Void), 18: Hole, 19: Embedded wiring.

Claims (5)

[Claims] 1. A trench isolation region selectively formed in a semiconductor substrate, and a trench embedded in the trench isolation region, and a peripheral surface in contact with an insulator formed in the same step in the trench isolation region. A semiconductor device comprising a wiring. 2. The method according to claim 1, wherein the trench isolation region is an N well
2. The semiconductor device according to claim 1, wherein the semiconductor device is an inter-well separation region. 3. An array of static memory cells using complementary insulated gate field effect transistors,
A static semiconductor memory using a trench-type element isolation structure, wherein a wiring embedded in a trench-type isolation region between a P-channel transistor region and an N-channel transistor region is provided as a part of a wiring of the memory cell. The semiconductor device according to claim 1, wherein the semiconductor device is used. 4. A method of forming a trench to selectively form a plurality of trench isolation regions in a semiconductor substrate and embedding an insulator, wherein a cavity is formed in the insulator embedded in at least a part of the trench. A first step, a second step of opening a plurality of holes connected to the cavity in the insulator, and a third step of burying a conductive material inside the holes and the cavity. A method for manufacturing a semiconductor device. 5. The semiconductor device according to claim 4, further comprising a fourth step of expanding said cavity by isotropic etching between said second step and said third step. Production method.