CN106206443A - The forming method of sram cell - Google Patents
The forming method of sram cell Download PDFInfo
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- CN106206443A CN106206443A CN201510215852.7A CN201510215852A CN106206443A CN 106206443 A CN106206443 A CN 106206443A CN 201510215852 A CN201510215852 A CN 201510215852A CN 106206443 A CN106206443 A CN 106206443A
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Abstract
The forming method of a kind of sram cell, the forming method of this sram cell includes: form first, second and third fin in first area, and second and third fin is laid out in parallel on the first fin length direction；Fourth, fifth, six fins, the five, the six fins laid out in parallel on the length direction of the 4th fin is formed at second area；The length direction of first, fourth fin is crystal orientation race<110>, second and third, the length direction of five, six fins be crystal orientation race<100>；It is developed across the first grid of the first fin, across the second grid of second and third fin, across the 3rd grid of the 4th fin, the 4th grid across the five, the six fins.In this case first, fourth fin vertical in second and third, five, six fins, the formation process of grid, such as patterning process be easier realize, all grid widths of formation meet expection.Such as at photoetching process, lithographic equipment is high to resolution and the resolution of the gate patterns after rotating 90 degree.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly to the forming method of a kind of sram cell.
Background technology
SRAM (Static Random Access Memory, SRAM) is as in memorizer
A member, have at high speed, the advantage such as low-power consumption and standard technology compatibility mutually, be widely used in PC, individual
The fields such as people's communication, consumption electronic product (smart card, digital camera, multimedia player).
One SRAM includes multiple static random access memory cell, and (hereinafter referred to as SRAM is mono-
Unit), the plurality of sram cell arranges according to array, and a sram cell includes six transistors (6-T).
Along with integrated circuit integrated level improve, the characteristic size of sram cell be gradually reduced and shared wafer area also
More and more less.Compared with the size of planar MOS transistors, fin formula field effect transistor smaller,
The most more meet the requirement of future integrated circuits more high integration.
In prior art, with reference to Fig. 1, comprise the 6T structure sram cell of six fin formula field effect transistors
Including:
First transmission transistor PG1 and the first pull-down transistor PD1, shares the first fin 1, the first transmission
Transistor PG1 has the first grid 2 across the first fin 1；
First pulls up transistor PU1, has the second fin 3, and the second fin 3 is parallel with the first fin 1, and
One PU1 and the first pull-down transistor PD1 that pulls up transistor shares second grid 4, second grid 4 simultaneously across
First fin 1 and the second fin 3；
Second transmission transistor PG2 and the second pull-down transistor PD2, shares the 3rd fin 5, the second transmission
Transistor PG2 has the 3rd grid 6 across the 3rd fin 5；
Second pulls up transistor PU2, has the 4th fin 7, and the 4th fin 7 is parallel with the 3rd fin 5, and
Two PU2 and the second pull-down transistor PD2 that pull up transistor share the 4th grid 8, the 4th grid 8 simultaneously across
3rd fin 5 and the 4th fin 7.Further, the first fin the 1, the 3rd fin 5 laid out in parallel, the second fin 3
And the 4th fin 7 between the first fin 1 and the 3rd fin 5.
In existing sram cell, due to the first fin the 1, second fin the 3, the 3rd fin 5 and the 4th fin
Portion 7 is parallel to each other, and all transistors channel direction operationally is identical.Wherein channel direction refers to raceway groove
Middle carrier flows to, and in fin formula field effect transistor, channel direction is fin length direction.Substrate 9
The indices of crystallographic plane are (100), and therefore channel direction all can use crystal orientation race<110>to represent.Wherein, in crystal
The each group crystal orientation being equal to because of symmetrical relations can merger be a crystal orientation race.
With reference to Fig. 2, curve A be channel direction be carrier in p-type fin formula field effect transistor time<100>
Mobility change curve, curve B be channel direction be current-carrying in p-type fin formula field effect transistor time<110>
Transport factor change curve, curve C be channel direction be in N-type fin formula field effect transistor time<100>
Carrier mobility change curve, curve D be channel direction be N-type fin field effect crystal time<110>
Carrier mobility change curve in pipe.It is seen that in same doping content NinvUnder the conditions of, right
For p-type fin formula field effect transistor, channel direction is that carrier mobility during crystal orientation race<110>is higher than
Channel direction is the carrier mobility of crystal orientation race<100>, the highest by 40%；Brilliant to N-type fin field effect
For body pipe, channel direction be carrier mobility during crystal orientation race<100>be crystal orientation race higher than channel direction
<110>carrier mobility is the highest by 10%.
For sram cell, when read operation, noise margin β be in pull-down transistor turn on electric current with
Turning on the ratio of electric current in transmission transistor, conducting size of current can represent by carrier mobility, its
Middle noise margin embodies the capacity of resisting disturbance of circuit.Owing to transmission transistor and pull-down transistor are N-type
Fin formula field effect transistor, therefore, is approximately equal to 1 in conjunction with reference to Fig. 2, β.When write operation, noise
Tolerance limit γ is to turn on the ratio of electric current and the middle conducting electric current that pulls up transistor in transmission transistor, due to upper crystal pulling
Body pipe is p-type fin formula field effect transistor, therefore, is less than 1 in conjunction with reference to Fig. 2, γ.
It will thus be seen that noise margin γ that sram cell is when write operation is less, sram cell resists
Interference performance is less, is easily subject to peripheral circuit signal disturbing, signal transmission instability in sram cell,
Data transmission efficiency is relatively low.
For solving the problems referred to above, prior art proposes: the channel direction keeping transmission transistor is crystal orientation race
<110>, pull-down transistor and the channel direction pulled up transistor are crystal orientation race<100>, so, and lower crystal pulling
The carrier mobility during conducting of body pipe increases 10% when being crystal orientation race<110>than channel direction, read operation
Time noise margin β more than or equal to 1.1；Meanwhile, the carrier mobility pulled up transistor compares channel direction
For reducing 40% time crystal orientation race<110>, noise margin γ during write operation is more than or equal to 1.4.
But, when the indices of crystallographic plane of substrate 9 are (100), being limited by existing technique, prior art is not
Pull-down transistor and the sram cell that channel direction is crystal orientation race<100>pulled up transistor can be formed.
Summary of the invention
The problem that the present invention solves is, when the indices of crystallographic plane of substrate are (100), to be limited by existing technique,
Prior art can not form pull-down transistor and the channel direction pulled up transistor is crystal orientation race<100>
Sram cell.
For solving the problems referred to above, the present invention provides the forming method of a kind of sram cell, this forming method
Including:
Thering is provided substrate, the indices of crystallographic plane of described substrate are (110), and described substrate has adjacent one another are the
One region and second area；
Form the first fin, the second fin and the 3rd fin in described first area, described second fin and
3rd fin is laid out in parallel on described first fin length direction；With,
Form the 4th fin, the 5th fin and the 6th fin at described second area, described 5th fin and
6th fin is laid out in parallel on the length direction of described 4th fin；
Described first fin, the 4th fin are parallel to each other and length direction is crystal orientation race<110>, and described second
Fin, the 3rd fin, the 5th fin, the length direction of the 6th fin are crystal orientation race<100>；
It is developed across the first grid of described first fin, across the of described second fin and the 3rd fin
Two grids, across the 3rd grid of described 4th fin, across the of described 5th fin and the 6th fin
Four grids；
In all grids, the fin of each grid both sides forms source electrode and drain electrode；
Described first grid and the first fin constitute the first transmission N-type fin formula field effect transistor, and described the
Two grids and the second fin constitute the first drop-down N-type fin formula field effect transistor, described second grid and
Three fins constitute the first pull-up p-type fin formula field effect transistor；
Described 3rd grid and the 4th fin constitute the second transmission N-type fin formula field effect transistor, and described the
Four grids and the 5th fin constitute the second drop-down N-type fin formula field effect transistor, described 4th grid and
Six fins constitute the second pull-up p-type fin formula field effect transistor.
Alternatively, formed on the substrate described first grid, second grid, the 3rd grid, the 4th
The method of grid includes:
Described substrate, the first fin, the second fin, the 3rd fin, the 4th fin, the 5th fin,
Forming gate material layers on 6th fin, the upper surface of described gate material layers is higher than all fin upper surfaces；
Described gate material layers is patterned, forms described first grid, second grid, the 3rd grid
Pole and the 4th grid.
Alternatively, the method being patterned described gate material layers includes:
Described gate material layers is formed layer of mask material；
Described layer of mask material is carried out the most graphical, described going out defined in described layer of mask material
First grid, the position of the 3rd grid；
Described layer of mask material is carried out second time graphical, described going out defined in described layer of mask material
Second grid, the position of the 4th grid；
Layer of mask material after, second time graphical with described first time is graphical is as mask, and etching is described
Gate material layers, to exposing substrate, forms first grid, second grid, the 3rd grid, the 4th grid.
Alternatively, described layer of mask material is hard mask layer.
Alternatively, use photoetching process described hard mask layer to be carried out for the first time the most graphically, figure for the second time
Change.
Alternatively, described first area point to second area be oriented parallel to described crystal orientation race<100>.
Alternatively, about a fixed point in boundary line between described first area and second area, described
It is right that one transmission N-type fin formula field effect transistor and described second transmission N-type fin formula field effect transistor rotate
Claim, described first drop-down N-type fin formula field effect transistor and the second drop-down N-type fin formula field effect transistor
Rotationally symmetrical, described first pull-up p-type fin formula field effect transistor and the second pull-up p-type fin field effect
Transistor is rotationally symmetrical.
Alternatively, described second fin than the 3rd fin near described first fin, described first fin shape
The part becoming to have the part of drain electrode and described second fin to be formed with drain electrode links together；
Described 5th fin is than the 6th fin near described 4th fin, and described 4th fin is formed with drain electrode
Part and the described 5th fin part that is formed with drain electrode link together.
Alternatively, after forming all source electrodes and drain electrode, also include:
Interlayer dielectric layer, described suprabasil inter-level dielectric is formed above described substrate, all transistors
Layer segment is higher than described first grid, second grid, the 3rd grid and the 4th grid；
The first interconnection line, described first interconnection line and described second fin is formed in described interlayer dielectric layer
Be formed with the part of drain electrode, described 3rd fin is formed with the part of drain electrode and the electrical connection of the 4th grid, shape
Become the first memory node；
The second interconnection line, described second interconnection line and described 5th fin is formed in described interlayer dielectric layer
Be formed with the part of drain electrode, described 6th fin is formed with the part of drain electrode and second grid electrical connection, shape
Become the second memory node；
Described first and second memory node constitutes complementary pair.
Compared with prior art, technical scheme has the advantage that
This programme selects the indices of crystallographic plane of substrate to be (110).Compared with existing sram cell, first,
In two transmission N-type fin formula field effect transistors, channel direction is constant, keeps the length side of first, fourth fin
To for crystal orientation race<110>.In (110) crystal face, crystal orientation race<110>and crystal orientation race<100>are mutually perpendicular to.
Therefore, the second fin of the first drop-down N-type fin formula field effect transistor, the first pull-up p-type fin field are made
3rd fin of effect transistor, the second drop-down N-type fin formula field effect transistor the 5th fin,
Two pull-up p-type fin formula field effect transistors the 6th fin vertical in first, fourth fin, second and third,
Five, the length direction of six fins is become crystal orientation race<100>from existing crystal orientation race<110>, the most all on
Draw, the channel direction of pull-down transistor is become crystal orientation race<100>from existing crystal orientation race<110>.This can be real
Noise when noise margin β when existing sram cell has preferably read operation and write operation holds
Limit γ, β, γ are relatively big, and the capacity of resisting disturbance of external circuit signals is strengthened by sram cell, SRAM
In unit, stable signal transmission promotes.
Due to first, fourth fin vertical in second and third, will pull-up in five, six fins, with prior art
Transistor rotates 45 degree with the fin of pull-down transistor on existing Process ba-sis and compares, in the technical program
The formation process of all fins is easily to realize, and all fin size ultimately formed meet expection.And
And, first and third gate vertical will pull up transistor and drop-down in second, four grids, with prior art
The grid of transistor rotates 45 degree on existing Process ba-sis and compares, the formation process of all grids, such as
Patterning process is easier to realize, and all grid widths ultimately formed meet expection.Such as exist
The photoetching process of grid forming process, lithographic equipment is higher to the resolution of the gate patterns after rotating 90 degree,
Resolution is high, and the gate patterns width finally given meets expection.
Accompanying drawing explanation
Fig. 1 is the layouts of the sram cell comprising 6 fin formula field effect transistors of prior art
Schematic diagram；
Fig. 2 is the existing MOS transistor carrier mobility operationally schematic diagram with concentration change,
Wherein,
Curve A be channel direction be carrier mobility change curve in PMOS transistor time<100>,
Curve B be channel direction be carrier mobility change curve in PMOS transistor time<110>,
Curve C be channel direction be carrier mobility change curve in nmos pass transistor time<100>,
Curve D be channel direction be carrier mobility change curve in nmos pass transistor time<110>；
Fig. 3 is in sram cell shown in Fig. 1, the structure cell coordinate system of substrate；
Fig. 4～Figure 16 is the sram cell knot in each stage of manufacture process of the specific embodiment of the invention
Structure schematic diagram, wherein,
Fig. 5 is the structure cell coordinate system of substrate shown in Fig. 4；
Fig. 9 is Fig. 8 along L3L4The cross-sectional view in direction, wherein L3L4It is parallel to crystal orientation race<100>；
Figure 10 is Fig. 8 along H3H4The cross-sectional view in direction, wherein H3H4It is parallel to crystal orientation race
<110>。
Detailed description of the invention
The problem existed for prior art, inventor is analyzed, and finds:
With reference to the coordinate system that Fig. 3, Fig. 3 are a structure cell, on (100) crystal face E (shadow region),
Crystal orientation race<110>includes that crystal orientation [110], crystal orientation race<100>include crystal orientation [100], the angle of [110] and [100]
Being 45 degree, [110] turn clockwise 45 degree available [100].Therefore, for product structure, make
The fin of pull transistor and pull-down transistor rotates 45 degree on existing Process ba-sis, so that it may make lower crystal pulling
Pipe and the channel direction pulled up transistor become crystal orientation race<100>.Correspondingly, occur at fin length direction
On the premise of change, pull-down transistor and the grid pulled up transistor also to rotate 45 degree with fin.
But, during manufacturing above-mentioned sram cell, the grid width obtained is more notable than expection to be subtracted
Little.Trace it to its cause, in the photoetching process forming grid, in order to make grid rotate 45 degree, need to make grid
The figure of pole rotates 45 degree.But after gate patterns rotates 45 degree, the lithographic equipment solution to gate patterns
Analysis degree declines, and resolution reduces, and the grid width formed after final etching technics is substantially reduced, Qi Zhong
In same fin formula field effect transistor, grid width is parallel to fin length direction.Therefore, by existing light
The restriction of carving technology, pulls up transistor and the grid width of pull-down transistor is too big with expection difference, this meeting
Causing sram cell to lose efficacy, existing technique cannot obtain intended sram cell.
For solving the problems referred to above, the present invention provides the forming method of a kind of new sram cell, to make
Obtain the sram cell with higher noise tolerance limit.
Understandable, below in conjunction with the accompanying drawings for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from
The specific embodiment of the present invention is described in detail.
With reference to Fig. 4, it is provided that substrate 10, the indices of crystallographic plane of substrate 10 are (110).Substrate 10 has that
This adjacent first area I and second area II, first area I are the region forming the first phase inverter, the
Two region II are the region forming the second phase inverter.
In conjunction with reference to the coordinate system that Fig. 5, Fig. 5 are the interior structure cell of substrate 10, the crystal face F in structure cell hangs down
Straight intersect in Z axis and with X-axis and Y-axis, and crystal face F is identical with the intercept of X-axis and Y-axis, because of
These available indices of crystallographic plane (110) represent.In forming process, by protecting in substrate 10 growth course
Hold the accurately control to crystal orientation and can obtain (110) crystal face F.In (110) crystal face F, crystal orientation race<110>
Including crystal orientation [110], crystal orientation race<100>includes crystal orientation [001], the folder between crystal orientation [110] and crystal orientation [001]
Angle is 90 degree, and crystal orientation [110] rotation 90 degree i.e. be can get crystal orientation [001].
Wherein, first area I point to second area II be oriented parallel to crystal orientation race<100>.
In the present embodiment, substrate 10 can be silicon base, it is also possible to be germanium, germanium silicon, GaAs substrate
Or silicon-on-insulator substrate.Those skilled in the art can select the type of substrate 10 as required, therefore
The type of substrate 10 should not become the feature limited the scope of the invention.Substrate 10 in the present embodiment
For silicon base, because implementing the technical program on a silicon substrate to implement this skill than in other types substrate
Art scheme low cost.
With reference to Fig. 6, form the first fin the 11, second fin 12 and the 3rd fin 13 at first area I,
Second fin 12 and the 3rd fin 13 laid out in parallel on the length direction of the first fin 11, namely
Two fins 12 are parallel to the 3rd fin 13 and the first fin 11 is perpendicular to the second fin 12 and the 3rd fin
13；With,
The 4th fin the 14, the 5th fin 15 and the 6th fin, the 5th fin 15 is formed at second area II
With the 6th fin 16 laid out in parallel on the length direction of the 4th fin 14, namely the 5th fin 15 is flat
Row is perpendicular to the 5th fin 15 and the 6th fin 16 in the 6th fin 16 and the 4th fin 14；
Wherein, the first fin 11 and the 4th fin 14 are parallel to each other, the first fin 11 and the 4th fin 14
Length direction be represented by crystal orientation race<110>.In conjunction with reference to Fig. 5, crystal orientation race<110>is perpendicular to crystal orientation
Race<100>, therefore hangs down at the second fin the 12, the 3rd fin the 13, the 5th fin 15 and the 6th fin 16
Straight when the first fin 11 and four fins 14, the second fin the 12, the 3rd fin the 13, the 5th fin 15
It is represented by crystal orientation race<100>with the length direction of the 6th fin 16.
Wherein the first fin 11 is as the fin of the first transmission N-type fin formula field effect transistor, the 4th fin
14 is the fin of the second transmission N-type fin formula field effect transistor, and the second fin 12 is the first drop-down N-type
The fin of fin formula field effect transistor, the 3rd fin 13 is the first pull-up p-type fin formula field effect transistor
Fin, the 5th fin 15 is the fin of the second drop-down N-type fin formula field effect transistor, the 6th fin 16
It it is the fin of the second pull-up p-type fin formula field effect transistor.With reference to Fig. 6, about first area I and second
In boundary line one fixed point between the II of region, the first fin 11 is rotationally symmetrical with the 4th fin 14, and the
Two fins 12 and the 5th fin 15 are rotationally symmetrical, and the 3rd fin 13 and the 6th fin 16 rotationally symmetrical,
So can realize between first and second transmission N-type fin formula field effect transistor rotationally symmetrical further, and the
One, rotationally symmetrical between two pull-up p-type fin formula field effect transistors, and first and second drop-down N-type fin
Between field-effect transistor rotationally symmetrical.
Further, the second fin 12 to the three fin 13 leans near the first fin 11, the first fin 11
One end of nearly second fin 12 and one end of the second fin 12 link together, and are used for realizing the first transmission N
The drain electrode of type fin formula field effect transistor and the drain electrode of the first drop-down N-type fin formula field effect transistor are electrically connected
Connect.5th fin 15 to the six fin 16 is near the 4th fin 14, and the 4th fin 14 is near the 5th fin
One end of 15 and one end of the 5th fin 15 link together, and are used for realizing the second transmission N-type fin field
The drain electrode of effect transistor and the drain electrode electrical connection of the second drop-down N-type fin formula field effect transistor.
Compared with prior art shown in Fig. 1, the first fin 11 and the 4th fin 14 are as transmission N-type fin
The fin of formula field-effect transistor, its length direction does not changes, and keeps crystal orientation race<110>.Compare it
Under, the second fin 12 and the 5th fin 15 as drop-down N-type fin formula field effect transistor fin,
Three fins 13 and the 6th fin 16 are as the fin of pull-up p-type fin formula field effect transistor, compared to Fig. 1
Shown pull-up, the fin of pull-down transistor, its length direction rotates on the upper surface being parallel to substrate 10
90 degree, it is achieved that crystal orientation race<110>becomes crystal orientation race<100>.
It addition, in addition to fin length direction changes, in sram cell, the position of each transistor can be followed
The position of transistor corresponding shown in Fig. 1 is arranged.
The length direction of the second fin the 12, the 3rd fin the 13, the 5th fin 15 and the 6th fin 16 occurs
Change, do not interfere with the formation process of all fins.First fin the 11, second fin the 12, the 3rd fin
Portion the 13, the 4th fin the 14, the 5th fin 15 and the forming method of the 6th fin 16, optional autoregistration
Dual patterning technique (SADP, Self-Aligned Double Patterning Technology).First fin
11, the second fin the 12, the 3rd fin the 13, the 4th fin the 14, the 5th fin 15 and the 6th fin 16
Characteristic size is less, uses SADP technique to can get the fine pattern of fin.
Fig. 6 is in a sram cell, the layouts schematic diagram of each fin, with reference to Fig. 7, Fig. 7
For comprising in a SRAM matrix array of sram cell shown in 16 Fig. 6, the cloth of all fins
Figure structure schematic representation.Direction L is parallel to crystal orientation race<100>, and direction H is parallel to crystal orientation race<110>, and 16
Individual sram cell one 4 × 4 type SRAM array of composition.Further, two adjacent along L direction SRAM
Unit constitutes line symmetric graph shape, such as, sram cell L1 and L2, Liang Zheguan adjacent along L direction
Symmetrical in straight line L0, sram cell L2 and L3 adjacent along L direction, both are about straight line L0 '
Symmetrical.The sram cell adjacent along H direction constitutes line symmetric graph shape, such as adjacent along H direction
Sram cell H1 and H2, both are symmetrical about straight line H0, along the sram cell that H direction is adjacent
H2 and H3, both are symmetrical about straight line H0 '.
With reference to Fig. 8～Figure 10, in substrate 10 (with reference to Fig. 6) upper formation gate material layers 20, it is positioned at grid
Hard mask layer 30 on material layer 20.Due to first fin the 11, second fin the 12, the 3rd fin 13,
4th fin the 14, the 5th fin 15 and the 6th fin 16 are covered by gate material layers 20, the most neither
Visible, therefore be represented by dashed line.
Gate material layers 20 may select polysilicon layer, and hard mask layer 30 may select silicon nitride, nitrogenous oxidation
The hard mask material such as silicon or metal hard mask.In addition to hard mask layer, also can in gate material layers 20 shape
Become the mask layer of other materials, and under same etching condition, this mask layer material is compared to the grid of lower section
Pole material has relatively low etching selection ratio, and the forming method of gate material layers 20 and hard mask layer 30 includes:
First, use chemical vapor deposition method, deposition of gate material layer in substrate 10 and all fins,
And make gate material layers upper surface higher than all fin upper surfaces；
Then, use chemical mechanical milling tech, gate material layers is carried out planarization process, makes grid
Material layer upper surface is smooth, and gate material layers upper surface is higher than all fin upper surfaces；
Afterwards, deposited hard mask layer 30 in gate material layers.
With reference to Figure 11, hard mask layer 30 is carried out the most graphical, hard mask layer 30 is formed horizontal stroke
Across the first grid figure 31 of the first fin 11, and the 3rd gate patterns 33 across the 4th fin 14.
The most patterned method includes:
Hard mask layer 30 is formed the first patterned photoresist layer (not shown), the first figure
The photoresist layer changed defines the first grid figure 31 across the first fin 11, and across the 4th fin
3rd gate patterns 33 of 14；
Then, with the first patterned photoresist layer as mask, etch hard mask layer 30 is to exposing grid material
The bed of material 20, first grid figure 31 and the 3rd gate patterns 33 are transferred in hard mask layer 30.
With reference to Figure 12, remove the first patterned photoresist layer, afterwards hard mask layer 30 is carried out second time
Graphically, in hard mask layer 30, it is developed across the second grid figure of the second fin the 12, the 3rd fin 13
Shape 32, and the 4th gate patterns 34 across the 5th fin the 15, the 6th fin 16.Second time is graphical
Method include:
Hard mask layer 30 is formed the photoresist layer (not shown) of second graphical, second graph
The photoresist layer changed defines the second grid figure 32 across the second fin the 12, the 3rd fin 13, and
The 4th gate patterns 34 across the 5th fin the 15, the 6th fin 16；
Then, with the photoresist layer of second graphical as mask, etch hard mask layer 30 is to exposing grid material
The bed of material 20, second grid figure 32 and the 4th gate patterns 34 are transferred in hard mask layer 30.
In the present embodiment, due to the first fin 11, the 4th fin 14 be perpendicular to the second fin 12,
Three fin the 13, the 5th fin the 15, the 6th fin 16, therefore first grid figure the 31, the 3rd grid figures
The length direction of shapeization 32 is perpendicular to second grid figure the 32, the 4th gate patterns 34.So,
In the patterned photoetching process of secondary, lithographic equipment is to second grid figure the 32, the 4th gate patterns 34 also
Having higher resolution and resolution, the width of second grid figure 32 and the 4th gate patterns 34 meets
Desired design.
It is interchangeable it should be noted that the most graphical with the patterned order of second time, is not subject to
The restriction of the present embodiment, namely can first carry out second time graphical, carries out the most graphical afterwards.
Further, it is perpendicular to second grid figure, the 4th grid due to first grid figure, the 3rd gate patterns
Pole figure, lithographic equipment is the highest to resolution and the resolution of all gate patterns, therefore as deformation
Example, it is also possible to be: in the most patterned photoetching process, forms first grid figure, second grid
Figure, the 3rd gate patterns and the 4th gate patterns.
With reference to Figure 13, remove the photoresist layer of second graphical, with the most graphical and second time figure
Hard mask layer 30 after change is mask, and etching grid material layer 20 (with reference to Figure 12) is to exposing substrate 10
With all fin upper surfaces, corresponding first grid figure 31 (with reference to Figure 12) obtains first grid 21, right
Second grid figure 32 (with reference to Figure 12) is answered to obtain second grid 22, corresponding 3rd gate patterns 33 (ginseng
According to Figure 12) obtain the 3rd grid 23, corresponding 4th gate patterns 34 (with reference to Figure 12) obtains the 4th grid
Pole 24；
Afterwards, hard mask layer is removed；
Afterwards, with reference to Figure 14, the first fin part, the second grid 22 liang to first grid 21 both sides
Second fin part of side, the 5th fin part of the 3rd grid 23 both sides, the 4th grid 24 both sides
4th fin part carries out N-type ion implanting, in the first fin 11 of first grid 21 both sides respectively
Form the first source electrode 110 and the first drain electrode 111, first grid the 21, first source electrode 110 and the first drain electrode
111 constitute the first transmission N-type fin formula field effect transistor PG1；With,
The second source electrode 120 and the second drain electrode is formed respectively in the second fin 12 of second grid 22 both sides
121, second grid the 22, second source electrode 120 and second drain electrode 121 composition the first drop-down N-type fin field
Effect transistor PD1, wherein first drain electrode 111 place the first fin parts and the second drain electrode 121 places
Second fin part links together, it is achieved the first drain electrode 111 and the second drain electrode 121 electrical connection；With,
The 4th source electrode 140 and the 4th drain electrode is formed respectively in the 4th fin 14 of the 3rd grid 23 both sides
141, the 3rd grid the 23, the 4th source electrode 140 and the 4th drain electrode 141 composition the second transmission N-type fin field
Effect transistor PG2, and form the 5th source electrode respectively in the 5th fin 15 of the 4th grid 24 both sides
150 and the 5th drain electrode 151, the 4th grid the 24, the 5th source electrode 150 and the 5th drain electrode 151 composition second time
Draw N-type fin formula field effect transistor PD2, wherein the 4th drain electrode 141 place the 4th fin parts and the 5th
151 place the 5th fin parts that drain link together, it is achieved the 4th drain electrode 141 and the 5th drain electrode 151
Electrical connection.
And then, with continued reference to Figure 14, the 3rd fin part, the 3rd grid to second grid 22 both sides
6th fin part of 23 both sides carries out p-type ion implanting, at the 3rd fin of second grid 22 both sides
The 3rd source electrode 130 and the 3rd drain electrode 131, the 3rd source electrode the 130, the 3rd drain electrode 131 and are formed respectively in 13
Second grid 22 constitutes the first pull-up p-type fin formula field effect transistor PU1；With,
The 6th source electrode 160 and the 6th drain electrode is formed respectively in the 6th fin 16 of the 4th grid 24 both sides
161, the 6th source electrode the 160, the 6th drain electrode 161 and the 4th grid 24 constitute the second pull-up p-type fin field effect
Answer transistor PU2.
With reference to Figure 14, the second source electrode the 120, the 3rd source electrode 130 is positioned at the same side of second grid 22, the
Three source electrode 130 to the three drain electrodes 131 are away from second area II；5th source electrode the 150, the 6th source electrode 160
In the same side of the 4th grid 24, the 6th source electrode 160 to the six drain electrode 161 is away from first area I.
It is the SRAM array comprising 16 shown in Figure 14 sram cell with reference to Figure 15, Figure 15,
Along direction L and direction H, adjacent two sram cells are that line is symmetrical.
By above step, in the sram cell formed on the substrate 10, with reference to Figure 14, first passes
The ditch of defeated N-type fin formula field effect transistor PG1 and second transmission N-type fin formula field effect transistor PG2
Direction, road is crystal orientation race<110>, the first drop-down N-type fin formula field effect transistor PD1 and the second drop-down N
The channel direction of type fin formula field effect transistor PD2 is crystal orientation race<100>.Incorporated by reference to reference to Fig. 2, to N
For type fin formula field effect transistor, channel direction is that carrier mobility during crystal orientation race<100>is higher than ditch
Direction, road is the carrier mobility of crystal orientation race<110>, the highest by 10%, therefore, existing with shown in Fig. 1
Sram cell is compared, the first drop-down N-type fin formula field effect transistor PD1 of the present embodiment and second time
The conducting electric current drawing N-type fin formula field effect transistor PD2 increases, making an uproar during sram cell read operation
Acoustic capacitance limit β is more than or equal to 1.1, and noise margin during read operation increases, and sram cell is at read operation
Time capacity of resisting disturbance strengthen.
Further, compared with prior art shown in Fig. 1, the first pull-up p-type fin formula field effect transistor
The channel direction of PU1 and second pull-up p-type fin formula field effect transistor PU2 is crystal orientation race<100>.Knot
Closing with reference to Fig. 2, for PMOS, channel direction is that carrier mobility during crystal orientation race<110>is higher than
Channel direction is the carrier mobility of crystal orientation race<100>, the highest by 40%, therefore, with prior art phase
Ratio, the first pull-up p-type fin formula field effect transistor PU1 and the second pull-up p-type fin formula field effect transistor
The conducting electric current of PU2 increases, and the sram cell of the present embodiment noise margin γ when write operation is big
In equal to 1.4.
Therefore, the sram cell of the present embodiment is respectively provided with bigger noise margin when reading and write data,
The signal disturbing of peripheral control circuits can be resisted, strengthen sram cell job stability and data transmission effect
Rate.
In the present embodiment, elaborated as a example by former grid technique that each fin field effect of sram cell is brilliant
The formation process of body pipe.In addition, it be also possible to use rear grid technique and form each fin formula field effect transistor.
With reference to Figure 16, forming interlayer dielectric layer 50 in substrate and all transistors, suprabasil interlayer is situated between
The upper surface of matter layer 50 part is higher than first grid 21, second grid the 22, the 3rd grid 23 and the 4th grid
Pole 24 upper surface；
The first interconnection line 51 is formed in interlayer dielectric layer 50, the first interconnection line 51 and the second drain electrode 121,
3rd drain electrode 131 and the 4th grid 24 electrically connect, and form the first memory node Q, the first drop-down N-type fin
Formula field-effect transistor PD1 and first pull-up p-type fin formula field effect transistor PU1 constitutes the first phase inverter；
With,
The second interconnection line 52 is formed in interlayer dielectric layer 50, the second interconnection line 52 and the 5th drain electrode 151,
6th drain electrode 161 and second grid 22 electrically connect, and form the second memory node QN, the second drop-down N-type
It is anti-phase that fin formula field effect transistor PD2 and second pull-up p-type fin formula field effect transistor PU2 constitutes second
Device.First memory node Q and the second memory node QN constitute complementary pair, the first reverser and second anti-
Phase device couples to constitute data storage areas.
The forming method of the first interconnection line 51 and the second interconnection line 52 includes:
Respectively corresponding first interconnection line 51 and the second interconnection line 52 position is formed in interlayer dielectric layer 50
Groove；
Groove and interlayer dielectric layer 50 form interconnection line layer, such as copper wire layer；
Remove the interconnection line layer higher than interlayer dielectric layer 50 upper surface, the interconnection line layer conduct in residue groove
First interconnection line 51 and the second interconnection line 52.
Interlayer dielectric layer 50 is also formed with: wordline WL, with first grid 21 and the 3rd grid 23
Electrical connection；
First bit line BL, with first source electrode 110 of the first transmission N-type fin formula field effect transistor PG1
Electrical connection；
Second bit line BLB, with the 4th source electrode 140 of the second transmission N-type fin formula field effect transistor PG2
Electrical connection, the first bit line BL and the second bit line BLB paratope line each other；
Earth lead Vss, with second source electrode 120 of the first drop-down N-type fin formula field effect transistor PD1 and
5th source electrode 150 of the second drop-down N-type fin formula field effect transistor PD2 electrically connects；
Power supply wiring Vdd, with the 3rd source electrode 130 of the first pull-up p-type fin formula field effect transistor PU1
Electrically connect with the 6th source electrode 160 of the second pull-up p-type fin formula field effect transistor PU2.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, all can make various changes or modifications, therefore the guarantor of the present invention
The scope of protecting should be as the criterion with claim limited range.
Claims (9)
1. the forming method of a sram cell, it is characterised in that including:
Thering is provided substrate, the indices of crystallographic plane of described substrate are (110), and described substrate has adjacent one another are the
One region and second area；
Form the first fin, the second fin and the 3rd fin in described first area, described second fin and
3rd fin is laid out in parallel on described first fin length direction, and forms the 4th at described second area
Fin, the 5th fin and the 6th fin, described 5th fin and the 6th fin are in the length of described 4th fin
Laid out in parallel on degree direction；
Described first fin, the 4th fin are parallel to each other and length direction is crystal orientation race<110>, and described second
Fin, the 3rd fin, the 5th fin, the length direction of the 6th fin are crystal orientation race<100>；
It is developed across the first grid of described first fin, across the of described second fin and the 3rd fin
Two grids, across the 3rd grid of described 4th fin, across the of described 5th fin and the 6th fin
Four grids；
Source electrode and drain electrode is formed in the fin of each grid both sides；
Described first grid and the first fin constitute the first transmission N-type fin formula field effect transistor, and described the
Two grids and the second fin constitute the first drop-down N-type fin formula field effect transistor, described second grid and
Three fins constitute the first pull-up p-type fin formula field effect transistor；
Described 3rd grid and the 4th fin constitute the second transmission N-type fin formula field effect transistor, and described the
Four grids and the 5th fin constitute the second drop-down N-type fin formula field effect transistor, described 4th grid and
Six fins constitute the second pull-up p-type fin formula field effect transistor.
2. the forming method of sram cell as claimed in claim 1, it is characterised in that on the substrate
Form described first grid, second grid, the 3rd grid, the method for the 4th grid include:
Described substrate, the first fin, the second fin, the 3rd fin, the 4th fin, the 5th fin,
Forming gate material layers on 6th fin, the upper surface of described gate material layers is higher than all fin upper surfaces；
Described gate material layers is patterned, forms described first grid, second grid, the 3rd grid
Pole and the 4th grid.
3. the forming method of sram cell as claimed in claim 2, it is characterised in that to described grid material
The method that the bed of material is patterned includes:
Described gate material layers is formed layer of mask material；
Described layer of mask material is carried out the most graphical, described going out defined in described layer of mask material
First grid, the position of the 3rd grid；
Described layer of mask material is carried out second time graphical, described going out defined in described layer of mask material
Second grid, the position of the 4th grid；
Layer of mask material after, second time graphical with described first time is graphical is as mask, and etching is described
Gate material layers, to exposing substrate, forms first grid, second grid, the 3rd grid, the 4th grid.
4. the forming method of sram cell as claimed in claim 3, it is characterised in that described mask material
Layer is hard mask layer.
5. the forming method of sram cell as claimed in claim 4, it is characterised in that use photoetching process
Described hard mask layer is carried out the most graphical, the most graphical.
6. the forming method of sram cell as claimed in claim 1, it is characterised in that described first area
That points to second area is oriented parallel to described crystal orientation race<100>.
7. the forming method of sram cell as claimed in claim 6, it is characterised in that about described first
In boundary line one fixed point between region and second area, described first transmission N-type fin field effect is brilliant
Body pipe and described second transmission N-type fin formula field effect transistor are rotationally symmetrical, described first drop-down N-type
Fin formula field effect transistor and the second drop-down N-type fin formula field effect transistor are rotationally symmetrical, and described first
Pull-up p-type fin formula field effect transistor and the second pull-up p-type fin formula field effect transistor are rotationally symmetrical.
8. the forming method of sram cell as claimed in claim 7, it is characterised in that described second fin
Than the 3rd fin near described first fin, described first fin is formed with the part and described the of drain electrode
Two fins are formed with the part of drain electrode and link together；
Described 5th fin is than the 6th fin near described 4th fin, and described 4th fin is formed with drain electrode
Part and the described 5th fin part that is formed with drain electrode link together.
9. the forming method of sram cell as claimed in claim 1, it is characterised in that active being formed
Behind pole and drain electrode, also include:
Interlayer dielectric layer, described suprabasil inter-level dielectric is formed above described substrate, all transistors
Layer segment is higher than described first grid, second grid, the 3rd grid and the 4th grid；
The first interconnection line, described first interconnection line and described second fin is formed in described interlayer dielectric layer
Be formed with the part of drain electrode, described 3rd fin is formed with the part of drain electrode and the electrical connection of the 4th grid, shape
Become the first memory node；
The second interconnection line, described second interconnection line and described 5th fin is formed in described interlayer dielectric layer
Be formed with the part of drain electrode, described 6th fin is formed with the part of drain electrode and second grid electrical connection, shape
Become the second memory node；
Described first and second memory node constitutes complementary pair.
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| CN109285837A (en) * | 2017-07-21 | 2019-01-29 | 中芯国际集成电路制造(上海)有限公司 | A kind of layout structure of semiconductor devices |
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| JP2000269319A (en) * | 1999-03-17 | 2000-09-29 | Toshiba Corp | Semiconductor device and manufacture thereof |
| CN1503368A (en) * | 2002-11-26 | 2004-06-09 | ̨������·����ɷ�����˾ | SRAM unit with multi-grid transistor and mfg method thereof |
| CN103022039A (en) * | 2011-09-21 | 2013-04-03 | 中国科学院微电子研究所 | Sram unit and manufacturing method thereof |
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2015
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000269319A (en) * | 1999-03-17 | 2000-09-29 | Toshiba Corp | Semiconductor device and manufacture thereof |
| CN1503368A (en) * | 2002-11-26 | 2004-06-09 | ̨������·����ɷ�����˾ | SRAM unit with multi-grid transistor and mfg method thereof |
| CN103022039A (en) * | 2011-09-21 | 2013-04-03 | 中国科学院微电子研究所 | Sram unit and manufacturing method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109285837A (en) * | 2017-07-21 | 2019-01-29 | 中芯国际集成电路制造(上海)有限公司 | A kind of layout structure of semiconductor devices |
| CN109285837B (en) * | 2017-07-21 | 2020-12-18 | 中芯国际集成电路制造(上海)有限公司 | Layout structure of semiconductor device |
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