經濟部中央標準局員工消費合作社印製 471064 2060T WF.DOC/006 A7 B7 * 五、發明説明（/) 本發明是有關於一種氧化層的製造方法，且特別是有關 於一種具有不同厚度氧化層的製造方法。 在積體電路元件中，不同的電路，需要具有不同基礎操 作特性的不周電路元件密切配合。而爲因應電路元件的競 爭力及多樣性，在某些元件上須具有不同的氧化層厚度， 以滿足不同操作電壓或電容的需求。 場效電晶體(FETs)是積體電路中最廣受使用的元件之 一，因爲場效電晶體電路可執行多種不同的功能，且場效 電晶體的製造，具有高度的再生性與可預測性。場效電晶 體元件的另一個優點是元件尺寸可以較小，並且可被緊密 的構裝。一典型的場效電晶體由形成在基底上被一通道區 分離的源極和汲極以及一導電的閘極組成，源極和汲極在 通道區的兩邊，而鬧極藉由一閘極氧化物層與通道區隔 開。 場效電晶體的操作特性’是由許多不同的元件構造所決 定，包括閘極氧化物層的厚度。場效電晶體之操作電壓的 上限，主要與閘極氧化物層可承受的崩潰電壓有關’此電 壓主要決定於閘極氧化物層的厚度。由於不同功用的場效 電晶體，被設計在不同的電壓下操作’故實際應用的場效 電晶體，應有不同的閘極氧化物層厚度，以提供不同的操 作電壓。場效電晶體亦可利用不同厚度的閘極氧化物層’ 達成場效電晶體的高操作速度（較薄的閘極氧化物）或低漏 電流(較厚的閘極氧化物）。因此，在記憶體元件內的場效電 晶體，其閘極氧化物層可能具有一第一厚度’而在高速、 3 本紙張尺度適用中國國家標準（CNS ) A4規格（21〇X297公釐） I 裝 訂 (請先閱讀背面之注意事項再填寫本頁) 471064 2060TWF.DOC/006 A7 B7 · 經濟部中央標準局員工消費合作社印製 五、發明説明（2) ， 低電壓之邏輯電路中的場效電晶體，則可能具有一第二， 厚度其明顯較薄的閘極氧化物層。通常，記憶體與邏輯電 路是分別位於不同晶片上。當記憶體與邏輯電路位於不同 晶片上時，則可對不同晶片，分別利用全面性的熱氧化製 程，以生成不同厚度的閘極氧化物。不同厚度的閘極氧化 物是將不同基底暴露在氧化環境中，控制不同暴露時間所 製成。 因此近來，晶片設計已經朝著利用具有不同厚度的氧化 物之電晶體，在單一晶片上結合成電路，用以獲得不同的 操作電壓，或藉以改變其他操作特性。 第1A圖至第1C圖爲習知技藝中，一般用來形成不同 厚度氧化物層的製造方法。請參照第1A圖，首先，在半導 體基底10上形成元件隔離結構11，再於基底10表面以熱 氧化法形成氧化層12,接著在氧化層12上沈積一氮化物層 13。之後，定義元件區，蝕刻部份的氮化物層及氧化物層， 以定義出不同的元件區14、15，再於元件區15的基底表面 成長一氧化層16，作爲元件區15的閘極氧化層。而元件區 14的閘極氧化層爲氧化層12與氮化物層13所構成。因此， 在元件區14與元件區15閘極氧化層的厚度並不相同。 而本發明的主要目的，就是在提供一種可應用於不同操 作電壓與電容，具有不同厚度的氧化層，且製程較習知爲 簡單。 爲達上述之目的，本發明提供一種不同厚度氧化層的製 造方法··首先，提供一半導體基底，且半導體基底具有一 4 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) ♦ 項再填1 裝· -訂 471064 2060T WF.DOC/006 A 7 B7 ^ 經濟部中央標準局員工消費合作社印製 五、發明説明（3) 第一元件區與一第二兀件區’接者在半導體基底、第一兀 件區該第二元件區表面形成一第一氧化層。再對第一元件 區上之第一氧化層提供一摻質’例如爲氮氣，而在第一元 件區上之第一氧化層上形成一第二氧化層，其中第一氧化 層與第二氧化層具有不同的特性，使得第二氧化層可作爲 一硬罩幕，且第二氧化層厚度小於第一氧化層厚度。最後’ 去除第一元件區上之第二氧化層，暴露出第一氧化層表 面，則第一元件區之第一氧化層厚度大於第二元件區上之 第一氧化層厚度。根據上述製造方法，可在不同元件區形 成不同厚度的氧化層。 另外，亦可在不同的元件區上形成複數層不同厚度的氧 化層。其製造方法如下：提供一半導體基底，且半導體基 底具有一第一元件區與一第二元件區。接著，在半導體基 底、第一元件區與第二元件區表面形成一第一氧化層。對 第一元件區上之第一氧化層提供一摻質，在第一氧化層上 形成一第二氧化層，其中第一氧化層與第二氧化層具有不 同的性質，使得第二氧化層可作爲一硬罩幕，且第二氧化 層厚度小於第一氧化層厚度。最後，去除第一元件區上之 第二氧化層，暴露出第一氧化層表面，使第一元件區表面 形成一第一厚度之氧化層，第二元件區形成一第二厚度之 氧化層。最後，重複前述步驟，則可在元件區上形成複數 層厚度不同的氧化層。 爲讓本發明之上述和其他目的、特徵、和優點能更明顯 易懂’下文特舉一較佳實施例，並配合所附圖式，作詳細 5 - 本紙張尺度中) A4規格（21〇χ297公楚） ~ — (請先閱讀背面之注意事_ Φ, >項再填· 裝-- :寫本頁)Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 471064 2060T WF.DOC / 006 A7 B7 * V. Description of the Invention (/) The present invention relates to a method for manufacturing an oxide layer, and in particular to an oxide layer having a different thickness Manufacturing method. Among integrated circuit components, different circuits require close coordination of inadequate circuit components with different basic operating characteristics. In order to respond to the competitiveness and diversity of circuit components, some components must have different oxide layer thicknesses to meet the requirements of different operating voltages or capacitors. Field effect transistors (FETs) are one of the most widely used components in integrated circuits, because field effect transistor circuits can perform many different functions, and the manufacture of field effect transistors is highly reproducible and predictable. Sex. Another advantage of field effect transistor devices is that they can be smaller in size and can be tightly packed. A typical field effect transistor is composed of a source and a drain formed on a substrate separated by a channel region, and a conductive gate. The source and the drain are on both sides of the channel region, and the alarm is formed by a gate. The oxide layer is separated from the channel region. The operating characteristics of a field effect transistor are determined by many different device configurations, including the thickness of the gate oxide layer. The upper limit of the operating voltage of a field effect transistor is mainly related to the breakdown voltage that the gate oxide layer can withstand. This voltage is mainly determined by the thickness of the gate oxide layer. Since field-effect transistors with different functions are designed to operate at different voltages', practical field-effect transistors should have different gate oxide layer thicknesses to provide different operating voltages. The field effect transistor can also use gate oxide layers of different thicknesses to achieve high operating speed (thinner gate oxide) or low leakage current (thicker gate oxide) of the field effect transistor. Therefore, the field-effect transistor in the memory element may have a gate oxide layer of a first thickness, and at high speed, 3 paper sizes are applicable to the Chinese National Standard (CNS) A4 specification (21 × 297 mm) I Binding (Please read the precautions on the back before filling this page) 471064 2060TWF.DOC / 006 A7 B7 · Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of Invention (2), Fields in Low-Voltage Logic Circuits The effect transistor may have a second, significantly thinner gate oxide layer. Usually, the memory and logic circuits are located on different chips. When the memory and the logic circuit are located on different wafers, a comprehensive thermal oxidation process can be used for different wafers to generate gate oxides of different thicknesses. Gate oxides of different thicknesses are made by exposing different substrates to an oxidizing environment and controlling different exposure times. Therefore, recently, wafer design has moved toward the use of transistors having different thicknesses of oxides to combine into a circuit on a single wafer to obtain different operating voltages or to change other operating characteristics. Figures 1A to 1C are conventional manufacturing methods used to form oxide layers of different thicknesses. Referring to FIG. 1A, first, an element isolation structure 11 is formed on a semiconductor substrate 10, then an oxide layer 12 is formed on the surface of the substrate 10 by a thermal oxidation method, and then a nitride layer 13 is deposited on the oxide layer 12. After that, the device region is defined, and a nitride layer and an oxide layer are etched to define different device regions 14 and 15. An oxide layer 16 is grown on the substrate surface of the device region 15 as a gate of the device region 15. Oxide layer. The gate oxide layer of the device region 14 is composed of an oxide layer 12 and a nitride layer 13. Therefore, the thicknesses of the gate oxide layers in the device region 14 and the device region 15 are not the same. The main purpose of the present invention is to provide an oxide layer with different thicknesses that can be applied to different operating voltages and capacitors, and the manufacturing process is simpler than conventional. In order to achieve the above-mentioned object, the present invention provides a method for manufacturing oxide layers with different thicknesses. First, a semiconductor substrate is provided, and the semiconductor substrate has a 4 paper size applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) ( (Please read the precautions on the back before filling this page) ♦ Please fill in 1 item again.-Order 471064 2060T WF.DOC / 006 A 7 B7 ^ Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A device region and a second element region are connected to each other to form a first oxide layer on a surface of the semiconductor element and the first element region. A dopant is provided to the first oxide layer on the first device region, such as nitrogen, and a second oxide layer is formed on the first oxide layer on the first device region, wherein the first oxide layer and the second oxide layer are The layers have different characteristics, so that the second oxide layer can be used as a hard mask, and the thickness of the second oxide layer is smaller than the thickness of the first oxide layer. Finally, the second oxide layer on the first device region is removed, and the surface of the first oxide layer is exposed. Then, the thickness of the first oxide layer on the first device region is greater than the thickness of the first oxide layer on the second device region. According to the above manufacturing method, oxide layers with different thicknesses can be formed in different element regions. In addition, a plurality of oxide layers of different thicknesses may be formed on different element regions. The manufacturing method is as follows: A semiconductor substrate is provided, and the semiconductor substrate has a first element region and a second element region. Next, a first oxide layer is formed on the semiconductor substrate, the surface of the first element region and the surface of the second element region. A dopant is provided to the first oxide layer on the first element region, and a second oxide layer is formed on the first oxide layer. The first oxide layer and the second oxide layer have different properties, so that the second oxide layer can be As a hard mask, the thickness of the second oxide layer is smaller than the thickness of the first oxide layer. Finally, the second oxide layer on the first element region is removed to expose the surface of the first oxide layer, so that the surface of the first element region forms an oxide layer of a first thickness, and the second element region forms an oxide layer of a second thickness. Finally, by repeating the foregoing steps, a plurality of oxide layers having different thicknesses can be formed on the element region. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following exemplifies a preferred embodiment, in conjunction with the accompanying drawings, to make a detailed 5-this paper size) A4 size (21 χ297 公 楚) ~ — (Please read the notes on the back _ Φ, > then fill in and install-: write this page)
'1T 471064 2060TWF.DOC/006 A7 B7 五、發明説明（¥) 說明如下： 圖式之簡單說明： 第1A圖至第lc圖係顯示一種習知技藝，其不同厚度 氧化層製造方法之流程剖面圖。 第2A圖至第2C圖係顯示根據本發明較佳實施例，使 用不同厚度氧化層製造方法之流程剖面圖。 其中’各圖標號與構件名稱之關係如下： 1〇、20 :基底 U、21 :元件隔離結構 12、16、22、22a、22c :氧化層 13 :氮化物層 22b :植入氮之氧化層 24 :光阻 實施例 第2A圖至第2C圖所示，爲根據本發明一較佳實施例， 揭示不同厚度氧化層製造方法之流程剖面圖。 本發明提供一種形成不同厚度氧化層的製造方法，可同 時形成不同厚度的氧化層，使其能承受不同操作電壓，而 使隨後形成的電路，能因此而具有不同的元件特性，以拓 展元件與電路的多樣性，提高產品的競爭力。因此本發明 不同厚度氧化層的製造方法，其可適用在積體電路製程 中’任何需要不同厚度氧化層之處，且不侷限在閘極氧化 層的使用。然在此，爲方便說明，仍以閘極氧化層作爲本 發明之一較佳實施例。 6 - 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） -----------------1T------ - f (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 471064 2060TWF.DOC/006 A7 B7 五、發明説明（$ ) 請參照第2A圖。首先在半導體矽基底2〇形成元件隔 離結構21，例如爲以LOCOS法形成的場氧化層，或是淺 溝渠隔離結構，兀件隔離結構係用以隔絕不同的元件區， 以防止相鄰的電晶體發生短路。接著，在基底20與元件隔 離結構表面形成一氧化層22，其可以熱氧化法形成，而厚 度約在120-210埃左右。 請參照第2B圖。在欲形成之一元件區23的氧化層22 上設有一光阻24，再植入摻質25於未覆蓋光阻的氧化層 中，而定義出另一兀件區26。摻質例如爲氮氣，氮氣植入 深度’可以植入能量控制’且植入深度，視元件所需氧化 層厚度而決定，植入能量約爲5-1 Okev左右。其中，經摻雜 氮氣在元件區26之氧化層22，其植入氮氣區域的氧化層 22b，其性質不同於原來形成的氧化層22，例如，其對同一 蝕刻劑，會具有不同的蝕刻率，因此氧化層22a可作爲一 蝕刻步驟的硬罩幕。 最後去除氧化層22b，例如以B0E(—種含HF的溶劑) 或熱磷酸去除氧化層22b，再以電漿去除光阻24，形成如 第2C圖所示之氧化層22c。在經上述之製造流程後，元件 區23與元件區26氧化層的厚度不同，其中，元件區23的 氧化層厚度大於元件區26的氧化層厚度。 之後，再以傳統技術在氧化層上形成所需元件。例如， 當氧化層22c作爲墊氧化層時，則可在其表面上再形成複 晶矽層，並經微影蝕刻後形成閘極，再以絕緣層覆蓋，並 形成間隙壁以保護閘極側邊，再以雜質植入基底，形成源/ 7 - 本紙張尺度適用中國國家榡準（CNS ) M規格（210X297公釐） (請先聞讀背面之注意事項再填寫本頁) f 項再填」 、-2-t> 經濟部中央標準局員工消費合作社印繁 471064 2060TWF.DOC/006 人 7 B7 * 五、發明説明（ό) 汲極區’而完成MOS電晶體。 同樣地，亦可以重複上述第2B圖與第2C圖的製造步 驟，藉著氮氣摻入氧化層，形成不同性質的氧化層，對於 同一蝕刻劑而言，具有不同的蝕刻選擇率之由，而在原本 已有二層不同厚度的氧化層上，依元件需要再增加不同厚 度的氧化層，而最後可形成複數層不同厚度的氧化層。 如上所述，依照較佳實施例形成不同厚度之氧化物，其 製程較習知技藝形成不同厚度的氧化層爲簡易，且氧化層 的品質亦較佳，因此除了可提供不同元件操作所需承受的 電壓外，同時亦可作爲元件所需之不同厚度氧化層，或應 用在閘極氧化層上。 雖然本發明已以一較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事' 蟀 項再填- 裝-- :寫本頁)'1T 471064 2060TWF.DOC / 006 A7 B7 V. Description of the invention (¥) The description is as follows: Figures 1A to lc show a conventional technique, a cross-section of the process of manufacturing a different thickness oxide layer Illustration. Figures 2A to 2C are cross-sectional views showing the flow of a method for manufacturing oxide layers with different thicknesses according to a preferred embodiment of the present invention. Among them, the relationship between each icon number and the component name is as follows: 10, 20: substrate U, 21: element isolation structure 12, 16, 22, 22a, 22c: oxide layer 13: nitride layer 22b: implanted nitrogen oxide layer 24: Photoresist embodiments shown in FIG. 2A to FIG. 2C are cross-sectional views illustrating the process of manufacturing oxide layers with different thicknesses according to a preferred embodiment of the present invention. The invention provides a manufacturing method for forming oxide layers with different thicknesses, which can form oxide layers with different thicknesses at the same time so that they can withstand different operating voltages, so that the subsequently formed circuits can have different element characteristics, so as to expand the components and The diversity of circuits improves the competitiveness of products. Therefore, the manufacturing method of the oxide layer with different thicknesses of the present invention can be applied to any place where an oxide layer with different thickness is required in the integrated circuit manufacturing process, and is not limited to the use of the gate oxide layer. However, for convenience of explanation, the gate oxide layer is still used as a preferred embodiment of the present invention. 6-This paper size applies to China National Standard (CNS) A4 (210X 297mm) ----------------- 1T -------f (Please read first Note on the back, please fill in this page again) Printed by the Employees' Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 471064 2060TWF.DOC / 006 A7 B7 V. Description of Invention ($) Please refer to Figure 2A. First, an element isolation structure 21 is formed on a semiconductor silicon substrate 20, such as a field oxide layer formed by the LOCOS method, or a shallow trench isolation structure. The element isolation structure is used to isolate different element regions to prevent adjacent electrical circuits. The crystal is shorted. Next, an oxide layer 22 is formed on the surface of the substrate 20 and the element isolation structure, which can be formed by a thermal oxidation method and has a thickness of about 120-210 angstroms. Please refer to Figure 2B. A photoresist 24 is provided on the oxide layer 22 of an element region 23 to be formed, and a dopant 25 is implanted in the oxide layer not covered with the photoresist to define another element region 26. The dopant is, for example, nitrogen. The implantation depth of the nitrogen can be controlled by the implantation energy and the implantation depth is determined by the thickness of the oxide layer required. The implantation energy is about 5-1 Okev. Among them, the oxide layer 22 doped with nitrogen in the element region 26 and implanted into the oxide layer 22b in the nitrogen region has properties different from those of the originally formed oxide layer 22. For example, it has different etching rates for the same etchant. Therefore, the oxide layer 22a can be used as a hard mask for an etching step. Finally, the oxide layer 22b is removed, for example, BOE (a solvent containing HF) or hot phosphoric acid is used to remove the oxide layer 22b, and then the photoresist 24 is removed by a plasma to form an oxide layer 22c as shown in FIG. 2C. After the above-mentioned manufacturing process, the thicknesses of the oxide layers of the device region 23 and the device region 26 are different. The thickness of the oxide layer of the device region 23 is greater than the thickness of the oxide layer of the device region 26. After that, the required elements are formed on the oxide layer by conventional techniques. For example, when the oxide layer 22c is used as a pad oxide layer, a polycrystalline silicon layer can be further formed on the surface thereof, and a gate electrode is formed after lithographic etching, and then the gate is covered with an insulating layer to form a gap to protect the gate Side, and then implant the substrate with impurities to form the source / 7-This paper size is applicable to China National Standard (CNS) M specification (210X297 mm) (Please read the precautions on the back before filling out this page) and then fill in the f item ”-2-t > Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs, Yinfan 471064 2060TWF.DOC / 006 People 7 B7 * V. Description of the invention (the drain region) to complete the MOS transistor. Similarly, the manufacturing steps shown in Figures 2B and 2C can be repeated. Oxide layers are mixed with nitrogen to form oxide layers with different properties. For the same etchant, they have different etching selectivity. On the existing two oxide layers with different thicknesses, different thickness oxide layers are added according to the needs of the device, and finally multiple oxide layers with different thicknesses can be formed. As described above, the formation of oxides of different thicknesses according to the preferred embodiment is simpler than the formation of oxide layers of different thicknesses by conventional techniques, and the quality of the oxide layers is also better. In addition to the high voltage, it can also be used as an oxide layer of different thickness for the device, or applied on the gate oxide layer. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. (Please read the notes on the back '蟀 before filling-Pack-: Write this page)
、1T 4 經濟部中央標準局員工消費合作社印製 8 本紙張尺度適财關家榡準（CNS ) Α4規格（21GX297公爱）、 1T 4 Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 8 This paper is suitable for financial and family standards (CNS) Α4 size (21GX297 public love)