經濟部智慧財產局員工消費合作社印製 t A7 ^_____B7__ 五、發明謀明（/ ) 發明之詳細說明： 發明之技術領域： 本發明是瀾於在積體電路中形成電晶體的方法，特別 是形成適用於十億位元之動態隨機存取記憶體之電晶體的 方法。 發明背景： 隨著半導體的技術跨入深次微米的領域，爲了降低積 體電路的製造成本以提高產品的競爭力，積體電路的集積 密度(Packing Density)亦隨著大幅增加。爲了維持元件 的穩定性與可靠性(Reliability)，具有低耗能優點的互 補式金氧半場效電晶體(以後皆簡稱爲CMOS)成爲積體電路 設計的主流。 然而CMOS也並非完美無缺，除了結構上較NM0S複雜 外’ NM0S和PM0S彼此間的隔離（Isolation)也非常重要， 否則所謂的閉鎖現象(Latch Up)便會發生，使CMOS的操作 癱瘓。爲了避免閉鎖現象的發生，多種解決方法已被提 出，例如護環（Guard Ring)以及絕緣層上有矽(Silicon on Insulator;以後皆簡稱爲SOI)等。 SOI的原理係在底材矽的表面不遠處增加一層介電 層，讓用以製造CMOS元件的底材矽表面與矽主體之間，以 這一層介電層加以隔離。這種以SOI來製作積體電路技術 的優點，在電性上，因爲形成CMOS的區域並不與底材矽相 連，因此CMOS電晶體會發生閉鎖的一些途徑，例如源極與 底材，井與底材等的連接，將因所述介電層的隔絕而消 --------1------------^ I ^---------O'· (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)M規格（210 X 297公釐） 經濟部智慧財產局員工消費合作杜印製 厶'δ厶Α7 ^ Β7 玉、發明說明（>) 失，使閉鎖現象不再發生，並增加MOS元件對α粒子所導 致的軟錯記(Soft Error)問題的免疫力，且因寄生電容較 小而使電路的操作速度加快。至於在製程上，因爲容許的 線寬可以比較小，因此所形成積體電路的集積密度可以大 幅增加。 傳統上製作SOI晶片的方法有兩種，分別是晶片黏著 法（Bonded Wafer)和氧植入隔離法（Separation by Implanted Oxygen;以後皆簡稱SIMOX)，其中又以SIMOX 法較佳。所述SIM0X製程分爲兩大主要步驟，首先在加熱 至約600°C晶片上，把氧離子植入晶片裡，然後再把晶片 置於溫度高達130(TC以上的環境數個小時，把經離子植入 而遭破壞的晶片表面的矽結構，恢復成低缺陷濃度的單晶 矽，並使植入的氧與底材矽結合成二氧化矽。 然而，所述氧離子植入的能量高達150至2G0KeV以便 穿透晶片至0.1到0. 2微米的深度，其植入的劑量必須高達 1E18離子/平方公分以便形成一層約0.1-G. 5微米厚的氧化 矽層，因此需要一部特殊且相當昂貴的離子植入機方可執 行所述SIM0X製程。另外晶片須置於溫度高達13G0°C以上 的環境數個小時之久，亦使產量大幅降低。因此SIM0X製 程使得SOI晶片變得相當地昂貴，大幅增加積體電路製造 的成本。 因此，開發出一種較不花成本，但仍能獲致與SOI晶 片相同效果的製程方法，便成爲各個半導體公司相當重要 的課題。 / 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 2右公釐） (請先閱讀背面之注意事項再填寫本頁) --------訂---------線！0. 經濟部智慧財產局員工消費合作社印製 f 418428 A7 j_B7_ 五、發明說明（）） 發明之簡要說明： 本發明之主要目的是提供一種積體電路中形成電晶體 的方法。 本發明之另一個目的是提供一種形成絕緣層上有砍 (Silicon on Insulator; SOI)的方法。 本發明之另一個目的是提供一種製造十億位元動態隨 機存取記憶體的新元件設計。 本發明之主要製程如下：首先在一矽基板上形成一層 介電層，接著利用微影與非均向蝕刻技術形成中間極板區 (Central Node Region)。接下來形成一層嘉晶砂層。形 成所述磊晶矽層，係先以低壓化學氣相沉積法形成一層非 晶矽層(Amorphous Silicon)，再將所述非晶砍層歷經550 至650°C的溫度，以所述中間極板區的矽基板爲晶種(Seed) 而成長成單晶(Single Crystal)。本發明適合關鍵尺寸 (Critical Dimension; CD)爲0_ 18微米以及0 18微米以下 之積體電路的製作。 接下來定義主動元件區。所述定義主動元件區，係先 形成一層氧化矽層，再形成一層氮化矽層，接著利用微影 與非均向蝕刻技術定義主動元件區。所述非均向蝕刻區分 爲三個步驟，首先蝕刻氮化矽層，再蝕刻氧化矽層，最後 再触刻磊晶矽層，以定義出主動元件區。接著進行一道熱 氧化步驟，之後將所述氮化矽層和氧化矽層去除。接下來 形成電晶體結構，本發明所述之在積體電路中形成電晶體 的方法於焉完成。 本紙張尺度適用中國國家標準（CNS)A.l規格（210 X 2杏公t ) ~ (請先閱讀背面之注意事項再填寫本頁) --------.iri——-----線乂'""^Γ. Α7Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs t A7 ^ _____ B7__ V. Inventive details (/) Detailed description of the invention: Technical field of the invention: The present invention is a method for forming transistors in integrated circuits, especially A method for forming a transistor suitable for gigabit dynamic random access memory. Background of the Invention: As semiconductor technology enters the field of deep sub-microns, in order to reduce the manufacturing cost of integrated circuits and improve the competitiveness of products, the packing density of integrated circuits has also increased significantly. In order to maintain the stability and reliability of the device, complementary metal-oxide-semiconductor field-effect transistors (hereinafter referred to as CMOS) with the advantage of low power consumption have become the mainstream of integrated circuit design. However, CMOS is not perfect. In addition to being more complex than NM0S, the isolation between NM0S and PM0S is also very important. Otherwise, the so-called latch-up phenomenon will occur, which will paralyze the operation of CMOS. In order to avoid the occurrence of latch-up, various solutions have been proposed, such as Guard Ring and Silicon on Insulator (hereinafter referred to as SOI). The principle of SOI is to add a dielectric layer not far from the surface of the substrate silicon, so that the substrate used to manufacture the CMOS device is separated from the silicon surface by the dielectric layer. The advantage of this integrated circuit technology using SOI is that, in terms of electrical properties, because the area where the CMOS is formed is not connected to the substrate silicon, there are some ways in which CMOS transistors can be blocked, such as the source and the substrate. The connection with the substrate will be eliminated due to the isolation of the dielectric layer -------- 1 ------------ ^ I ^ -------- -O '· (Please read the notes on the back before filling in this page) This paper size applies the Chinese National Standard (CNS) M specification (210 X 297 mm). The Intellectual Property Bureau of the Ministry of Economic Affairs' employee consumption cooperation prints' 厶厶 Α7 ^ Β7 Jade, description of the invention (>), so that the blocking phenomenon no longer occurs, and increase the MOS device's immunity to the soft error caused by alpha particles (Soft Error), and because the parasitic capacitance is small Speed up the operation of the circuit. As for the manufacturing process, because the allowable line width can be relatively small, the accumulation density of the integrated circuit formed can be greatly increased. There are two traditional methods for making SOI wafers, namely the wafer bonding method (Separation by Implanted Oxygen; hereinafter referred to as SIMOX), and the SIMOX method is preferred. The SIM0X process is divided into two main steps. First, the wafer is heated to about 600 ° C, oxygen ions are implanted into the wafer, and then the wafer is placed in an environment with a temperature of 130 ° C or higher for several hours. The silicon structure on the surface of the wafer damaged by ion implantation is restored to a single crystal silicon with a low defect concentration, and the implanted oxygen is combined with the substrate silicon to form silicon dioxide. However, the energy of the oxygen ion implantation is as high as 150 to 2G0KeV in order to penetrate the wafer to a depth of 0.1 to 0.2 microns, the implanted dose must be as high as 1E18 ions / cm 2 in order to form a layer of about 0.1-G. 5 microns thick silicon oxide, so a special And the relatively expensive ion implantation machine can perform the SIM0X process. In addition, the wafer must be placed in an environment with a temperature as high as 13G0 ° C for several hours, which also significantly reduces the yield. Therefore, the SIM0X process makes the SOI wafers quite equivalent. It is expensive, which greatly increases the cost of integrated circuit manufacturing. Therefore, it is very important for each semiconductor company to develop a manufacturing method that does not cost much but still achieves the same effect as an SOI wafer. Topics / This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 2 mm) (Please read the notes on the back before filling this page) -------- Order ----- ---- Line! 0. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs f 418428 A7 j_B7_ V. Description of the invention ()) Brief description of the invention: The main purpose of the present invention is to provide a transistor formed in a integrated circuit. method. Another object of the present invention is to provide a method for forming a Silicon on Insulator (SOI). Another object of the present invention is to provide a new component design for manufacturing a gigabit dynamic random access memory. The main process of the present invention is as follows: first, a dielectric layer is formed on a silicon substrate, and then a lithography and anisotropic etching techniques are used to form a central node region. Next, a layer of carmine sand is formed. To form the epitaxial silicon layer, an Amorphous Silicon layer is first formed by a low-pressure chemical vapor deposition method, and then the amorphous layer is subjected to a temperature of 550 to 650 ° C, and the intermediate electrode is formed. The silicon substrate in the plate area is a seed and grows into a single crystal. The invention is suitable for the fabrication of integrated circuits with a critical dimension (CD) of 0-18 microns and below 0-18 microns. Next, define the active component area. The active device region is defined by first forming a silicon oxide layer and then a silicon nitride layer, and then using lithography and anisotropic etching techniques to define the active device region. The non-uniform etching is divided into three steps. First, the silicon nitride layer is etched, then the silicon oxide layer is etched, and then the epitaxial silicon layer is etched to define the active device region. Then, a thermal oxidation step is performed, and then the silicon nitride layer and the silicon oxide layer are removed. Next, a transistor structure is formed, and the method for forming a transistor in a integrated circuit according to the present invention is completed. This paper size applies Chinese National Standard (CNS) Al specification (210 X 2 apricot t) ~ (Please read the precautions on the back before filling this page) --------. Iri -------- -线 乂 '" " ^ Γ. Α7
Γ 41842d 五、發明說明（f) 圖式之簡要說明： 圖一爲本發明第一實施例中形成中間極板區的製程剖面 圖。 圖二爲本發明第一實施例中形成磊晶矽層的製程剖面 圖。 圖三爲本發明第一實施例中定義主動元件區的製程剖面 圖。 圖四爲本發明第一實施例中進行熱氧化步驟的製程剖面 圖。 圖五爲本發明第一實施例中形成電晶體結構的製程剖面 圖。 圖六爲本發明第二實施例中定義出主動元件區並形成淺 渠溝的製程剖面圚。 圖七爲本發明第二實施例中進行熱氧化步驟並形成逢渠 溝隔離的製程剖面圖。 圖八爲本發明第二實施例中形成電晶體結構的製程剖面 圖。 (請先閱讀背面之注意事項再填寫本頁) 訂---------緯- 經濟部智慧財產局員工消費合作社印製 圖號說明： 10- 矽基板 20- 第一介電層 30- 光阻 40- 中間極板區 50- 嘉晶砂層 50A- 複晶砂區 50B-氧化矽區域 60- 氧化矽層 70- 氮化矽層 80- 光阻 本紙張尺度適用令國國家標準（CNS)A-l規格(210 X 2的公釐） ί 4 1 8 4 ^ ο Α7 Β7 五、發明說明（/") 90-電晶體結構 92-閘極 94-源極/汲極 110-淺渠溝隔離 120-電晶體結構 122-閘極 124-源極/汲極 91- 閘極氧化矽層 93- 間隙壁 100-淺渠溝 121-閘極氧化矽層 123-間隙壁 經濟部智慧財產局員工消費合作社印製 第一實施例 請參考圖一，首先在一砂基板10上形成一層第一介電 層20，接著塗佈上一層光阻30，利用微影與非均向蝕刻技 術形成中間極板區（Central Node Region)40。所述第一 介電層2G係利用化學氣相沉積法或熱氧化法所形成的氧化 砍層，其厚度介於1000至5G00埃之間。 請參考圖二，接下來形成一層磊晶矽層50。形成所述 磊晶矽層50，係先以低壓化學氣相沉積法(Low Pressure Chemical Vapor Deposition; LPCVD)形成一層非晶砍層 (Amorphous Silicon)，再將所述非晶砍層歷經550至650 °C的溫度，以所述中間極板區40的矽基板10爲晶種(Seed) 而成長成單晶（Single Crystal)，其厚度介於5QG至2000 埃之間。 如圖二所示，在距離所述中間極板區40較遠的區域， 所述磊晶矽層5G有一部份係屬於複晶矽區50A，其原因是 上述的磊晶製程將非晶矽轉換爲單晶的區域是有限的，距 (請先閱讀背面之注意事項再填寫本頁) -10¾--------訂---------線Γ''}· 本紙張尺度適用中國國家標準（CNS)A.l規格（210x2赉公釐）Γ 41842d V. Brief description of the invention (f) Schematic drawing: Fig. 1 is a cross-sectional view of a process for forming an intermediate electrode plate region in the first embodiment of the present invention. FIG. 2 is a cross-sectional view of a process of forming an epitaxial silicon layer in the first embodiment of the present invention. FIG. 3 is a cross-sectional view of a process for defining an active device region in the first embodiment of the present invention. FIG. 4 is a cross-sectional view of a process of performing a thermal oxidation step in the first embodiment of the present invention. Fig. 5 is a cross-sectional view of a process for forming a transistor structure in the first embodiment of the present invention. FIG. 6 is a cross-sectional view of a process in which an active device region is defined and a shallow trench is formed in a second embodiment of the present invention. FIG. 7 is a cross-sectional view of a process of performing a thermal oxidation step and forming a trench isolation in the second embodiment of the present invention. FIG. 8 is a cross-sectional view of a process for forming a transistor structure in a second embodiment of the present invention. (Please read the precautions on the back before filling out this page) Order --------- Wei-Printed number description of the employee consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs: 10- Silicon substrate 20- First dielectric layer 30- Photoresistance 40- Intermediate plate area 50- Jiajing sand layer 50A- Polycrystalline sand area 50B- Silicon oxide area 60- Silicon oxide layer 70- Silicon nitride layer 80- Photoresistance CNS) Al specification (210 X 2 mm) ί 4 1 8 4 ^ Α7 Β7 V. Description of the invention (") 90-transistor structure 92-gate 94-source / drain 110- shallow channel Trench isolation 120-transistor structure 122-gate 124-source / drain 91-gate silicon oxide layer 93-spacer 100-shallow trench 121-gate silicon oxide layer 123-smart wall intellectual property bureau The first embodiment printed by the employee consumer cooperative is shown in FIG. 1. First, a first dielectric layer 20 is formed on a sand substrate 10, and then a photoresist 30 is coated. The middle is formed by lithography and anisotropic etching techniques. The Central Node Region 40. The first dielectric layer 2G is an oxide layer formed by a chemical vapor deposition method or a thermal oxidation method, and has a thickness between 1000 and 5 G00 angstroms. Referring to FIG. 2, an epitaxial silicon layer 50 is formed next. The epitaxial silicon layer 50 is formed by first forming an amorphous crystalline layer (Low Pressure Chemical Vapor Deposition; LPCVD), and then passing the amorphous crystalline layer through 550 to 650 At a temperature of ° C, the silicon substrate 10 of the middle electrode plate region 40 is used as a seed to grow into a single crystal with a thickness between 5QG and 2000 angstroms. As shown in FIG. 2, in a region far from the intermediate plate region 40, the epitaxial silicon layer 5G partially belongs to the polycrystalline silicon region 50A. The reason is that the above-mentioned epitaxial process uses amorphous silicon. The area for conversion to single crystal is limited. (Please read the precautions on the back before filling this page) -10¾ -------- Order --------- line Γ ''} · This paper size applies to Chinese National Standard (CNS) Al specifications (210x2 赉 mm)
經濟部智慧財產局貝工消費合作社印製 五、發明說明（i;) 離晶種一定範圍之內的非晶矽可轉換爲單晶矽，但距離晶 種一定範圍之外的非晶矽僅可轉換爲複晶矽β利用本發明 方法所形成的磊晶矽層50，其形成單晶矽的區域係以中間 極板區40爲圚心，面積約爲G. 3平方微米的區域內。因本 發明所述的磊晶矽層50係用來形成電晶體的源極和汲極， 因此僅能運用單晶矽的區域。因此本發明適合關鍵尺寸 (Critical Dimension; CD)爲〇. 18微米以及〇. 18微米以下 之積體電路的製作β 請參考圖三，接下來定義主動元件區。所述定義主動 元件區，係先形成一層氧化砂層60，再形成一層氮化矽層 70，接著塗佈上光阻80，利用微影與非均向蝕刻技術定義 主動元件區。所述非均向蝕刻區分爲三個步驟，首先蝕刻 氮化矽層7G ’再蝕刻氧化矽層60，最後再蝕刻磊晶矽層 5G，以定義出主動元件區。 請參考圖四’進行一道熱氧化步驟，之後將所述氮化 矽層70和氧化矽層60去除。所述熱氧化步驟，目的係修補 因蝕刻而造成的缺陷，並且在所述磊晶矽層5Q上形成氧化 矽區域50Β，以做爲絕緣之用。 請參考圖五，接下來形成電晶體結構90。首先利闬微 影和非均向蝕刻技術定義出源極汲極區域，接著進行離子 佈植製程形成淡摻雜源極/汲極（Lightly Doped Drain/Source; LDD)(爲避免圖形太過複雜而未顯示在圖 上接著再進行一道離子佈植以進行啓始電壓調整。連 續形成一層氧化矽層及一層導電層，再利用微影與蝕刻技 本紙張尺度適用中國國家標準（CNS)A-l規格（210x2^公；SI >Printed by Shelley Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (i;) Amorphous silicon within a certain range from the seed can be converted to single crystal, but only The epitaxial silicon layer 50 formed by the method of the present invention can be converted into a polycrystalline silicon β. The region where the single crystal silicon is formed is centered on the intermediate electrode plate region 40 and has an area of about G. 3 square microns. Since the epitaxial silicon layer 50 according to the present invention is used to form a source and a drain of a transistor, only a region of single crystal silicon can be used. Therefore, the present invention is suitable for the fabrication of integrated circuits with a critical dimension (CD) of 0.18 micrometers and less than 0.01 micrometers. Please refer to FIG. 3, and then define an active device region. The active device area is defined by first forming an oxide sand layer 60, then forming a silicon nitride layer 70, and then coating a photoresist 80. The active device area is defined by lithography and anisotropic etching techniques. The non-uniform etching is divided into three steps. First, the silicon nitride layer 7G 'is etched, then the silicon oxide layer 60 is etched, and finally the epitaxial silicon layer 5G is etched to define the active device region. Please refer to FIG. 4 'to perform a thermal oxidation step, and then remove the silicon nitride layer 70 and the silicon oxide layer 60. The purpose of the thermal oxidation step is to repair defects caused by etching, and to form a silicon oxide region 50B on the epitaxial silicon layer 5Q for insulation. Referring to FIG. 5, a transistor structure 90 is formed next. First, lithography and anisotropic etching techniques are used to define the source-drain region, and then an ion implantation process is performed to form a lightly doped source / drain (LDD) (to prevent the graphics from being too complicated) It is not shown in the figure, and then an ion implantation is performed to adjust the initial voltage. A silicon oxide layer and a conductive layer are continuously formed, and then the photolithography and etching techniques are used. The paper size applies the Chinese National Standard (CNS) Al specification. (210x2 ^ male; SI >
-------線φ (請先閱讀背面之注意事項再填寫本頁) . 4184il〇 A7 _ B7 五、發明說明（7 ) 術形成閘極氧化矽層91和閘極92。接著沉積一層氧化矽層 再進行回蝕刻，以形成間隙壁(SideWall Spacer)93。最 後進行一道離子佈植製程以形成源極/汲極94。本發明所 述在積體電路中形成電晶體的方法於焉完成。 第二實施例 接下來揭露本發明另一最佳實施例，在第二實施例的 製程步驟中，在定義主動元件區之前的步驟皆和第一實施 例完全相同，因此不再贅述。 請參考圖六，接下來定義主動元件區。所述定義主動 元件區，係先形成一層氧化砍層60，再形成一層氮化矽層 70，塗佈上光阻80，利用微影與非均向蝕刻技術定義主動 元件區。所述非均向蝕刻區分爲三個步驟，首先蝕刻氮化 矽層70，再蝕刻氧化矽層60，最後再蝕刻磊晶矽層50和矽 基板10，以定義出主動元件區，並形成淺渠溝(Shallow Trench)100 。 請參考圖七，進行一道熱氧化步驟，之後將所述氮化 矽層70和氧化矽層60去除，並形成淺渠溝隔離(Shallow Trench Isolation; STD11Q。所述熱氧化步驟，目的係 修補因蝕刻而造成的缺陷。所述形成淺渠溝隔離110，係 先形成一層氧化矽層將所述淺渠溝1GG填滿，再利用化學 機械研磨法(Chemical Mechanical Polishing; CMP)將位 於所述磊晶矽層50上方之所述氧化矽層磨去，以形成淺渠 溝隔離110。 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 2赉公釐） (請先閱讀背面之注意事項再填寫本頁) 0^------!訂·--------線0 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 416428 A7 B7 五、發明說明（y) 請參考圚八’接下來形成電晶體結構120。首先利用 微影和非均向蝕刻技術定義出源極汲極區域，接著進行離 子佈植製程形成淡摻雜源極/汲極（爲避免圖形太過複雜 而未顯示在圖上）。接著再進行一道離子佈植以進行啓始 電壓調整。連續形成一層氧化矽層及一層導電層，再利用 微影與蝕刻技術形成閘極氧化矽層121和閘極122。接著沉 積一層氧化矽層再進行回蝕刻，以形成間隙壁123。最後 進行一道離子佈植製程以形成源極/汲極124。本發明所述 在積體電路中形成電晶體的方法於焉完成。 運用本發明所形成的電晶體有如下優點： 1·可形成淺汲極/源極接面，大幅改善短通道效應 (Short channel effect)。 2·可使底材電流(Substrate Current)降到最低。 3. 降低次啓始電流(Subthreshold Current) 〇 4. CMOS電晶體發生閉鎖的一些途徑，例如源極與底材，井 與底材等的連接，將因所述介電層的隔絕而消失，使閉 鎖現象不再發生。 5. 將本發明應用在動態隨機存取記憶體上，可降低漏電流 (Leakage Current)，因而大幅增加電容器的再補充 (Re fresh)時間。 6. 本發明提供一種製造十億位元動態隨機存取記憶體的新 元件設計。 7. 非常適用於負偏差(negative biased)字元線結構的設 計0 -----；—^-----0裝-----------訂---------線Ό. (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 * 2於公釐） (4184 28 at _B7__ 五、發明說明（7) 上述係以兩個較佳實施例來闡述本發明，而非限制本 發明的範圍。並且，熟知半導體技藝人士皆能明瞭，適當 而作些微的改變及調整，仍將不失本發明之要義所在，亦 不脫離本發明精神和範圍。 (請先闉讀背面之注意事項再填寫本頁) -「)衣------— —訂----------線 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A.l規格 (210 X 公釐）------- Line φ (Please read the precautions on the back before filling this page). 4184il0 A7 _ B7 V. Description of the invention (7) The gate oxide silicon layer 91 and gate 92 are formed by the operation. Next, a silicon oxide layer is deposited and then etched back to form a SideWall Spacer 93. A final ion implantation process is performed to form the source / drain 94. The method for forming a transistor in an integrated circuit according to the present invention is completed. Second Embodiment Next, another preferred embodiment of the present invention is disclosed. In the process steps of the second embodiment, the steps before the definition of the active device area are exactly the same as those of the first embodiment, and therefore will not be described again. Please refer to Figure 6, next define the active device area. The active device region is defined by first forming an oxide layer 60, then forming a silicon nitride layer 70, coating a photoresist 80, and defining the active device region using lithography and anisotropic etching techniques. The non-uniform etching is divided into three steps. First, the silicon nitride layer 70 is etched, then the silicon oxide layer 60 is etched, and then the epitaxial silicon layer 50 and the silicon substrate 10 are etched to define an active device region and form a shallow layer. Ditch (Shallow Trench) 100. Referring to FIG. 7, a thermal oxidation step is performed, and then the silicon nitride layer 70 and the silicon oxide layer 60 are removed, and a shallow trench isolation (Shallow Trench Isolation; STD11Q) is formed. The purpose of the thermal oxidation step is to repair the cause Defects caused by etching. The formation of the shallow trench isolation 110 is to form a silicon oxide layer to fill the shallow trench 1GG, and then use Chemical Mechanical Polishing (CMP) to be located in the Lei. The silicon oxide layer above the crystalline silicon layer 50 is abraded to form a shallow trench isolation 110. This paper size applies to China National Standard (CNS) A4 (210 X 2 mm) (Please read the note on the back first Please fill in this page for matters) 0 ^ ------! Order · -------- Line 0 Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 416428 A7 B7 V. Description of the invention (y) Please refer to 28. The next step is to form the transistor structure 120. First, the source and drain regions are defined by lithography and anisotropic etching, and then the ion implantation process is performed to form a lightly doped source. / Drain (to avoid graphics too much (Not shown on the figure). Then, an ion implantation is performed to adjust the starting voltage. A silicon oxide layer and a conductive layer are continuously formed, and the gate silicon oxide layer 121 and the gate are formed by lithography and etching technology. Electrode 122. Next, a silicon oxide layer is deposited and then etched back to form the gap wall 123. Finally, an ion implantation process is performed to form a source / drain 124. The method for forming a transistor in an integrated circuit according to the present invention Completed in Yu. The transistor formed by using the present invention has the following advantages: 1. It can form a shallow drain / source interface, which greatly improves the short channel effect. 2. It can make the substrate current (Substrate Current). ) To a minimum 3. Reduce the Subthreshold Current 〇4. Some methods of CMOS transistor latch-up, such as the source and substrate, well and substrate connection, will be due to the dielectric layer Isolation and disappearance, so that the latch-up phenomenon no longer occurs. 5. Applying the present invention to dynamic random access memory can reduce the Leakage Current, thus greatly increasing the replenishment of the capacitor (Re (fresh) time. 6. The present invention provides a new device design for manufacturing 1 billion bits of dynamic random access memory. 7. Very suitable for the design of negatively biased word line structures 0 -----; — ^ ----- 0 Pack ----------- Order --------- Lines. (Please read the precautions on the back before filling this page) This paper size applies Chinese National Standard (CNS) A4 specification (210 * 2 in mm) (4184 28 at _B7__ V. Description of the invention (7) The above description uses two preferred embodiments to illustrate the invention, but not to limit the scope of the invention. Moreover, those skilled in the art of semiconductors can understand that making appropriate changes and adjustments will still not lose the essence of the invention, nor depart from the spirit and scope of the invention. (Please read the precautions on the back before filling out this page)-") Clothing ------------ Order ------------ Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Standards apply to Chinese National Standard (CNS) Al specifications (210 X mm)