TW394970B - The formation of semiconductor substrate surface insulation film and its related processes - Google Patents

The formation of semiconductor substrate surface insulation film and its related processes Download PDF

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Publication number
TW394970B
TW394970B TW087109635A TW87109635A TW394970B TW 394970 B TW394970 B TW 394970B TW 087109635 A TW087109635 A TW 087109635A TW 87109635 A TW87109635 A TW 87109635A TW 394970 B TW394970 B TW 394970B
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Taiwan
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insulating film
semiconductor substrate
forming
patent application
scope
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TW087109635A
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English (en)
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Hikaru Kobayashi
Kenji Yoneda
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Matsushita Electronics Corp
Japan Science & Tech Corp
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Description

A7 B7 五、發明說明(I ) 在半導體裝置、特別是MNOS (金屬氧氮化半導體 )電晶體、MN 0 S電容之閘極絕緣膜以及電容絕緣膜, 當採用矽裝置的情形,會使用到氮化矽膜。由於該等絕緣 膜係被要求著高絕緣擊穿耐壓及高絕緣擊穿電荷量,因此 晶圓之洗淨爲一非常重要之過程。又,於洗淨晶圓的同時 ,亦要求著低固定電荷密度、低界面態(interface state)密度 〇 另一方面,伴隨著裝置的精細化、高集積化,閘極絕 緣膜以及電容絕緣膜亦隨之薄膜化,例如在0.1#m的設計 準則下要求著3nm之薄膜閘極絕緣膜。 以往形成MN 0 S電晶體之閘極絕緣膜所使用之方法 係於1000°C左右之高溫中,將半導體基板暴露一氧化二氮 (N2〇)或一氧化氮(NO)的周圍氣氛中,或是於氨氣周圍氣氛 中將晶圓加熱至700°C左右》 除此之外,做爲以低溫形成氧氮化膜的方法,有一邊 照射紫外線一邊進行熱氧氮化之方法、藉由將矽暴露於氮 化合物或氮氣之電漿中直接氧氮化之方法,但無論何種方 法,皆無法以良好之控制性以及再現性來形成厚度薄且高 品質的氧氮化膜。 以往使用^^2〇氣體行熱氧氮化時需高溫加熱,又有 氧氮化膜所內含之氮原子的量少與二氧化矽膜的薄膜性質 並未十分改善之問題。又,使用N 0氣體行熱氧氮化時, 雖然加熱溫度降至900°C左右,且氧氮化膜所內含之氮原 子的量有若干增加,但有無法成長具既定以上薄膜厚度之 3 (請先閱讀背面之注意事項再填寫本頁) I n II ϋ 一:eJ· n ϋ n 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4-規格(210 X 297公釐) 經濟部智慧財產局員工消费合作社印製 A7 ___B7____ 五、發明說明(Y) 氧氮化膜的問題。又,使用氨氣行熱氧氮化時,氧氮化膜 中將含大量的氫,由於氫扮演著捕集電子的角色,因而薄 膜性質變差,從而造成之問題爲,爲了去除氫,必須於氧 氮化膜形成之後加熱至i〇〇〇°c左右或進行氧化。 又,藉由電漿將矽直接氧氮化時,有因電漿衝擊造成 薄膜性質不良的問題,特別是界面態的發生,不僅造成電 晶體之熱載子特性變差,亦會引起電晶體之臨限電壓 (threshold voltage)的不安定、載子之移動度的降低等對細微 裝置而言致命性的問題。 再者,伴隨元件的細微化,是以亦要求於熱處理過程 之低溫化,其理由係以高溫加熱時將會有摻質的擴散與缺 陷的形成等問題β就以R F電漿將二氧化矽膜氧氮化而言 ,當使用ΝΗ3電漿之時,雖然可於薄膜中摻入大量之氮原 子,但同時於薄膜中亦含有大量之氫原子,而有薄膜性質 變差的問題。 又,使用Ν2電漿的情形,有薄膜中之氮原子含有量少 、薄膜性質未十分改善之問題〔例如可參照P. Fazan,Μ. Dutoit and Μ· Ilegems,(Appl. Surf. Sci.) 30 章,224 頁 ’ 1987 年〕。 〔發明摘要〕 爲解決上述習知之含氮原子絕緣膜的形成方法所具有 的問題,本發明之目的乃提供一種半導體基板表面的絕緣 膜之形成方法以及其形成裝置,其不需高溫加熱,即可高 控制性地於半導體基板的表面上形成含大量氮原子之高品 4 _ 本紙張尺度適用t國國家標準(CNS)A4規格(210 X 297公釐) ---1--------^褒--------訂---------線f . (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 A7 _______B7___ 五、發明說明(j ) 質的絕緣膜。 爲求達成上述目的’本發明特徵係提供一種至少於半 導體基板表面含絕緣膜之半導體裝置,且絕緣膜之厚度介 於1〜20nm之範圍。 又,於半導體裝置中’暴露於以電子衝擊所產生之電 漿的絕緣膜以二氧化矽膜爲佳,二氧化矽膜可使用以熱氧 化、化學氣相成長、化學氧化、物理氣相成長及電發促使 化學氣相成長等所形成之物。 又,於上述半導體裝置中,半導體基板以擇自單結晶 砂、多結晶矽、非結晶砂、砷化鎵、磷化銦、碳化砂、鍺 化矽、碳化矽鍺中至少一種材料爲佳。 其次,本發明之特徵在於,先於半導體基板表面形成 厚度介於1〜20nm範圍的二氧化矽膜,接著將其暴露於 以電子衝擊所產生之電漿中,藉以改善二氧化矽膜之品質 。此時較佳爲,藉由於電子放出源、或是於柵形電極與半 導體基板間施加適當的電壓,以防止暴露於電漿中所生成 之絕緣膜發生充電現象。 於上述方法中,以電子衝擊產生電漿時所使用之氣體 較佳者係擇自下述A〜Η中至少一種。 A ·氮氣 B·—氧化二氮氣體 C·氧化氮氣體 D ·氨氣 E·上述氣體中二種以上之混合氣體 5 11 ^装--------訂------1·線·->. (請先閱讀背面之注咅?事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) B7 經濟部智慧財產局員工消費合作社印製 五、發明說明(φ) F ·上述氣體與氬、氖等鈍性氣體之混合氣體 G·上述氣體與乾燥氧之混合氣體 Η·上述氣體與含水蒸氣之氧的混合氣體 使用上述Α〜η的氣體之理由係其適於對例如矽表面 具二氧化砍膜之半導體進行氮化以改善薄膜特性。 又’於上述方法電漿處理中的熱處理溫度以〇°c〜7〇〇 °C的範圍爲佳。這是因爲藉由低溫氧氮化處理的進行可達 成本發明的目的。 又’於上述半導體及其絕緣膜的形成方法中,半導體 基板以擇自單結晶矽、多結晶矽、非晶形矽、砷化鎵、磷 化銦、碳化矽、鍺化矽、碳化矽鍺中至少—植材料爲佳, 這是因爲其作爲半導體基板之應用範圍很廣。 又’於上述方法,進行電漿處理之絕緣膜,以膜厚介 於1〜20nm範圍之二氧化矽膜爲佳。這是因如在上述的 範圍’最後獲得之絕緣膜之厚度可用於MIS電晶體、MIS 電容的極薄閘極絕緣膜及電容絕緣膜等方面。 依據本發明之半導體基板表面的絕緣膜之形成 方法’係於半導體基板上形成厚度介於丨〜2〇11111範圍之 絕緣膜’然後’將半導體基板溫度保持於70(TC以下之溫 度狀態的半導體基板上之絕緣膜暴露於以電子衝擊所生成 之電漿中’藉此’乃可有效率、合理地在半導體基板上形 成兼具高品質及高控制性之均一品質的絕緣膜。 於此時所形成之絕緣膜,在絕緣膜與半導體基板的界 面以及絕緣膜的最表面處,含有較高濃度氮原子,由於界 6 本紙張尺度適用中國國豕標準(CNS)A4規格(210 X 297公釐) ----1.--------裝------— —訂---------線(-· (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消费合作社印製 A7 ___B7_ 五、發明說明(() 面附近存在有氮原子,所獲得之物乃具有優異的界面特性 ,而可形成低界面態密度、高品質的絕緣膜。 再者,由於絕緣膜的表面附近存在有氮原子,故此時 所形成之絕緣膜具有優異之表面特性,並可緻密地形成可 防止硼等之不純物向內擴散之絕緣膜。 此時形成之絕緣膜的薄膜性質,首先,可依照在半導 體基板上最初形成絕緣膜所採用之形成方法加以改變,另 外,氧氮化速度、絕緣膜中之含氮量、於絕緣膜中之深度 方向的氮分佈,可依據進行熱處理時之溫度與時間、氣體 氣氛的種類、爲進行電子衝擊之熱電子源的溫度、以及爲 加速電子而於柵形電極與燈絲間所施加之電壓而變化。於 本發明的更佳條件下,於半導體基板上所形成之絕緣膜可 在0°C至範圍的溫度進行氮化。 [圖式之暴明〕 圖示本發明之第1實施例之使用半導體基板上_ 的絕緣膜良方法來形成MN CLSJt容之胜成過程截面_ 圖。 圖2爲表示本發明之第1實施例之進行晶圓的洗淨將 自然氧化膜去除後,在含水蒸氣之氧周圍氣氛中以850°C 加熱12分鐘後所測定之X射線光電子能譜》 圖3爲表示本發明之第1實施例之在矽基板上形成熱 氧化膜後,於以電子衝擊所生成之氮電漿中以_25°(:暴露1 小時後所測定之X線光電子能譜。 圖4爲表示本發明之第一實施例之在矽基板上形成熱 7 本及張尺度適用中國國家標準 1CNS)A4規袼⑵G X 297公餐> 一 ---Γ--------^裝--------訂---------線~ , (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消费合作社印製 A7 B7 五、發明說明(t) 氧r、化膜後所測定之同步加速紫外線光電子能譜。> '圖5爲表示本發明之第一實施例之在矽.基上形成熱 氧化膜後於以電子衝擊所生成之氮電漿中以25°C暴露1小 時後所測定之同步加速紫外線光電子能譜。 圖6爲表示本發明之第一實施例之在矽基板上形成熱 氧化膜後於以電子衝擊所生成之氮電漿中以25°C暴露1小 時後所測定之氮原子量/(氧原子與氮原子量之和―)的比値對 離開絕緣膜表面的距離所繪製之圖表。 ,圖7爲表示本發明之第一實施例之在矽基板上形成熱 氧化膜後於以電子衝擊所生成之氮電漿中以700°C暴露1小 時後所測定之X射線光電子能譜。 圖8爲表示本發明之第一實施例之在矽基板上形成熱 氧化膜後於以電子衝擊所生成之氮電漿中以700°C暴露1小 時後所測定之氮原子量/(氧原子與氮原子量之和)的比値對 離開絕緣膜之表面的距離所繪製之圖表。 圖9爲表示本發明之第一實施例之在矽基板上形成熱 氧化膜後於以電子衝擊所生成之氮電漿中以7〇〇°C暴露1小 時後所測定之氮原子量/(氧原子與氮原子量之和)的比値對 離開絕緣膜表面的距離所繪製之圖表。 圖10爲表示本發明之第二實施例絕緣膜的形成裝置 之槪略構成圖。 〔發明之較佳實施形態〕 以下,參照圖面同時詳細說明本發明之實施的形態。 圖1爲表示本發明之第一實施例之半導體基板上的絕 8 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱) ---Γ--------^ 衮--------- 訂---------線 A . (請先閱讀背面之注意事項再填寫本頁) A7 A7 經濟部智慧財產局員工消費合作社印製 ____Β7_ 五、發明說明(Ί) 緣膜之形成過程截面圖。本實施例取作爲半導體基板之矽 基板爲例,說明MN 0 S電容之形成過程。 (1) 首先,矽基板上以習知的選擇氧化技術,形成隔離 區域2與活性區域4。活性區域4的表面上存在自然氧化 膜8〔圖1 (a)〕°也就是說’作爲砂基板係使用P型 (100)、10〜15Ω c m之基板’作爲隔離區域2係形成膜 厚 500 nm 之區域氧化(LOCOS : local oxidation of silicon)氧化膜。 (2) 其次,爲洗淨活性區域4的表面,依眾知之R C A 洗淨(參照 W. Kevn,D. A. Plutien,RCA 回顧 31,187 頁’ 1970年)方法,將晶圓洗淨後,在稀H F溶液(0.5v ο 1 .% H F水溶液)浸漬5分鐘,去除矽基板表面的自然氧化 膜8〔圖1 ( b )〕。爲在矽基板表面上形成高品質之二 氧化矽膜,淸淨的矽表面3是必要的’因此矽基板表面之 自然氧化膜8的完全去除以及矽基板表面之不純物的去除 是重要的。 (3) 其次,用超純水將晶圓淸洗(洗淨)5分鐘後’在含 水蒸氣之氧周圍氣氛中以850°C進行氧化,以於矽基板1上 形成厚度8n m之二氧化矽膜5〔圖1 ( c )〕。作爲半導 體基板表面的絕緣膜之形成方法,除本實施例之熱氧化外 ,尙有將甲矽烷熱分解以於基板表面進行堆積之氣相成長 法、濺鍍法、電子束蒸鍍法、電阻加熱蒸鍍法、陽極氧化 法,將半導體浸漬於硝酸與過鹽酸等化學藥品中以化學地 形成二氧化矽膜之方法等。 9 紙張尺度適用中國國家標準(CNS>A4規格(210 X 297公釐) ---1丨.--------^裝--------訂------_!線{"- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明(ί) 上述之自然氧化膜8的完全去除,在之後將形成之二 氧化矽膜5的特性上扮演重要之角色,以符合形成淸淨且 均質之二氧化矽膜的要求。 (4) 其次,在1.5X10_2托的氮周圍氣氛中,將鎢絲加 熱至1400°C,在鎢絲與柵形電極之間施加53V之電壓,以 加速從鎢絲上放出熱電子使其衝撞氮分子來產生氮電漿, 將其暴露在二氧化矽膜5上以形成改良之絕緣膜6〔圖1 ( d )〕。此時,半導體基板係加熱至700°C或維持於室溫 下。又,針對柵形電極,乃在半導體基板上施加-10V之電 壓。這是因藉施加此電壓,將電漿中之相同數量的陽離子 與電子打入半導體試料中,於試料位置上之電流量將消失 ,故可防止因充電造成對絕緣膜之損害。 (5) 其次,爲形成電極,乃以濺鍍法將鋁膜7堆積1μ m〔圖1 (e)〕,接著以眾知微影技術將閘電極圖案化後 ,再以眾知的乾蝕刻技術將鋁膜蝕刻,形成閘電極9〔圖1 (f )〕。 圖2爲表示本發明之第1實施例之進行矽晶圓之洗淨 將自然氧化膜去除後,在含水蒸氣之氧周圍氣氛中以850 °C加熱12分鐘後所測定之X射線光電子能譜。 X線光電子能譜是用VG SCIENTIFIC社所製之 ESCALAB 220 i-XL測定。此時,使用能量1487 e V的鋁K α射線作爲X射線源。又,光電子是以表面垂直方向觀測 。波峰(1)是依據從二氧化矽膜的氧之1S軌道來的光電 子而成。於此試料並未存在來自氮1S軌域波峰,可知在 10 ---^1-------^ · 111---—til! — — — · I f ** (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 經濟部智慧財產局員工消费合作社印製 A7 B7__ 五、發明說明(^ ) 二氧化矽膜中並無氮原子。 圖3爲上述之二氧化矽膜在以電子衝擊所生成之氮電 漿中以25°C暴露1小時後所觀測到之X射線光電子能譜。 從此圖可明瞭’波峰(2)是依據由氮之is軌道來的 光電子。從波峰(2)和由氧的1S軌道來的光電子波峰( 1)之面積強度比,可計算出從表面到光電子的脫離深度3 n m之表面區域所含氮原子數/(氧原子數與氮原子數和)之 比値爲29%。此事可表示,藉由將二氧化矽膜暴露於因電 子衝擊所生成之氮電漿中,薄膜中將可含有氮原子,而使 二氧化矽膜改良。 圖4爲矽基板上形成之熱氧化膜的同步加速紫外線光 電子能譜。 此同步加速紫外線光電子能譜是用高能量物理學硏究 所,放射光實驗設施之射束B L - 3B所測定。此時,入射 光的能量爲65e V。因爲以吸收此入射光能量而放出之光 電子的脫離深度爲6〜7A,是以觀測係從表面至6〜7埃 之深度。能量基準爲費米能等級。波峰(2)是依據來自氧 2S軌道之光電子。 圖5爲在矽基板上形成熱氧化膜,其試料在以電子衝 擊而生成之氮電漿中以暴露1小時,之後所觀測到之 同步加速紫外線光電子能譜。 此時,入射光之能量爲65e V。此時可歸類波峰(2 )爲來自四氮化三矽的氮2S軌道之光電子,波峰(3)爲 來自四氮化三矽的氮2P軌道與矽3S軌道的混成軌道之光 11 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱1 (請先閲讀背面之注意事項再填寫本頁) 裝--------訂---------線f 經濟部智慧財產局員工消費合作社印製 B7_ 五、發明說明(
電子,波峰(4)爲來自四氮化三矽的氮2P軌道與矽3P 軌道的混成軌道之光電子,波峰(5)爲來自氮2P非結合 性軌道之光電子。〔例如參照(:.56!^1^11山厘.〇1^-
Khodja,A· Gheorghiu,S. Harel,G. Dufour,and H. Roulet 應用 物理學雜誌 U. Appl. Phys ) 74 卷(1993 年)5042 頁〕。 此顯示藉由將二氧化矽膜暴露在因電子衝擊所生成之 氮電漿中,表面將變化成四氮化三矽層,薄膜受到了改良 〇 圖6係就藉由將二氧化矽膜暴露於室溫下之以電子衝 擊所生成之氮電漿中而改良之絕緣膜,其氮原子量/(氧原 子與氮原子量之和)之比値對離開絕緣膜表面的距離所繪製 而成之圖表。 此圖表是以動能爲2K e V之氬離子將絕緣膜的表面 慢慢地蝕刻,之後藉由測定X射線光電子能譜而得。從此 圖表可得知,氮原子的量在絕緣膜之表面附近爲最多,其 次爲在絕緣膜與矽基板之界面。 界面附近上之氮原子的增加,並非因氬離子的打入所 造成之氮原子的導入現象,亦即不是藉撞出而成,因如爲 撞出而成則具有與氮原子相近質量數之氧原子也應該在界 面附近增加,但結果在界面附近氧原子的存在量卻減少了 〇 表面附近之氮原子有防止在雙閘C Μ 0 S裝置之P通 道電晶體之閘電極上所含的硼等之不純物侵入薄膜內部的 效果。 12 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) ---L—--------^裝--------訂---------線f 丨 (請先閲讀背面之注意事項再填寫本頁) A7 —___B7 _ 五、發明說明uh (請先閱讀背面之注意事項再填寫本頁) 又,此表面附近之氮原子係視爲終止氧化膜/上部電 極(就本實施例而言爲鋁,亦有爲多結晶矽等的情形)界 面附近之懸空鍵與彎曲鍵等,而有降低界面態、增加絕緣 擊穿電荷量、提昇絕緣擊穿耐壓性等效果。 另一方面,在氧化膜與矽基板的界面附近也觀察氮原 子的波峰。於MNO S構造中,氧化膜/矽基板界面在絕 緣擊穿特性、界面特性等電氣特性上扮演極重要之角色, 藉由以氮原子強固地終止界面附近之懸空鍵、不規則鍵、 彎曲鍵,不僅可降低界面態密度,亦可藉由施加電流應力 等防止界面附近之惡化。亦即,如依據本發明的絕緣膜之 形成方法,絕緣膜的特性可由表面及界面等兩面來改良, 進而可實現高性能之超薄絕緣膜。 圖7爲在矽基板上形成熱氧化膜,將該半導體試料在 以電子衝擊所生成之氮電漿中用700°C暴露1小時,而後觀 測到之X射線光電子能譜。波峰(2)爲來自氮的1S軌道 之光電子。 經濟部智慧財產局員工消费合作社印製 從波峰(2)與來自氧的1S軌道之光電子波峰(1) 之面積強度比,可計算出從表面到約3nm之表面區域上 所含氮原子數/(氧原子數與氮原子數之和)的比値爲11% » 從波峰(1)之結合能可得知1個氮原子上面結合著3個的 矽原子。 圖8爲在矽基板上形成熱氧化膜,將該半導體試料在 以電子衝擊所生成之氮電漿中用700°C暴露1小時,而後觀 測到之同步加速紫外線光電子能譜。 13 參&張尺度適用令國國家標準(CNS)A4規格(210 x297公釐) 經濟部智慧財產局員工消費合作社印製 A7 ____—_B7____ 五、發明說明(/1) 此處,可歸類波峰(1)爲來自氧2 s軌道之光電子’ 波峰(2)爲來自氮2 s軌道之光電子。結合能從〇e V至 15e V的區間之能譜的形狀,會因將二氧化矽膜暴露在氮 電漿上而發生若干變化,但並未觀測到因四氮化三矽產生 之波峰。又,從氮的含有量11%此較爲少量的結果可得知 在表面區域已形成氧氮化膜。 圖9爲關於在矽基板上形成熱氧化膜,將該半導體試 料在以電子衝擊所生成之氮電漿中用700°C暴露而改良之 薄膜,其氮原子、氧原子、矽原子的存在量對離開薄膜表 面之距離繪製而成之圖表。從此圖表可得知大量的氮原子 係於薄膜表面附近、薄膜與矽基板的界面上存在。 這些結果爲半導體基板之加熱溫度如果愈低,可在絕 緣膜的表面上含有愈高濃度的氮,此含有量可藉由加熱溫 度來控制。又,關於表面附近與界面附近之氮濃度,相較 於在室溫之電漿暴露表面濃度明顯高於界面,在700°C則 是界面的氮濃度比表面濃度高,此點亦無庸置疑的說明了 可控制薄膜中氮的分布。 其次,說明本發明之第2實施例。 圖10爲表示本發明之第2實施例所示之半導體基板 表面的絕緣膜之形成裝置的槪略構成圖。 如圖所示,藉由不銹鋼S U S 316構成之容積約 18000 cm3的橫向延伸之反應室101內,半導體基板1〇2 係以水平狀態被支持在撐桿101A上。 在反應室101的上部設有熱電子放出源(鎢絲)104、 14 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) ---- I I I------^裝! !| 訂·11!!·線(· (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局具工消費合作社印製 A7 B7 五、發明說明(/1]) 柵形電極105、網狀電極106,於鎢絲104之兩端可施加電 壓,又鎢絲104受到加熱將放出熱電子。在柵形電極105 上施加電壓將可加速自鎢絲104放出之熱電子。 在網狀電極106、半導體基板102上亦可施加電壓, 藉由調整施加在這些上面之電壓,可使射入絕緣膜表面之 電荷量歸零,進而防止絕緣膜之充電。又,在反應室101 之上部與下部,設有鹵素燈泡103,於鹵素燈泡103的部 分,係在反應室101上設有石英玻璃所製之窗。藉由鹵素 燈泡103可加熱半導體102。 於此絕緣膜之形成裝置中,係以從反應室的左端分別 設置氧氣導入管107、水蒸氣導入管108、氮氣導入管109 、一化二氮氣體導入管110、氧化氮氣體導入管111、氬氣 導入管112、氟化氫氣體導入管113的方式所構成。這些 氣體,在反應室101內之半導體基板102的表面反應後, 由反應室101之右端的排氣口排出。再者,實際裝置上備 有半導體基板搬送機構和控制部、電源部及溫度測量部等 ,於本實施例中,只表示實際上製程進行時反應室附近及 電壓施加部。 其次,用備有上述構成之絕緣膜的形成裝置,說明關 於絕緣膜形成情況。此時,作爲半導體基板,係使用表面 積314 c m 2之直徑200mm單結晶矽基板。 首先,將半導體基板(單結晶矽基板)102配置在既 定之位置後,爲去除半導體基板(單結晶矽基板)102表 面之自然氧化膜,乃在反應室101內導入約30秒之20c c 15 本紙張尺度適用令國國家標準(CNS)A4規格(210 X 297公釐) --j—-------^裝--------訂---------線f - (請先閱讀背面之注意事項再填寫本頁) A7 B7 五、發明說明((十) /分之流量的無水氟化氫氣體。 依此,可完全去除半導體基板(單結晶矽基板)102 表面的自然氧化膜,進而露出淸淨的矽表面。 其次,將氧氣以5000 c c/分之流量導入反應室101 的同時,藉由鹵素燈泡103將半導體基板(單結晶矽基板 )102之表面溫度達到1000°C般地加熱之。在此狀態加熱 到120秒時,半導體基板(單結晶矽基板)102的表面上 將形成膜厚8n m之二氧化矽膜。此時,若改爲導入氧或 同時導入水蒸氣以及氧,將可以更低溫度得到既定的膜厚 〇 其次,將反應室101排氣後,在其中導入氮氣,使反 應室101內之壓力成爲0.5托。此時氮氣之流量爲50c c /分。 其次,藉由在鎢絲104上流入電流以加熱至1300°C, 其次,相對鎢絲104在柵形電極105上施加23 V之電壓, 使氮分子藉由電子衝擊來產生氮電漿。 此時,相對柵形電極105在網狀電極106上施加-5V 電壓,於半導體基板102上施加-10V之電壓。又,藉由鹵 素燈泡103使半導體基板(單結晶矽基板)102之表面溫 度加熱至400°C。藉由暴露在氮電漿狀態下1小時,將二氧 化矽膜改良。 於本實施之形態中,亦可藉由調整半導體基板(單結 晶矽基板)102的加熱溫度、導入反應室101中氮氣的流 量、絕緣膜在電漿中暴露的時間、鎢絲104的溫度、施加 16 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) 裝--------訂----- 線(! 經濟部智慧財產局員工消費合作社印製 B7 B7 經濟部智慧財產局員工消费合作社印製 五、發明說明(/0 在柵形電極105上之電壓,可對存在於絕緣膜中之氮原子 含有量、絕緣膜中之氮原子在深度方向的分布簡單地進行 控制。 依以上所述,在半導體基板(單結晶矽基板)102的 表面上形成氧氮化膜後,可依照上述第1之實施例的圖1 所示之MN 0 S電容之製作流程來製作MN 0 S裝置。 再者,於本實施例之形態中,係以使用氮氣之情況舉 例說明,但只要係含有一氧化二氮氣體、氧化氮氣體、氨 氣等含氮原子之化合物氣體,即可達成所期待之目的。此 時,氣體中亦可混入氬氣及氖氣等氣體。 又,於本實施例之形態中,半導體基板之加熱溫度係 設定爲400°C,但溫度未必受限於此,只要半導體基板之 加熱溫度爲〇°C以上、700°C以下即可。 又,於本實施之形態中,係藉由鹵素燈泡使半導體基 板102之表面加熱,但構成未必受限於此,亦可用電阻加 熱方式。 又,於上述第1及第2實施例中,作爲半導體基板, 係以使用單結晶矽基板的情況舉例說明,但未必限定在單 結晶矽板上,亦可適用在多結晶矽、非晶形矽、砷化鎵、 磷化銦、鍺矽、碳化鍺矽、碳化矽等由其他半導體所構成 之基板上。 再者,本發明並不限定僅爲上述實施例,基於本發明 之宗旨之種種的變形亦可,這些並未排除在本發明的範圍 之外。 17 ---r---------^裝--------訂---------線f 丨 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用^國國家標<(CNS)A4規格(210><297公^| ) " A7 _B7_ 五、發明說明(丨k) 如以上詳細之說明般,根據本發明,藉由將絕緣膜暴 露在以電子衝擊所生成之電漿中,可以700°C以下之低溫 來進行絕緣膜之改良,藉由將這些絕緣膜作爲閘極絕緣膜 來使用,可實現高性能之Μ N 0 S裝置。 -------------^裝!----訂-----! — I 線(— (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)

Claims (1)

  1. 六、申請專利範圍 經濟部智慧財產局員工消費合作社印製 1 .一種半導體基板表面的絕緣膜之形成方法,其特 徵在於,係將形成於半導體基板表面之絕緣膜暴露於以電 子衝擊所產生之電漿中。 2 ·如申請專利範圍第1項之半導體基板表面的絕緣 膜之形成方法,其中,形成於上述半導體基板表面之絕緣 膜係膜厚介於1〜2〇n m範圍之二氧化砍。 3 ·如申請專利範圍第1項之半導體基板表面的絕緣 膜之形成方法,其中,上述所產生之電漿係藉由對含有氮、 原子之化合物、單體,亦即對氮分子、一氧化二氮(N 2 0 )、一氧化氮(NO)、氨等進行電子衝擊所產生之電漿 0 4 ·如申請專利範圍第丨項之半導體基板表面的絕緣 膜之形成方法,其中.,上述半導體基板係擇启單結晶砂一、 多結晶矽、非晶形矽、砷化鎵、磷化銦、碳化矽、鍺化矽 、碳化砂鍺·中至少一者之材料。 5 .如申請專利範圍第1項之半導體基板表面的絕緣 膜之形成方法,其中,形成於上述半導體基板之絕緣膜係 藉由熱氧化或化學氣相成長、化學氧化膜、電漿促使化學 氣相成長以及物理氣相成長等所成長者。 6 ·如申請專利範圍第1項之半導體基板表面的絕緣 膜之形成方法,其中,上述絕緣膜的表勝附近以及該絕緣 膜與上述半導體基板的界面附近有兩個氮濃度的波峰,且 波峰之氮濃度爲0.1原子%至60原子%。 7 · —種絕緣膜之形成裝置,係用以實現申請專利範 (請先閱讀背面之注$項再填寫本頁) -*·
    本紙張尺度逍用中國國家榡準(CNS ) A4規格(il〇X297公釐)
    六、申請專利範圍 經濟部智慧財產局員工消費合作社印製 1 .一種半導體基板表面的絕緣膜之形成方法,其特 徵在於,係將形成於半導體基板表面之絕緣膜暴露於以電 子衝擊所產生之電漿中。 2 ·如申請專利範圍第1項之半導體基板表面的絕緣 膜之形成方法,其中,形成於上述半導體基板表面之絕緣 膜係膜厚介於1〜2〇n m範圍之二氧化砍。 3 ·如申請專利範圍第1項之半導體基板表面的絕緣 膜之形成方法,其中,上述所產生之電漿係藉由對含有氮、 原子之化合物、單體,亦即對氮分子、一氧化二氮(N 2 0 )、一氧化氮(NO)、氨等進行電子衝擊所產生之電漿 0 4 ·如申請專利範圍第丨項之半導體基板表面的絕緣 膜之形成方法,其中.,上述半導體基板係擇启單結晶砂一、 多結晶矽、非晶形矽、砷化鎵、磷化銦、碳化矽、鍺化矽 、碳化砂鍺·中至少一者之材料。 5 .如申請專利範圍第1項之半導體基板表面的絕緣 膜之形成方法,其中,形成於上述半導體基板之絕緣膜係 藉由熱氧化或化學氣相成長、化學氧化膜、電漿促使化學 氣相成長以及物理氣相成長等所成長者。 6 ·如申請專利範圍第1項之半導體基板表面的絕緣 膜之形成方法,其中,上述絕緣膜的表勝附近以及該絕緣 膜與上述半導體基板的界面附近有兩個氮濃度的波峰,且 波峰之氮濃度爲0.1原子%至60原子%。 7 · —種絕緣膜之形成裝置,係用以實現申請專利範 (請先閱讀背面之注$項再填寫本頁) -*·
    本紙張尺度逍用中國國家榡準(CNS ) A4規格(il〇X297公釐) A8 B8 C8 D8 夂、申請專利範圍 圍第1項之半導體基板表面的絕緣膜之形成方法;該裝置 具有:用以產生電漿之可施加電壓之燈絲,位於該燈絲上 部之可施加電壓之柵形電極,以及位於燈絲極下部之可施 加電壓之網狀電極;該網狀電極、燈絲、柵形電極係位於 晶圓表面之上部,晶圓係具有得以藉由於反應室上下所配 置之虜素燈泡來加熱之構造,上述反應室爲一於上述鹵素 燈泡部份具有石英窗的金屬反應室’並具有可自該反應室 之一端導入氣體、再由另一端進行真空排氣之構造。 8 .如申請專利範圍第7項之絕緣膜之形成裝置,其 中,可自氣體導入口導入之氣體係無水H F、氧、水蒸氣 、N2〇、N〇、NH3、N2。 (請先聞讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 準 梂 家 A4 If 公 97 2
TW087109635A 1997-06-20 1998-06-17 The formation of semiconductor substrate surface insulation film and its related processes TW394970B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7045447B2 (en) 2002-03-26 2006-05-16 Hitachi Kokusai Electric Inc. Semiconductor device producing method and semiconductor device producing apparatus including forming an oxide layer and changing the impedance or potential to form an oxynitride

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020008844A1 (en) * 1999-10-26 2002-01-24 Copeland Victor L. Optically superior decentered over-the-counter sunglasses
US6450116B1 (en) * 1999-04-22 2002-09-17 Applied Materials, Inc. Apparatus for exposing a substrate to plasma radicals
EP2256808A2 (en) * 1999-04-30 2010-12-01 Semiconductor Energy Laboratory Co, Ltd. Semiconductor device and manufacturing method therof
JP2001223269A (ja) * 2000-02-10 2001-08-17 Nec Corp 半導体装置およびその製造方法
US6413881B1 (en) * 2000-03-09 2002-07-02 Lsi Logic Corporation Process for forming thin gate oxide with enhanced reliability by nitridation of upper surface of gate of oxide to form barrier of nitrogen atoms in upper surface region of gate oxide, and resulting product
US6939756B1 (en) * 2000-03-24 2005-09-06 Vanderbilt University Inclusion of nitrogen at the silicon dioxide-silicon carbide interace for passivation of interface defects
US6559007B1 (en) 2000-04-06 2003-05-06 Micron Technology, Inc. Method for forming flash memory device having a tunnel dielectric comprising nitrided oxide
US6686298B1 (en) * 2000-06-22 2004-02-03 Micron Technology, Inc. Methods of forming structures over semiconductor substrates, and methods of forming transistors associated with semiconductor substrates
US6833329B1 (en) * 2000-06-22 2004-12-21 Micron Technology, Inc. Methods of forming oxide regions over semiconductor substrates
US6660657B1 (en) 2000-08-07 2003-12-09 Micron Technology, Inc. Methods of incorporating nitrogen into silicon-oxide-containing layers
US6548368B1 (en) * 2000-08-23 2003-04-15 Applied Materials, Inc. Method of forming a MIS capacitor
US6544908B1 (en) * 2000-08-30 2003-04-08 Micron Technology, Inc. Ammonia gas passivation on nitride encapsulated devices
JP5068402B2 (ja) 2000-12-28 2012-11-07 公益財団法人国際科学振興財団 誘電体膜およびその形成方法、半導体装置、不揮発性半導体メモリ装置、および半導体装置の製造方法
JP4713752B2 (ja) * 2000-12-28 2011-06-29 財団法人国際科学振興財団 半導体装置およびその製造方法
US6838380B2 (en) * 2001-01-26 2005-01-04 Fei Company Fabrication of high resistivity structures using focused ion beams
JP2003069011A (ja) * 2001-08-27 2003-03-07 Hitachi Ltd 半導体装置とその製造方法
US6878585B2 (en) * 2001-08-29 2005-04-12 Micron Technology, Inc. Methods of forming capacitors
KR20030044394A (ko) * 2001-11-29 2003-06-09 주식회사 하이닉스반도체 듀얼 게이트절연막을 구비한 반도체소자의 제조 방법
US6723599B2 (en) * 2001-12-03 2004-04-20 Micron Technology, Inc. Methods of forming capacitors and methods of forming capacitor dielectric layers
US6706643B2 (en) * 2002-01-08 2004-03-16 Mattson Technology, Inc. UV-enhanced oxy-nitridation of semiconductor substrates
US20030134486A1 (en) * 2002-01-16 2003-07-17 Zhongze Wang Semiconductor-on-insulator comprising integrated circuitry
JP2003282872A (ja) * 2002-03-20 2003-10-03 Japan Science & Technology Corp プラズマ処理を含む基板材料及び半導体デバイスの製造方法
JP2004023008A (ja) * 2002-06-20 2004-01-22 Renesas Technology Corp 半導体集積回路装置およびその製造方法
US6780720B2 (en) * 2002-07-01 2004-08-24 International Business Machines Corporation Method for fabricating a nitrided silicon-oxide gate dielectric
JP4164324B2 (ja) * 2002-09-19 2008-10-15 スパンション エルエルシー 半導体装置の製造方法
JP4485754B2 (ja) * 2003-04-08 2010-06-23 パナソニック株式会社 半導体装置の製造方法
US7291568B2 (en) * 2003-08-26 2007-11-06 International Business Machines Corporation Method for fabricating a nitrided silicon-oxide gate dielectric
TWI311781B (en) 2004-02-16 2009-07-01 Sharp Kabushiki Kaish Thin film transistor and method for manufacturing same, display device, method for modifying oxidized film, method for forming oxidized film, semiconductor device and method for manufacturing same, and apparatus for manufacturing semiconductor device
JP4579637B2 (ja) * 2004-10-01 2010-11-10 東京エレクトロン株式会社 半導体記憶装置及びその製造方法
US7244659B2 (en) * 2005-03-10 2007-07-17 Micron Technology, Inc. Integrated circuits and methods of forming a field effect transistor
KR100811267B1 (ko) * 2005-12-22 2008-03-07 주식회사 하이닉스반도체 반도체소자의 듀얼게이트 형성방법
US7459403B1 (en) * 2006-05-01 2008-12-02 The United States Of America As Represented By The Secretary Of The Air Force Method for reducing device and circuit sensitivity to electrical stress and radiation induced aging
US7557002B2 (en) * 2006-08-18 2009-07-07 Micron Technology, Inc. Methods of forming transistor devices
US7989322B2 (en) * 2007-02-07 2011-08-02 Micron Technology, Inc. Methods of forming transistors
JP5343224B1 (ja) 2012-09-28 2013-11-13 Roca株式会社 半導体装置および結晶

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53123659A (en) * 1977-04-05 1978-10-28 Futaba Denshi Kogyo Kk Method of producing compound semiconductor wafer
US4135097A (en) * 1977-05-05 1979-01-16 International Business Machines Corporation Ion implantation apparatus for controlling the surface potential of a target surface
US4179312A (en) * 1977-12-08 1979-12-18 International Business Machines Corporation Formation of epitaxial layers doped with conductivity-determining impurities by ion deposition
US4351712A (en) * 1980-12-10 1982-09-28 International Business Machines Corporation Low energy ion beam oxidation process
US4509451A (en) * 1983-03-29 1985-04-09 Colromm, Inc. Electron beam induced chemical vapor deposition
US5180435A (en) * 1987-09-24 1993-01-19 Research Triangle Institute, Inc. Remote plasma enhanced CVD method and apparatus for growing an epitaxial semiconductor layer
US4870030A (en) * 1987-09-24 1989-09-26 Research Triangle Institute, Inc. Remote plasma enhanced CVD method for growing an epitaxial semiconductor layer
US4929986A (en) * 1987-09-25 1990-05-29 The United States Of America As Represented By The Secretary Of The Navy High power diamond traveling wave amplifier
JPH0262039A (ja) * 1988-08-29 1990-03-01 Hitachi Ltd 多層素子の微細加工方法およびその装置
JPH05190796A (ja) * 1991-07-30 1993-07-30 Internatl Business Mach Corp <Ibm> ダイナミック・ランダム・アクセス・メモリ・セル用誘電体皮膜およびその形成方法
US5334554A (en) * 1992-01-24 1994-08-02 Taiwan Semiconductor Manufacturing Co., Ltd. Nitrogen plasma treatment to prevent field device leakage in VLSI processing
JPH06128732A (ja) * 1992-10-15 1994-05-10 Ricoh Co Ltd 薄膜形成装置および薄膜形成方法
JPH0750295A (ja) * 1993-08-05 1995-02-21 Fujitsu Ltd 半導体装置の製造方法
JPH0817174B2 (ja) * 1993-11-10 1996-02-21 キヤノン販売株式会社 絶縁膜の改質方法
US5665640A (en) * 1994-06-03 1997-09-09 Sony Corporation Method for producing titanium-containing thin films by low temperature plasma-enhanced chemical vapor deposition using a rotating susceptor reactor
JP3348263B2 (ja) * 1995-02-08 2002-11-20 富士通株式会社 半導体装置の製造方法
US5672521A (en) * 1995-11-21 1997-09-30 Advanced Micro Devices, Inc. Method of forming multiple gate oxide thicknesses on a wafer substrate
JPH1064477A (ja) * 1996-08-20 1998-03-06 Nissin Electric Co Ltd イオン照射装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7045447B2 (en) 2002-03-26 2006-05-16 Hitachi Kokusai Electric Inc. Semiconductor device producing method and semiconductor device producing apparatus including forming an oxide layer and changing the impedance or potential to form an oxynitride

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EP0886308A2 (en) 1998-12-23
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US6265327B1 (en) 2001-07-24
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