TW387135B - Semiconductor lead frame - Google Patents

Semiconductor lead frame Download PDF

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Publication number
TW387135B
TW387135B TW086100256A TW86100256A TW387135B TW 387135 B TW387135 B TW 387135B TW 086100256 A TW086100256 A TW 086100256A TW 86100256 A TW86100256 A TW 86100256A TW 387135 B TW387135 B TW 387135B
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Taiwan
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layer
alloy
lead frame
thickness
semiconductor lead
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TW086100256A
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English (en)
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Joong-Do Kim
Young-Ho Baek
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Samsung Aerospace Ind
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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C28/00—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
    • C23C28/02—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D only coatings only including layers of metallic material
    • C23C28/021—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D only coatings only including layers of metallic material including at least one metal alloy layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C28/00—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
    • C23C28/02—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D only coatings only including layers of metallic material
    • C23C28/023—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D only coatings only including layers of metallic material only coatings of metal elements only
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/10—Electroplating with more than one layer of the same or of different metals
    • C25D5/12—Electroplating with more than one layer of the same or of different metals at least one layer being of nickel or chromium
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/60—Electroplating characterised by the structure or texture of the layers
    • C25D5/623—Porosity of the layers
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
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    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48663—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/48664—Palladium (Pd) as principal constituent
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L2924/15747—Copper [Cu] as principal constituent

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  • Lead Frames For Integrated Circuits (AREA)
  • Electroplating Methods And Accessories (AREA)
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Description

A7 _ B7__ 五、發明説明（1 ) <發明之範圍〉 本發明是有關一種半導體引線支架，特別是有關一種 半導體引線支架，是種半導體弓丨線支架，依照一具有一増 進構造之電鍍層（Plated layer)，乃具有ί曽進的導線結合 (wire bonding)與沖模附著（die attachment)特性者。 <發明之货景〉 半導體引線支架係構成一半導體包裝之核心、元件（core eleiaerrb)之一，其乃作為一連接半導體包裝之內側與外側 之弓丨線从及支持半導體晶片之框架。半導體引線支架通常 '· 係利用一沖歷方法Μ冲頭沖壓而模塑薄板材料，以及，一 蝕刻方法使用化學物質來蝕刻材料的固定部份。 以上述之方法所製造的半導體引線支架乃依照加諸於 一基板之方法而有結構上的改變，而且，其通常包括一墊 片（pad)ll,其上嵌設一半導體晶片（未示），一内導腳12 乃利用導線接合而連接至晶Η，而夕卜導腳13則連接至一外 電路。 具有上述構造的半導體引線框架利用與例如一晶Η等 的其他部份組合而構成半導體包装，在半導體包裝中，沖 模墊片部份11與引線框架之内導腳12通常係利用一具有預 定特性之金屬電鍍Μ増進在製造過程中晶片與引線框架的 內導腳12之間的導線接合，Μ及晶片對沖模墊片部份的沖 模附著者。而且，外導腳係鍍上Sn-Pb以、在一樹脂保護膜 模塑程序後增進加至於基板上的焊接能力。 必#注意的是，在上述Sn-Pb電鍍程序中，電鍍溶疲經 —3 — 本紙張尺度適用中國國家標準（CNS ) ( 210X297公釐） A7 B7_ 五、發明説明（2 ) 常穿透至內導腳12之中，如此，即需要一用來除去溶液的 程序。有一個叫做'預電鏡框杂法ΊίΙ道是可來解決此問— 題，在此方法中，一中間電鍍磨係利用在半導體包裝接序 Μ前被擾具有良好的焊接可沾性（solar wettability)材 料來形成。 Μ預電鍍框架法形成之電鍍層構造係表示於第2圖中 ，請參考第2圖，多數電鍍層23係系_著分別於一Cu基板21 上沈積一 N i層22與一Pb/N i合金層23,作為中間電雛層，且 沈積一Pb廇於Pb/Ni合金層23上。 Μ 在上述具有多數個電鍍層的構造，Ni層22防止基板21 的Cu原子藉著擴散到最夕卜表面而產生銅反應物（copper reactants)，例如氧化物或硫化物。 在則層22的厚度少於4〇0^英寸（大約10.2//111)的情 況時，在Ni層22中產生多重性的孔隙、率，Cu原子即通過多 重孔隙擴散。相反地，在Ni層22的厚度大於400 μ英寸時， 當引線框架彎折時即會產生破裂。 如上述，已知道有一方法用來防止Cu原子在Ni層22的 厚度少於400以英寸時從孔隙擴散。Μ此方法形成之電鍍 層的構造乃如第3圖所示。請參看第3圖，此多數電鍍層 的構造係藉著於Cu基板31上沈積一大約5 w英寸厚之Ni放 電層32，大約英寸之Pd/hTi合金層33與一Ni層34作為中 間電鍍層，以及一Pd層35沈積於Ni層34上。. 然而，甚至於在上述構造中，在很多情況，例如氧化 物或硫化物的銅反廳物乃產生在引線支架的最外表面，此 -4- 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0 X 297公釐） « m n m -- 0 · (請先閲讀背面之注意事項再填寫本頁) I n . m '-ITn n 經濟部中央橾準局員工消費合作衽印製 级濟部中央標準局員工消費合作社印製 A7 £7___ 五、發明説明（3 ) 會引起很多的問題，例如表面色著的改變與焊接能力的劣 化。 用來克服上述電鍵層構造之問題的方法已為人所知道 ，以此方法所形成之電鍍層構造乃示方》第4圖中》請參看 該第4—，此多數個電鍍層構造係藉著於一Cu基板41沈積 —Ni 層42 , —Au.放電層43.，一"Pd/m合金膚44與一*Pd層45' 作為中間電鑛層，且Pd層45上沈積一Αιι層46。在上述的鐘 • · ‘ 鍍層構造中，Au放電膚43作為一Ni層42與Pd/Ni合金層44 之間的β付著層，Pd層45作為從Pd/Mi合金層44來的Ni源子 的收集科，Au在夕卜面的電鍍層貝U用來減少孔隙率且ί曾進焊 接性與導線接合特性。辩而，由於Au層46的原故，此種穷 法有成本上的缺點。 在依照上述之傳統技術的電鍍層構造中，有一另外的 問題*亦即，中間層與外層的結合很弱。由於上逑結合力 微弱的原因，中間層與外層的結合部份在將導腳彎折峙即 .· 成為破裂起始部份，如此很容易形成破裂而部份的腐触在 一些情況下會加快，因此使得整個電鍍層勞化。 ‘ 〈發明之總論〉 本發明之目的乃在提供一種半導體引線支架，其具有 增進的導線結合特性_腐触忍耐性。 為了達成上述之目的，本發明提供了一種半導體引線 支架，依照本發明，其具有一多數電鍍層構造，包括一形 成一半導體引線支架之金屬基板，一形成在基板上之Ni合 金«鑛層，一*形成在Ni合金電鍍層上的Pd放竃電鑛層，與 -5 - 本紙锒尺度適用中國國家標準（CNS ) A4規格（2丨〇乂297公釐） (請先閲讀背面之注意事項再填寫本頁) .續- A7 B7 經濟部中央樣準局員工消費合作社印製 五、發明説明（4 ) —形成在Pd放電電鍍層上之Pd-X合金電鍍層。 在依照本發明之半導體引線支架中*基板較佳的是以 Cu、Cu合金、合金之一所形成，其較佳的形成厚度為 0.1至3.0mm 〇 Pd-X合金層較佳的是MPd作為主要成份Μ及 Au、Co、W、As、Ti、Mo與Sn之一者而形成 〇
Pd-X合金層的形成厚虔較佳的是0.1至。則合 金電鍍層較佳的是形成有一0.1至2.0« m β勺厚度者。Pd放 電電鍍餍所形成之厚度則為0.005至0.05以m 〇 〈圖示之簡單說明> 上述之本發明的目的與優點，參照下列依附圖所作之 說明將會更為了解，附圖者。 第1圖為表示一平常的半導體引線支架的平面圖。 第2圖至第4圖表示應用於一傳統半導體引線框架之 電鍍層構造的不同實施例的縱截面圖；Μ及 第5圖係表示侬照本發明之半導體引線框架之電鍍層 構造的截面圖。 〈本發明之詳細描述> 以下參照附圖詳細敘述依照本發明之具有多數個薄片 層的半導體引線支架的較佳具體實施例。 請參看第5圖，依照本發明之半導體引線支架之電鍛 層具有多數電鎞層之構造，其中一Ni合金電鍍層52 *與一 Pd放電電鍍曆53B作為形成半導體引線支架的金屬基板51的 中間電艘層，而一Pd-X合金電鍍層54則又沈積於Pd放電電 鍍層53。 —0 — 本紙張尺度適用中國國家標準（CNS ) A4規格{_ 210X297公釐） —.— — II ------dw% -I - . (請先閲讀背面之注意事項再填寫本頁) -、tT' 經濟部中央榇準局員工消費合作社印製 A7 __—_B7 ___ 五、發明説明（5 ) _ 在上述的電鍍層構造中，基板51係MCu、Cu合金、與，
Ni合金的一種材料所形成，其較佳的厚度為0.1至3.0臓， . ·
Ni合金電鍵層52較佳的係具有一0.1至2.0以m的厚度，作 為上中間層之Pd放電電鍍53隱藏了作為中間層之N i合金電 , · · · . 鍍層52的表面之孔隙率，旦減少了表面的粗糙*結果，均 旬厚度之Pd-X合金電#度層54乃電子沈積（ele0tr〇-.deposi tecJ )在Pd放電電鑛層53上面。因此，在一鹽分大氣中所發生 的典型釋蝕現象可被相當地減低。Pd放簞電趟層53也增強 了 Hi合金電鍍層52與Pd-X合金電鍍層54的結合力乂肚i 一结 合力的增強可使得在將一半導體晶片放置在第1圖之引線 支架11的墊片部份後，使得在微調與成型中破損的產生可 ‘ 降為最低，因此增強腐蝕的忍受性且防止基板51的矩陣合 金元件（例如鋼）與Ni合金電鑛層52的Ni&tl擴散。結果， 焊接能力即可增進。 同時，Pd-X合金^鍍層54較佳的是Μ包括Pd為主要成 分與例如Au、Co、W、As、Ti、Mo與Sn的一種元件構成的 合金所形成。Pd-X合金電織曆54較佳地具有一0.1至2.0 M m 的厚度。適當的厚度範圍可依照X的量作些許改變，X則為 一合金組成元素。例如，電鍍層54的厚度較佳的是隨著X, 合金組成元素的增加而變薄。在本發明中，Pd-Au合金彳％ 使用作為外電鍍層54，其是用來增進一Au線與存在於夕卜廇 54之Au成份間的接合力量*且由為Pd-Au合金比較純Pd具 有馕異腐触忍受特性，可增強腐蝕忍受性。此係因為，在 Pd-Au合金的情況，擴散至夕卜電鑛層54中之氫的量，係決定 丁： 本紙浪尺度適用中國國家標準（CNS ) A4規格（210X297公釐)~— ~~~~ (請先閲讀背面之注意事項再填寫本頁) .'嚷 訂 Α7 Β7 五、發明説明(β) 被覆於以Cu形成之導線支架上的外電鍍層540tl腐蝕的重要 因素，而其係少於其在純Pd中的量。 本.發明將參照一較佳實施例與比較例來說明於下^ 實施例： . ' . · . 在01^-194的情況中，其係為山会歐林金屬（¥日腿^13- 01 in Meta 1)的二個產品，一般的油脂去除與活化程序係施 加於MCu所形成之引線支架的表面，N i合#電鍍層52與Pd .· 放電電鍍層53係順序地形成，而Bd-Au合金電鍍層54乃被形 成，Μ使得具有一厚度為大約0.5的外導腳部份被形成 。在此時，'使用.了漢陽化學工業公司（Hanyang Chemi.Cal Industries Co.，Ltd)可製造的Pd-Au合金，Pd-25重量％ Au電鍵溶液，電鍍層乃藉由施加每兩個極板的電流為1.0A 而形成。 比較例1
I 經濟部中央標準局員工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 鎳電鍍層係利用每兩個極板施加1.0A的電流，而使用 N i—氨基確酸鹽溶液（N i -suIfamate solut ion),形成於Μ 上述實施例之相同材料所形成的引線支架的表面上。Pd— 電鑛層係直接形成在表面上而未形成Pd放電電鍍層。 比較例2 鏡電鍍層係利每兩個極板胞加1.0A的電流，而使用Ni —(M i —su 1 faraate so 1 ut ion) , 述實施例之相同材料所形成的引線支架的表面上，Pd-Au · 電鑛層係直接形成於表面上，而未形成Pd放電電鍍層。 葑於實施例的電鍍層的構造而言，fcb較實例1，Μ及 -δ - 本紙依尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） 3B71S5 at B7 五、發明説明（7 ) fcb較實例2，一焊接性能試驗；MIL-STD-883D，方法 2003·7 (焊接性能）"，一鹽噴霧試驗；、' MIL-STD-883D ，方法1009.8鹽大氣遞（腐蝕），、、與一導線接合試驗係 Μ美國軍用標準檢測，試驗的結果係顯示於下列表中。 附 表 分 類 實施例 比較例1 fcb較例2 焊接性能 通過 失敗 失敗 接合力 12.01gf 4.61sf 8.40sf 腐蝕忍耐性 通過 失敗 失敗 參考上列的表，可Μ注意到焊接性能、導線接合力、 腐触忍陋性試驗的結果，Pd放電電鍍層53形成於Ni—放電 層52與Pd-Au放電層54之本發明的引線支架係優於比較例1 與2的引線框架。 經濟部中央標準局員工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 在侬頤本發明之具有多數電鍍曆，而其中Pd放電電鑛 層形成於N i電鍍層與Pd-X合金電鍍層之間的引線支架中， Pd放電電鍍層覆蓋了 Ni電鍍層的多孔隙率表面，並減少表 面的粗键度〇由於外Pd-X合金電鍍層可由於Pd放電電鐽詹 而維持均匀，腐触忍受性與結合力即可增加，如此破損的 產生與進程即可變為最小。因此，可藉由婿進引線支架的 導線接合特性與焊接性能促進半體包裝程序的產能。 .· - 9 - 本紙張尺度適用中國國家標準（CNS ) Α4ί?^· ( 210X297公釐）

Claims (1)

  1. A8 B8 C8 D8 3871S5 六、申請專利範圍 1. —種半導體引線支架，包括： —形5成一半導體引線支架之金屬基板； (請先閱讀背面之注意事項再填寫本頁) —形成在基板上之Ni合金電鍍層； —形成在Ni合金電鑛層上的Pd放電電鍍層；Μ及 —形成在Pd放電電鑛層上的Pd-X合金電鐽層者 2. 如申請專利範崮第1項之半導體引線支架，其中所述基 板係MCu、Cu合金與Ni合金之一所形成者。 3. 如申請專利範圍第1項之半導體引線支架，其中所述基 板戸万形成之厚度為0.1至3.0誦者。 4·如申請專利範園第2項之半導輝引線支架，其中所述基 板所形成之厚度為〇. 1至3.0酬者。 5.如申請專利範圍第;l項之半導體引線支架，其中所述阳 -X合金電鍍層係以Pd作為一主要成分以及Au、Co、W、Ag 、.Ti、Mo與sn之所形成的。 6·如申請專利範圍第：l項之半導體引線支架，其中所述阳 -X合金電總層係形成為有一〇. ：L至2.〇 “威勺厚度者。 7. 如申請專利範園第4項之半導體引線支架，其中所逑时 -X合金電鍵層係形成為有一〇 ·：[至2. 〇 w &的厚度者。 經濟部中央標準局員工消費合作社製 8. 如申請專利範圍第1項之半導體引線支絮，其中所述Ni 合金電鍵層係柩成為有一0. i至2 · 〇 ^ ^的厚度者·：， 9. 如申請專利範園第1項之半導體引線支架，其中所述pd 放電電§度層係形成為有一0.005至〇. 5 w m的厚度者。 -10 -
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KR970067815A (ko) 1997-10-13
US5767574A (en) 1998-06-16

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