TW372354B - CMOS structure with FETS having isolated wells with merged depletions and methods of making same - Google Patents

CMOS structure with FETS having isolated wells with merged depletions and methods of making same

Info

Publication number
TW372354B
TW372354B TW085115275A TW85115275A TW372354B TW 372354 B TW372354 B TW 372354B TW 085115275 A TW085115275 A TW 085115275A TW 85115275 A TW85115275 A TW 85115275A TW 372354 B TW372354 B TW 372354B
Authority
TW
Taiwan
Prior art keywords
well
depletions
fets
merged
methods
Prior art date
Application number
TW085115275A
Other languages
English (en)
Inventor
Seshadri Subbanna
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of TW372354B publication Critical patent/TW372354B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7394—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
TW085115275A 1996-05-22 1996-12-10 CMOS structure with FETS having isolated wells with merged depletions and methods of making same TW372354B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/651,353 US5731619A (en) 1996-05-22 1996-05-22 CMOS structure with FETS having isolated wells with merged depletions and methods of making same

Publications (1)

Publication Number Publication Date
TW372354B true TW372354B (en) 1999-10-21

Family

ID=24612558

Family Applications (1)

Application Number Title Priority Date Filing Date
TW085115275A TW372354B (en) 1996-05-22 1996-12-10 CMOS structure with FETS having isolated wells with merged depletions and methods of making same

Country Status (6)

Country Link
US (2) US5731619A (zh)
EP (1) EP0809302B1 (zh)
JP (1) JP3101585B2 (zh)
KR (1) KR100243715B1 (zh)
DE (1) DE69706601D1 (zh)
TW (1) TW372354B (zh)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5882982A (en) * 1997-01-16 1999-03-16 Vlsi Technology, Inc. Trench isolation method
US5926723A (en) * 1997-03-04 1999-07-20 Advanced Micro Devices, Inc. Generation of a loose planarization mask having relaxed boundary conditions for use in shallow trench isolation processes
JP3497059B2 (ja) * 1997-04-25 2004-02-16 株式会社リコー 半導体装置の製造方法
KR100296130B1 (ko) * 1998-06-29 2001-08-07 박종섭 이중막 실리콘웨이퍼를 이용한 금속-산화막-반도체 전계효과트랜지스터 제조방법
US6589834B1 (en) * 1998-10-06 2003-07-08 Alliance Semiconductor Corporation Semiconductor chip that isolates DRAM cells from the peripheral circuitry and reduces the cell leakage current
US6353246B1 (en) 1998-11-23 2002-03-05 International Business Machines Corporation Semiconductor device including dislocation in merged SOI/DRAM chips
US6091657A (en) * 1999-01-20 2000-07-18 Lucent Technologies Inc. Integrated circuit having protection of low voltage devices
US6372607B1 (en) * 1999-06-30 2002-04-16 Intel Corporation Photodiode structure
US6372639B1 (en) 1999-08-31 2002-04-16 Micron Technology, Inc. Method for constructing interconnects for sub-micron semiconductor devices and the resulting semiconductor devices
US6440805B1 (en) * 2000-02-29 2002-08-27 Mototrola, Inc. Method of forming a semiconductor device with isolation and well regions
US6433372B1 (en) 2000-03-17 2002-08-13 International Business Machines Corporation Dense multi-gated device design
US6537891B1 (en) * 2000-08-29 2003-03-25 Micron Technology, Inc. Silicon on insulator DRAM process utilizing both fully and partially depleted devices
US6486043B1 (en) 2000-08-31 2002-11-26 International Business Machines Corporation Method of forming dislocation filter in merged SOI and non-SOI chips
US6472715B1 (en) * 2000-09-28 2002-10-29 Lsi Logic Corporation Reduced soft error rate (SER) construction for integrated circuit structures
US6426547B1 (en) 2000-12-12 2002-07-30 Information Business Machines Corporation Lateral polysilicon pin diode and method for so fabricating
US6664141B1 (en) 2001-08-10 2003-12-16 Lsi Logic Corporation Method of forming metal fuses in CMOS processes with copper interconnect
JP4173658B2 (ja) * 2001-11-26 2008-10-29 株式会社ルネサステクノロジ 半導体装置及びその製造方法
US6927460B1 (en) 2002-02-15 2005-08-09 Fairchild Semiconductor Corporation Method and structure for BiCMOS isolated NMOS transistor
US6686624B2 (en) 2002-03-11 2004-02-03 Monolithic System Technology, Inc. Vertical one-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region
US6661042B2 (en) * 2002-03-11 2003-12-09 Monolithic System Technology, Inc. One-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region
JP3581354B2 (ja) * 2002-03-27 2004-10-27 株式会社東芝 電界効果トランジスタ
JP2003309182A (ja) * 2002-04-17 2003-10-31 Hitachi Ltd 半導体装置の製造方法及び半導体装置
US6808994B1 (en) * 2003-06-17 2004-10-26 Micron Technology, Inc. Transistor structures and processes for forming same
KR101060426B1 (ko) * 2003-12-12 2011-08-29 엔엑스피 비 브이 바이폴라 디바이스 내에 에피택셜 베이스층을 형성하는 방법 및 구조체
US7271453B2 (en) * 2004-09-20 2007-09-18 International Business Machines Corporation Buried biasing wells in FETS
US7071047B1 (en) * 2005-01-28 2006-07-04 International Business Machines Corporation Method of forming buried isolation regions in semiconductor substrates and semiconductor devices with buried isolation regions
US7435638B2 (en) * 2006-05-26 2008-10-14 Texas Instruments Incorporated Dual poly deposition and through gate oxide implants
US7598575B1 (en) * 2007-09-12 2009-10-06 National Semiconductor Corporation Semiconductor die with reduced RF attenuation
CN101572263B (zh) * 2008-04-30 2012-01-18 中芯国际集成电路制造(北京)有限公司 互补金属氧化物半导体器件及其制作方法
US8609483B2 (en) * 2009-06-26 2013-12-17 Texas Instruments Incorporated Method of building compensated isolated P-well devices
US9059291B2 (en) 2013-09-11 2015-06-16 International Business Machines Corporation Semiconductor-on-insulator device including stand-alone well implant to provide junction butting
US20150200295A1 (en) * 2014-01-10 2015-07-16 Cypress Semiconductor Corporation Drain Extended MOS Transistors With Split Channel
US20160118353A1 (en) * 2014-10-22 2016-04-28 Infineon Techologies Ag Systems and Methods Using an RF Circuit on Isolating Material

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5374840A (en) * 1989-04-25 1994-12-20 Matsushita Electronics Corporation Semiconductor device with isolated transistors
US4170501A (en) * 1978-02-15 1979-10-09 Rca Corporation Method of making a semiconductor integrated circuit device utilizing simultaneous outdiffusion and autodoping during epitaxial deposition
JPS54136281A (en) * 1978-04-14 1979-10-23 Toko Inc Semiconductor device and method of fabricating same
US4291327A (en) * 1978-08-28 1981-09-22 Bell Telephone Laboratories, Incorporated MOS Devices
US4416050A (en) * 1981-09-24 1983-11-22 Rockwell International Corporation Method of fabrication of dielectrically isolated CMOS devices
US4599789A (en) * 1984-06-15 1986-07-15 Harris Corporation Process of making twin well VLSI CMOS
US4764480A (en) * 1985-04-01 1988-08-16 National Semiconductor Corporation Process for making high performance CMOS and bipolar integrated devices on one substrate with reduced cell size
EP0794575A3 (en) * 1987-10-08 1998-04-01 Matsushita Electric Industrial Co., Ltd. Structure and method of manufacture for CMOS semiconductor device against latch-up effect
JPH0797627B2 (ja) * 1987-12-21 1995-10-18 株式会社日立製作所 半導体装置
JP2845493B2 (ja) * 1988-06-24 1999-01-13 株式会社東芝 半導体装置
US5015594A (en) * 1988-10-24 1991-05-14 International Business Machines Corporation Process of making BiCMOS devices having closely spaced device regions
US5422299A (en) * 1989-09-11 1995-06-06 Purdue Research Foundation Method of forming single crystalline electrical isolated wells
US5138420A (en) * 1989-11-24 1992-08-11 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having first and second type field effect transistors separated by a barrier
EP0435541A3 (en) * 1989-12-26 1991-07-31 Motorola Inc. Semiconductor device having internal current limit overvoltage protection
JPH04291952A (ja) * 1991-03-20 1992-10-16 Sony Corp 半導体装置
JP3100663B2 (ja) * 1991-05-24 2000-10-16 株式会社東芝 半導体装置及びその製造方法
JPH04359567A (ja) * 1991-06-06 1992-12-11 Toshiba Corp 半導体装置およびその製造方法
TW260816B (zh) * 1991-12-16 1995-10-21 Philips Nv
JPH05183159A (ja) * 1992-01-07 1993-07-23 Fujitsu Ltd 半導体装置及びその製造方法
US5250829A (en) * 1992-01-09 1993-10-05 International Business Machines Corporation Double well substrate plate trench DRAM cell array
JPH07112049B2 (ja) * 1992-01-09 1995-11-29 インターナショナル・ビジネス・マシーンズ・コーポレイション ダイナミック・ランダム・アクセス・メモリ・デバイスおよび製造方法
JP2736493B2 (ja) * 1992-04-03 1998-04-02 三菱電機株式会社 半導体装置およびその製造方法
KR0139773B1 (ko) * 1992-08-11 1998-06-01 사또오 후미오 반도체 집적 회로 장치 및 그 제조 방법
US5268588A (en) * 1992-09-30 1993-12-07 Texas Instruments Incorporated Semiconductor structure for electrostatic discharge protection
US5268312A (en) * 1992-10-22 1993-12-07 Motorola, Inc. Method of forming isolated wells in the fabrication of BiCMOS devices
KR950021600A (ko) * 1993-12-09 1995-07-26 가나이 쯔또무 반도체 집적회로장치 및 그 제조방법
JPH07335837A (ja) * 1994-06-03 1995-12-22 Hitachi Ltd 半導体装置および論理回路
US5698458A (en) * 1994-09-30 1997-12-16 United Microelectronics Corporation Multiple well device and process of manufacture
US5541132A (en) * 1995-03-21 1996-07-30 Motorola, Inc. Insulated gate semiconductor device and method of manufacture
JP2734436B2 (ja) * 1995-12-26 1998-03-30 日本電気株式会社 Ｍｏｓ型半導体装置

Also Published As

Publication number Publication date
JPH1050863A (ja) 1998-02-20
EP0809302B1 (en) 2001-09-12
KR100243715B1 (ko) 2000-02-01
JP3101585B2 (ja) 2000-10-23
US5789286A (en) 1998-08-04
DE69706601D1 (de) 2001-10-18
KR970077537A (ko) 1997-12-12
US5731619A (en) 1998-03-24
EP0809302A3 (en) 1998-12-30
EP0809302A2 (en) 1997-11-26

Similar Documents

Publication Publication Date Title
TW372354B (en) CMOS structure with FETS having isolated wells with merged depletions and methods of making same
US6249027B1 (en) Partially depleted SOI device having a dedicated single body bias means
US5091332A (en) Semiconductor field oxidation process
EP0319047A3 (en) Power integrated circuit
TW335513B (en) Semiconductor component for high voltage
EP1071132A3 (en) Method for reducing substrate capacitive coupling of a thin film inductor by reverse P/N junctions
EP1033760A3 (en) High withstand voltage MOS transistor and method of producing the same
WO2001043197A3 (en) Source/drain-on-insulator (s/doi) field effect transistors and method of fabrication
EP0877425A3 (en) Field effect device with polycrystalline silicon channel
TW347565B (en) A complementary bipolar transistors and a fabrication method thereof
US20170154957A1 (en) Compact cmos device isolation
US6525394B1 (en) Substrate isolation for analog/digital IC chips
EP1024537A3 (en) Insulated gate field effect transistor having a buried region and method of making the same
EP0827206A3 (en) Semiconductor device with circuit for preventing latch-up
TW360981B (en) Semiconductor integrated circuit device
Watanabe et al. High speed BiCMOS VLSI technology with buried twin well structure
EP0424926A2 (en) Bi-CMOS integrated circuit
US5168341A (en) Bipolar-cmos integrated circuit having a structure suitable for high integration
TW373338B (en) A semiconductor device having an SOI structure and a method for manufacturing the same
EP0387836A3 (en) Semiconductor device for use in a hybrid lsi circuit
KR970704244A (ko) 절연체 상 실리콘(soi) 기판에 형성된 cmos 인터페이스 회로
JPH0291967A (ja) Ｂｉ−ｃｍｏｓ半導体装置
JP2666749B2 (ja) 半導体装置
JPH10335658A (ja) Ｍｏｓｆｅｔ
KR920020722A (ko) 투윈 웰 씨모스의 래치-업 방지구조