TW363185B - Random-access memory - Google Patents

Random-access memory

Info

Publication number
TW363185B
TW363185B TW086115692A TW86115692A TW363185B TW 363185 B TW363185 B TW 363185B TW 086115692 A TW086115692 A TW 086115692A TW 86115692 A TW86115692 A TW 86115692A TW 363185 B TW363185 B TW 363185B
Authority
TW
Taiwan
Prior art keywords
wiring
psa
applying
ldb0
nsa
Prior art date
Application number
TW086115692A
Other languages
English (en)
Inventor
Atsushi Hatakeyama
Shusaku Yamaguchi
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of TW363185B publication Critical patent/TW363185B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
TW086115692A 1996-12-27 1997-10-23 Random-access memory TW363185B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP35127696A JP3277192B2 (ja) 1996-12-27 1996-12-27 半導体装置

Publications (1)

Publication Number Publication Date
TW363185B true TW363185B (en) 1999-07-01

Family

ID=18416223

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086115692A TW363185B (en) 1996-12-27 1997-10-23 Random-access memory

Country Status (4)

Country Link
US (1) US5828613A (zh)
JP (1) JP3277192B2 (zh)
KR (1) KR100311269B1 (zh)
TW (1) TW363185B (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2217375C (en) * 1997-09-30 2001-09-11 Valerie Lines Bi-directional data bus scheme with optimized read and write characteristics
US6052323A (en) * 1998-07-22 2000-04-18 Texas Instruments Incorporated Memory circuit including reduced area sense amplifier circuitry
KR100333728B1 (ko) 1999-06-30 2002-04-25 박종섭 반도체메모리장치의 글로벌데이터버스 프리차지 방법 및 장치
US6327202B1 (en) * 2000-08-25 2001-12-04 Micron Technology, Inc. Bit line pre-charge in a memory
US6754762B1 (en) * 2001-03-05 2004-06-22 Honeywell International Inc. Redundant bus switching
DE10121837C1 (de) * 2001-05-04 2002-12-05 Infineon Technologies Ag Speicherschaltung mit mehreren Speicherbereichen

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6376192A (ja) * 1986-09-19 1988-04-06 Fujitsu Ltd 半導体記憶装置
JP2614514B2 (ja) * 1989-05-19 1997-05-28 三菱電機株式会社 ダイナミック・ランダム・アクセス・メモリ
JP3129336B2 (ja) * 1991-12-09 2001-01-29 沖電気工業株式会社 半導体記憶装置
KR0133973B1 (ko) * 1993-02-25 1998-04-20 기다오까 다까시 반도체 기억장치
KR0137084B1 (ko) * 1993-09-14 1998-04-29 세끼자와 다다시 반도체 메모리 장치
JP3004177B2 (ja) * 1993-09-16 2000-01-31 株式会社東芝 半導体集積回路装置
JP2551360B2 (ja) * 1993-11-18 1996-11-06 日本電気株式会社 ダイナミックメモリ
KR960009953B1 (ko) * 1994-01-27 1996-07-25 삼성전자 주식회사 반도체 메모리 장치의 센스앰프 제어회로
US5512371A (en) * 1994-03-18 1996-04-30 Innotech, Inc. Composite lenses
JP3100849B2 (ja) * 1994-11-11 2000-10-23 株式会社東芝 半導体記憶装置
JP3181479B2 (ja) * 1994-12-15 2001-07-03 沖電気工業株式会社 半導体記憶装置
JP3646344B2 (ja) * 1995-04-28 2005-05-11 富士通株式会社 半導体記憶装置

Also Published As

Publication number Publication date
KR100311269B1 (ko) 2001-11-15
KR19980063547A (ko) 1998-10-07
US5828613A (en) 1998-10-27
JP3277192B2 (ja) 2002-04-22
JPH10199250A (ja) 1998-07-31

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees