TW351811B - Synchronized semiconductor memory device (3) - Google Patents

Synchronized semiconductor memory device (3)

Info

Publication number
TW351811B
TW351811B TW084114162A TW84114162A TW351811B TW 351811 B TW351811 B TW 351811B TW 084114162 A TW084114162 A TW 084114162A TW 84114162 A TW84114162 A TW 84114162A TW 351811 B TW351811 B TW 351811B
Authority
TW
Taiwan
Prior art keywords
output
data
signal
indication
mask
Prior art date
Application number
TW084114162A
Other languages
English (en)
Inventor
Seiji Sawada
Yasuhiro Konishi
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Application granted granted Critical
Publication of TW351811B publication Critical patent/TW351811B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
TW084114162A 1995-12-19 1995-12-30 Synchronized semiconductor memory device (3) TW351811B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33039495A JP3756231B2 (ja) 1995-12-19 1995-12-19 同期型半導体記憶装置

Publications (1)

Publication Number Publication Date
TW351811B true TW351811B (en) 1999-02-01

Family

ID=18232122

Family Applications (1)

Application Number Title Priority Date Filing Date
TW084114162A TW351811B (en) 1995-12-19 1995-12-30 Synchronized semiconductor memory device (3)

Country Status (6)

Country Link
US (1) US6157992A (zh)
JP (1) JP3756231B2 (zh)
KR (1) KR100256466B1 (zh)
CN (1) CN1158669C (zh)
DE (1) DE19649704B4 (zh)
TW (1) TW351811B (zh)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000100160A (ja) 1998-09-18 2000-04-07 Nec Corp 同期型半導体メモリ
KR100311044B1 (ko) * 1999-10-05 2001-10-18 윤종용 클럭 주파수에 따라 레이턴시 조절이 가능한 레이턴시 결정 회로 및 레이턴시 결정 방법
JP4025002B2 (ja) 2000-09-12 2007-12-19 株式会社東芝 半導体記憶装置
JP4095317B2 (ja) 2002-03-14 2008-06-04 富士通株式会社 非同期式半導体記憶装置、非同期式半導体記憶装置の内部制御方法及びシステム
US6795899B2 (en) 2002-03-22 2004-09-21 Intel Corporation Memory system with burst length shorter than prefetch length
JP2004185134A (ja) * 2002-11-29 2004-07-02 Matsushita Electric Ind Co Ltd 記憶装置
US20050172091A1 (en) * 2004-01-29 2005-08-04 Rotithor Hemant G. Method and an apparatus for interleaving read data return in a packetized interconnect to memory
KR100625294B1 (ko) * 2004-10-30 2006-09-18 주식회사 하이닉스반도체 전원 공급 제어 회로 및 전원 공급 회로의 제어 방법
JP4628319B2 (ja) * 2006-07-06 2011-02-09 ルネサスエレクトロニクス株式会社 同期型半導体記憶装置
KR100800382B1 (ko) * 2006-08-17 2008-02-01 삼성전자주식회사 반도체 메모리 장치에서의 신호제어방법 및 그에 따른컬럼선택라인 인에이블 신호 발생회로
KR100815179B1 (ko) * 2006-12-27 2008-03-19 주식회사 하이닉스반도체 변화하는 지연값을 가지는 메모리장치.
KR100821584B1 (ko) 2007-03-09 2008-04-15 주식회사 하이닉스반도체 라이트 트래이닝 기능을 갖는 반도체 메모리 장치
KR100933800B1 (ko) * 2008-06-30 2009-12-24 주식회사 하이닉스반도체 반도체 메모리 소자의 출력 인에이블 신호 생성회로
KR100949277B1 (ko) 2008-08-20 2010-03-25 주식회사 하이닉스반도체 데이터 입력 버퍼 인에이블 신호 발생 회로 및 방법
KR101143469B1 (ko) 2010-07-02 2012-05-08 에스케이하이닉스 주식회사 반도체 메모리의 출력 인에이블 신호 생성 회로
KR20160091686A (ko) * 2015-01-26 2016-08-03 에스케이하이닉스 주식회사 반도체 장치

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960003526B1 (ko) * 1992-10-02 1996-03-14 삼성전자주식회사 반도체 메모리장치
US5103466A (en) * 1990-03-26 1992-04-07 Intel Corporation CMOS digital clock and data recovery circuit
JP2988804B2 (ja) * 1993-03-19 1999-12-13 株式会社東芝 半導体メモリ装置
JPH07130166A (ja) * 1993-09-13 1995-05-19 Mitsubishi Electric Corp 半導体記憶装置および同期型半導体記憶装置
US5781789A (en) * 1995-08-31 1998-07-14 Advanced Micro Devices, Inc. Superscaler microprocessor employing a parallel mask decoder
JPH1139877A (ja) * 1997-07-15 1999-02-12 Mitsubishi Electric Corp 半導体記憶装置
US5983314A (en) * 1997-07-22 1999-11-09 Micron Technology, Inc. Output buffer having inherently precise data masking
JP4057125B2 (ja) * 1998-01-23 2008-03-05 株式会社ルネサステクノロジ 半導体記憶装置

Also Published As

Publication number Publication date
CN1158669C (zh) 2004-07-21
CN1157986A (zh) 1997-08-27
JP3756231B2 (ja) 2006-03-15
KR970051305A (ko) 1997-07-29
KR100256466B1 (ko) 2000-05-15
US6157992A (en) 2000-12-05
DE19649704B4 (de) 2004-07-08
JPH09167485A (ja) 1997-06-24
DE19649704A1 (de) 1997-06-26

Similar Documents

Publication Publication Date Title
TW351811B (en) Synchronized semiconductor memory device (3)
TW367501B (en) Synchronous semiconductor memory device
TW353750B (en) Synchronous type semiconductor memory
TW353176B (en) A semiconductor device capable of holding signals independent of the pulse width of an external clock and a computer system including the semiconductor
GB2307068B (en) Numerical control system using a personal computer and a method of controlling the same
KR950010564B1 (en) Data output buffer of synchronous semiconductor memory device
KR970023373A (ko) 동기식 반도체 메모리
KR970016970A (ko) 동기메모리의 고주파동작용 데이타 출력버퍼 제어방법
CA2037289A1 (en) Single circuit for detecting a frame synchronization pattern and generating control signals
TW343296B (en) Internal clock generation circuit of semiconductor device and method for generating internal clock
KR890003147A (ko) 선택호출수신기
TW430803B (en) Clock synchronous memory
CA2042676A1 (en) Ringing signal control circuit for an enhanced subscriber line interface
TW329488B (en) Synchronous serial data transmission device
SE9501608L (sv) Fördröjningsanpassad klock- och datagenerator
MY116600A (en) Radio communications device with reference-compensated power down control and methods of operating thereof
KR0163889B1 (ko) 슬립모드 제어회로
JPS57143993A (en) Data transfer system
JPS57198595A (en) Dynamic memory driving circuit
TW342501B (en) Data input circuit including echo clock generator
KR970056002A (ko) 개인통신용 단말기의 호출채널 쉬프트 클록신호 발생장치
JPS6472653A (en) Digital talkie trunk
KR970056005A (ko) 개인통신용 단말기의 호출채널 쉬프트 클록신호 발생장치
KR970055934A (ko) 개인통신용 단말기의 프레임동기신호 발생장치
KR970055929A (ko) 개인통신용 단말기의 102-멀티프레임 동기신호 발생장치

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees