TW202243155A - 記憶裝置及記憶裝置模組 - Google Patents
記憶裝置及記憶裝置模組 Download PDFInfo
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Abstract
本發明之記憶裝置具備:配線基板,其具有第1面、第1面之相反側之第2面、及多層配線層;控制元件,其埋入配線基板內,且具有配置與多層配線層連接之複數個電極焊墊之第1元件面、與第1元件面之相反側之第2元件面;第1散熱構件,其配置於配線基板之第1面中與控制元件重疊之區域;散熱構造,其與控制元件之第2元件面對向,並自配線基板之第2面露出;及至少1個記憶體元件,其等配置於配線基板之第1面中不與控制元件重疊之區域,並與多層配線層連接。多層配線層具有:信號圖案,其電性連接控制元件、與記憶體元件或外部連接端子;及散熱導體圖案,其形成控制元件與第1散熱構件之間之散熱路徑。
Description
本發明係關於一種記憶裝置及記憶裝置模組。
SSD(Solid State Drives:固態驅動器)具有將NAND(Not-AND:與非)型記憶體元件、與控制該記憶體元件之控制元件(控制器)安裝於配線基板上之構成。藉由近年之記憶容量之大容量化或高速動作化之進展,控制元件之高性能化有所發展,且發熱量亦增大。若記憶體元件之溫度亦因該控制元件之熱量而上升,則有時必須降低記憶體元件之動作速度(寫入速度或讀入速度)。
[先前技術文獻]
[專利文獻]
[專利文獻1]日本專利第5767338號公報
[專利文獻2]日本專利第6584258號公報
[發明所欲解決之問題]
本發明之目的在於提供一種提高控制元件之散熱性之記憶裝置及記憶裝置模組。
[解決問題之技術手段]
根據本發明之一態様,記憶裝置具備:配線基板,其具有第1面、上述第1面之相反側之第2面、及多層配線層;控制元件,其埋入上述配線基板內,且具有配置與上述多層配線層連接之複數個電極焊墊之第1元件面、與上述第1元件面之相反側之第2元件面;第1散熱構件,其配置於上述配線基板之上述第1面中與上述控制元件重疊之區域;散熱構造,其與上述控制元件之上述第2元件面對向,並自上述配線基板之上述第2面露出;及至少1個記憶體元件,其等配置於上述配線基板之上述第1面中不與上述控制元件重疊之區域,並與上述多層配線層連接。上述多層配線層具有:信號圖案,其電性連接上述控制元件、與上述記憶體元件或外部連接端子;及散熱導體圖案,其形成上述控制元件與上述第1散熱構件之間之散熱路徑。
以下,參照圖式,對實施形態進行說明。另,於各圖式中,對相同構成標註相同符號。
[第1實施形態]
圖1係第1實施形態之記憶裝置1之模式剖視圖。
記憶裝置1具備配線基板10、控制元件20、至少1個記憶體元件40、第1散熱構件31、及散熱構造32。另,雖未圖示,但連接連接器、晶片電容器等搭載於配線基板10。例如,連接連接器作為與外部電路電性連接之外部連接端子發揮功能。
配線基板10具有第1面11、第1面11之相反側之第2面12、多層配線層50、及絕緣層13。多層配線層50為金屬層,例如包含銅。於多層配線層50之層間設置有絕緣層13。絕緣層13例如為包含環氧樹脂之樹脂層。
控制元件20埋入配線基板10內。控制元件20例如為未進行樹脂塑模之矽晶片半導體元件,具有配設數百個電極焊墊之第1元件面21、與第1元件面21之相反側之第2元件面22。第1元件面21朝向配線基板10之第1面11側,第2元件面22朝向配線基板10之第2面12側。控制元件20之側面由配線基板10之絕緣層13覆蓋。
圖7係控制元件20之第1元件面21之模式俯視圖。
於控制元件20,形成有用以控制記憶體元件40之讀出/寫入之積體電路。於第1元件面21,配置有與積體電路電性連接之複數個電極焊墊54a、54b、54c。電極焊墊54a、54b、54c與配線基板10之多層配線層50電性連接。
控制元件20之電極焊墊包含圖7中附註有“PW”之複數個電源焊墊54a、與圖7中附註有“GND”之複數個接地焊墊54b。對電源焊墊54a賦予電源電位,且對接地焊墊54b賦予接地電位。電極焊墊進而包含複數個信號焊墊54c。通過信號焊墊54c,於控制元件20與記憶體元件40之間、及/或控制元件20與輸入來自外部之輸入信號之外部連接端子之間交換各種信號。
如圖1所示,於配線基板10之第1面11中與控制元件20重疊之區域,配置有第1散熱構件31。例如,第1散熱構件31為具有複數個鰭片之金屬構件。第1散熱構件31之上表面31a及側面31b、31c於第1面11上自配線基板10露出。第1散熱構件31之下表面介隔多層配線層50,與控制元件20之第1元件面21對向。第1散熱構件31之高度較記憶體元件40之高度高。
與控制元件20之第2元件面22對向,配置有散熱構造32。散熱構造32中與第2元件面22對向之面之相反側之面,自配線基板10之第2面12露出。
於配線基板10之第1面11中不與控制元件20重疊之區域,配置有複數個記憶體元件40。自第1散熱構件31朝向記憶體元件40之第1方向相對於自控制元件20朝向第1散熱構件31之第2方向正交。又,自控制元件20朝向記憶體元件40之第3方向相對於上述第1方向及第2方向傾斜。
記憶體元件40具有將積層於基板42上之複數個記憶體晶片41以樹脂44密封之封裝構造。記憶體晶片41例如為NAND型記憶體。金屬導線45將記憶體晶片41、與形成於基板42之配線層電性連接。樹脂44覆蓋複數個記憶體晶片41及金屬導線45。於基板42之背面,配置有與基板42之配線層電性連接之複數個端子(例如,焊料球)43。端子43與配線基板10之多層配線層50電性連接。該記憶體元件40若超過約80℃,則可使寫入/讀出之動作速度降低,且為維持動作品質而使性能下降且於高溫下亦進行動作。
圖2係記憶裝置1中配置有控制元件20及第1散熱構件31之部分之詳細之模式剖視圖。
於控制元件20之第1元件面21與第1散熱構件31之間,例如設置有3層配線層(導體圖案L1a~b、L2a~c、L3a~c)。各配線層經由複數個導通孔而層間連接。另,控制元件20與第1散熱構件31之間之配線層之層數不限於此,亦可為2層或4層以上。
多層配線層50具有電性連接控制元件20與記憶體元件40之信號圖案L2c、L3c、及熱連接控制元件20與第1散熱構件31之散熱導體圖案L1a、L1b、L2a、L2b、L3a、L3b。散熱導體圖案L1a、L1b、L2a、L2b、L3a、L3b形成控制元件20與第1散熱構件31之間之散熱路徑。
圖3係配線基板10之第1面11側之最上層之配線層之模式俯視圖。最上層之配線層包含第1電源圖案L1a與第1接地圖案L1b。第1電源圖案L1a兼作賦予電源電位之電源圖案、及與第1散熱構件31熱連接之散熱導體圖案。第1接地圖案L1b兼作賦予接地電位之接地圖案、及與第1散熱構件31熱連接之散熱導體圖案。
第1電源圖案L1a之寬度及第1接地圖案L1b之寬度較信號圖案之寬度寬,且第1電源圖案L1a及第1接地圖案L1b形成為板狀。
如圖2所示,於第1電源圖案L1a上及第1接地圖案L1b上設置有第1散熱構件31。於第1電源圖案L1a與第1散熱構件31之間、及第1接地圖案L1b與第1散熱構件31之間,設置有熱傳導性之絕緣構件14。
最表層之信號圖案由絕緣保護膜(阻焊劑)15覆蓋。
圖4係圖3所示之配線層之下層之配線層之模式俯視圖。於圖4所示之層,設置有第2電源圖案L2a、第2接地圖案L2b、及第2信號圖案L2c。
第2信號圖案L2c形成為複數個線狀。第2信號圖案L2c電性連接控制元件20之信號焊墊54c、與輸入來自記憶體元件40及/或外部之輸入信號之外部連接端子。
第2電源圖案L2a形成為寬度較第2信號圖案L2c寬之板狀,且亦於配置有記憶體元件40之區域延伸。第2電源圖案L2a經由複數個導通孔51a,與第1電源圖案L1a電性連接。第2電源圖案L2a兼作電源圖案、與散熱導體圖案。
第2接地圖案L2b形成為複數個島狀。各個第2接地圖案L2b經由導通孔51b,與第1接地圖案L1b電性連接。第2接地圖案L2b兼作接地圖案、與散熱導體圖案。
圖5及圖6係圖4所示之配線層之下層之配線層之模式俯視圖。於圖5及圖6所示之層,設置有第3電源圖案L3a、第3接地圖案L3b、及第3信號圖案L3c。
第3信號圖案L3c形成為複數個線狀。第3信號圖案L3c電性連接控制元件20之信號焊墊54c、與輸入來自記憶體元件40及/或外部之輸入信號之外部連接端子。
第3電源圖案L3a形成為寬度較第3信號圖案L3c寬之板狀。第3電源圖案L3a經由複數個導通孔52a,與第2電源圖案L2a電性連接。第3電源圖案L3a兼作電源圖案、與散熱導體圖案。
第3接地圖案L3b形成為寬度較第3信號圖案L3c寬之板狀。第3接地圖案L3b經由導通孔52b,與第2接地圖案L2b電性連接。第3接地圖案L3b兼作接地圖案、與散熱導體圖案。第3接地圖案L3b之一部分形成為線狀,且亦於配置有記憶體元件40之區域延伸。
圖7所示之控制元件20之第1元件面21位於設置有第3電源圖案L3a、第3接地圖案L3b、及第3信號圖案L3c之層下。第3電源圖案L3a、第3接地圖案L3b、及第3信號圖案L3c分別經由圖6中虛線所示之導通孔53a、導通孔53b、及導通孔53c,與控制元件20之電極焊墊連接。
第3電源圖案L3a經由導通孔53a,與控制元件20之電源焊墊54a電性連接。第3接地圖案L3b經由導通孔53b,與控制元件20之接地焊墊54b電性連接。第3信號圖案L3c經由導通孔53c,與控制元件20之信號焊墊54c電性連接。不同之層之信號圖案間由導通孔電性連接。
控制元件20發出之熱經由電源圖案L3a、L2a、L1a、接地圖案L3b、L2b、L1b、導通孔53a、52a、51a、53b、52b、51b、及熱傳導性之絕緣構件14,傳遞至第1散熱構件31,並自第1散熱構件31朝記憶裝置1之外部散熱。
另,亦可僅藉由電源圖案,將控制元件20與第1散熱構件31熱連接。又,可僅藉由接地圖案,將控制元件20與第1散熱構件31熱連接。該情形時,接地圖案可不經由絕緣構件地與第1散熱構件31連接。
另一方面,如圖2所示,於控制元件20之第2元件面22,形成有散熱構造32。散熱構造32例如包含複數個金屬層60、L4、L5、L5、及將該等金屬層間連接之複數個熱導通孔61、62、63。金屬層及熱導通孔包含與多層配線層50同樣之材料(例如銅)。
圖8係控制元件20之第2元件面22之模式俯視圖。
於控制元件20之第2元件面22不配置電極焊墊,而將例如矽之表面擴展至整面。於該第2元件面22設置有第1金屬層60。第1金屬層60未與控制元件20之積體電路電性連接。第1金屬層60覆蓋第2元件面22之整面。
於第1金屬層60連接有複數個第1熱導通孔61。複數個第1熱導通孔61之數量多於配置於控制元件20之第1元件面21的電極焊墊之數量。第1熱導通孔61作為散熱通路發揮功能。第1熱導通孔61可不考慮與控制元件20之積體電路之電性連接而配置。因此,可藉由數量較配置於第1元件面21之電極焊墊更多之第1熱導通孔61,提高自第2元件面22側之散熱性。
圖9係第1金屬層60之下之第2金屬層L4之模式俯視圖。第2金屬層L4於配線基板10之絕緣層13內,以較控制元件20之第2元件面22更寬之面積擴展。第2金屬層L4藉由上述之複數個第1熱導通孔61,與第1金屬層60連接。
又,於第2金屬層L4中與第1金屬層60連接之面為相反側之面,連接有複數個第2熱導通孔62。
圖10係第2金屬層L4之下之第3金屬層L5之模式俯視圖。第3金屬層L5於配線基板10之絕緣層13內,以較控制元件20之第2元件面22更寬之面積擴展。第3金屬層L5藉由上述之複數個第2熱導通孔62,與第2金屬層L4連接。
由於將第2金屬層L4之面積及第3金屬層L5之面積設得較控制元件20之第2元件面22寬,故可將連接該等之第2熱導通孔62之數量設得比與控制元件20之第2元件面22連接之第1熱導通孔61多。藉此,可增加散熱通路,而提高散熱性。
圖11係第3金屬層L5之下之第4金屬層L6之模式俯視圖。第4金屬層L6於配線基板10之絕緣層13內,以較控制元件20之第2元件面22寬之面積擴展。第4金屬層L6藉由複數個第3熱導通孔63,與第3金屬層L5連接。
由於將第3金屬層L5之面積及第4金屬層L6之面積設得較控制元件20之第2元件面22寬,故可將連接該等之第3熱導通孔63之數量設得較與控制元件20之第2元件面22連接之第1熱導通孔61多。藉此,可增加散熱通路,而提高散熱性。
如圖2所示,於配線基板10之第2面12側形成絕緣保護膜(阻焊劑)16,且第4金屬層L6之表面自保護膜16露出。
控制元件20產生之熱量經由金屬層60、L4、L5、L6、及熱導通孔61~63,散熱至記憶裝置1之外部。另,散熱構造32包含之金屬層之層數不限於圖2所示之層數。
根據本發明之實施形態,可藉由將控制元件20埋入配線基板10內,而將控制元件20之兩面(第1元件面21及第2元件面22)各者以形成向配線基板10之兩面之散熱路徑之方式,連接於第1散熱構件31與散熱構造32。因此,可自兩面通過第1散熱構件31與散熱構造32有效地將控制元件20產生之熱量散熱。又,記憶體元件40不位於自控制元件20向第1散熱構件31及散熱構造32之散熱路徑中。根據此種本實施形態,可抑制控制元件20之熱量傳遞至記憶體元件40。藉此,可抑制記憶體元件40上升至可招致寫入速度或讀入速度降低之溫度(例如,80℃以上)。
根據圖12及圖13所示之例,於控制元件20之第1元件面21形成有不與控制元件20之電路、電極焊墊、及配線基板10之信號圖案連接,而經由配線基板10之散熱導體圖案與第1散熱構件31連接之金屬圖案71、72。
於圖12所示之例中,形成有包圍控制元件20之第1元件面21中配置有複數個電極焊墊54a、54b、54c之區域之熱環71。熱環71例如包含銅。
於圖13所示之例中,於控制元件20之第1元件面21中之複數個電極焊墊54a、54b、54c以外之區域形成有熱平面72。於熱平面72形成複數個開口,且電極焊墊54a、54b、54c位於該開口。熱平面72例如包含銅。
藉由於控制元件20之第1元件面21形成電極焊墊54a、54b、54c以外之金屬圖案71、72,並使該金屬圖案71、72經由配線基板10之散熱導體圖案與第1散熱構件31連接,而可進一步提高控制元件20之第1元件面21側之散熱性。
[第2實施形態]
圖14係第2實施形態之記憶裝置2之模式剖視圖。
第2實施形態之記憶裝置2具備連接於第2元件面22之第2散熱構件132,作為控制元件20之第2元件面22側之散熱構造。第2散熱構件132例如藉由焊料膏134接合於第2元件面22。第2散熱構件132例如為包含銅之金屬體。第2散熱構件132埋入於配線基板10之絕緣層13內,一面與控制元件20之第2元件面22相接,另一面自配線基板10之第2面12露出。第2散熱構件132可為硬幣形狀之銅。
[第3實施形態]
圖15係第3實施形態之記憶裝置3之模式剖視圖。
於第3實施形態之記憶裝置3中,將記憶體元件140之複數個記憶體晶片41,不經由基板等而直接積層於配線基板10之第1面11上。且,於配線基板10之第1面11上,設置有覆蓋複數個記憶體晶片41及金屬導線45之樹脂構件150。
樹脂構件150覆蓋第1散熱構件31之側面31b、31c。第1散熱構件31之表面31a(配線基板10之第1面11所對向之面之相反側之面)自樹脂構件150露出。另,第1散熱構件31之側面31b、31c亦可自樹脂構件150露出。
[第4實施形態]
圖16係第4實施形態之記憶裝置模組4之模式俯視圖。
該記憶裝置模組4具備上述之第1實施形態之複數個記憶裝置1、與冷卻構件100。另,記憶裝置模組4具備之複數個記憶裝置亦可為第2或第3實施形態之構成。
複數個記憶裝置1於圖16中於橫向排列,且例如以適合資料中心之大容量構成搭載複數個SSD之記憶體儲存裝置。於相鄰之配線基板10彼此中,使一配線基板10之第1面11與另一配線基板10之第2面12對向。
於圖16中於紙面縱深方向設置有模組基板。於各配線基板10之紙面縱深方向設置連接器,並將該連接器插入至模組基板之插口。
複數個記憶裝置1於相鄰之記憶裝置1中之一記憶裝置1之散熱構造32自配線基板10露出之面32a,連接另一記憶裝置1之第1散熱構件31之表面31a而排列。
冷卻構件100沿複數個記憶裝置1排列之方向延伸,且連接於各記憶裝置1之第1散熱構件31之側面31c(插入至模組基板之側之相反側之面)。冷卻構件100例如包含散熱器等之金屬構件、風扇等之空冷裝置、水冷裝置、氣冷裝置或其等之組合。
根據本實施形態,藉由各記憶裝置1之兩面之散熱構件31、32與另一記憶裝置1之散熱構件31及散熱構造32連接並接觸,而構成更大之金屬體,且以覆蓋該金屬體之整體之方式連接冷卻構件100,因而於模組整體獲得非常高之散熱性。
於以上說明之各實施形態中,未將記憶體元件40、140安裝於配線基板10之第2面12,而安裝於與第1散熱構件31之安裝面相同之第1面11,藉此可將記憶裝置及記憶裝置模組整體之厚度薄化。
可於配線基板10之第2面12中與記憶體元件40重疊之區域,安裝其他元件或進而安裝記憶體元件。又,如圖1、圖14、圖15所示,亦可於配線基板10之第2面12側中,將多層配線層150形成於與記憶體元件40重疊之區域。多層配線層150例如經由IVH(interstitial via hole:局部層間導通孔),與第1面11側之多層配線層50電性連接。
[第5實施形態]
圖17係第5實施形態之記憶裝置5之模式剖視圖。
第5實施形態之記憶裝置5中之控制元件20之第2元件面22側之散熱構造130與圖14所示之第2實施形態同樣,具備連接於第2元件面22之第2散熱構件132。再者,散熱構造130具備連接於第2散熱構件132之、自配線基板10之第2面12露出之面132a的第3散熱構件133。第3散熱構件133可於配線基板10之第2面12側中露出於配線基板10之外部,並設為較埋入配線基板10之第2散熱構件132厚。第3散熱構件133例如為具有複數個鰭片之金屬構件。
又,第5實施形態之記憶裝置5具有雙面安裝構造。於配線基板10之第2面12上與記憶體元件40重疊之區域,安裝有另一記憶體元件240。記憶體元件240例如包含DRAM(Dynamic Random Access Memory:動態隨機存取記憶體)晶片241。
又,亦可於配線基板10之第2面12上與記憶體元件40重疊之區域,例如安裝電阻或電容器等之被動元件250、或與安裝於第1面11之記憶體元件40相同之記憶體元件40。自配線基板10之第2面12突出之第3散熱構件133之高度,高於記憶體元件40之高度、記憶體元件240之高度、及被動元件250之高度。
於配線基板10之第2面12側,形成有與控制元件20電性連接之多層配線層150。又,多層配線層150例如經由IVH,與第1面11側之多層配線層50電性連接。安裝於第2面12之記憶體元件240、被動元件250、及記憶體元件40與多層配線層150電性連接。
[第6實施形態]
圖18係第6實施形態之記憶裝置模組6之模式俯視圖。
該記憶裝置模組6具備上述第5實施形態之複數個記憶裝置5、與冷卻構件100。
複數個記憶裝置5於圖18中於橫向排列,且例如以適合資料中心之大容量構成搭載複數個SSD之記憶體儲存裝置。於相鄰之配線基板10彼此中,使一配線基板10之第1面11與另一配線基板10之第2面12對向。
於圖18中,於紙面縱深方向設置有模組基板。於各配線基板10之紙面縱深方向設置連接器,並將該連接器插入至模組基板之插口。
複數個記憶裝置5於相鄰之記憶裝置5中之一記憶裝置5之第3散熱構件133,連接另一記憶裝置5之第1散熱構件31而排列。
冷卻構件100沿複數個記憶裝置5排列之方向延伸,且連接於各記憶裝置5之第1散熱構件31之側面31c及第3散熱構件133之側面133c。冷卻構件100例如包含散熱器等之金屬構件、風扇等之空冷裝置、水冷裝置、氣冷裝置或其等之組合。
根據本實施形態,藉由各記憶裝置5之兩面之散熱構件31、133與另一記憶裝置5之散熱構件31、133連接並接觸,而構成更大之金屬體,且以覆蓋該金屬體之整體之方式連接冷卻構件100,因而於模組整體獲得非常高之散熱性。
雖已說明本發明之若干實施形態,但該等實施形態係作為例而提示者,並未意欲限定發明之範圍。該等新穎之實施形態係可以其他多種形態實施,且於不脫離發明之主旨之範圍內,可進行多種省略、置換、變更。該等實施形態或其變化包含於發明範圍或主旨內,且包含於申請專利範圍所記載之發明及其均等之範圍內。
1~3,5:記憶裝置
4,6:記憶裝置模組
10:配線基板
11:第1面
12:第2面
13:絕緣層
14:絕緣構件
15:絕緣保護膜
16:絕緣保護膜
20:控制元件
21:第1元件面
22:第2元件面
31:第1散熱構件
31a:上表面
31b:側面
31c:側面
32,130:散熱構造
32a:面
40:記憶體元件
41:記憶體晶片
42:基板
43:端子
44:樹脂
45:金屬線
50:多層配線層
51a,51b:導通孔
52a,52b:導通孔
53a,53b,53c:導通孔
54a:電極焊墊/電源焊墊
54b:電極焊墊/接地焊墊
54c:電極焊墊/信號焊墊
60:第1金屬層
61:第1熱導通孔
62:第2熱導通孔
63:第3熱導通孔
71:金屬圖案/熱環
72:金屬圖案/熱平面
100:冷卻構件
132:第2散熱構件
132a:面
133:第3散熱構件
133c:側面
134:焊膏
140:記憶體元件
150:樹脂構件/多層配線層
240:記憶體元件
241:DRAM晶片
250:被動元件
GND:接地焊墊
L1a:散熱導體圖案/第1電源圖案
L1b:散熱導體圖案/第1接地圖案
L2a:散熱導體圖案/第2電源圖案
L2b:散熱導體圖案/第2接地圖案
L2c:第2信號圖案
L3a:散熱導體圖案/第3電源圖案
L3b:散熱導體圖案/第3接地圖案
L3c:第3信號圖案
L4:第2金屬層
L5:第3金屬層
L6:第4金屬層
PW:電源焊墊
圖1係第1實施形態之記憶裝置之模式剖視圖。
圖2係第1實施形態之記憶裝置中配置有控制元件及第1散熱構件之部分之詳細之模式剖視圖。
圖3係第1實施形態之記憶裝置中之配線基板之配線層之模式俯視圖。
圖4係第1實施形態之記憶裝置中之配線基板之配線層之模式俯視圖。
圖5係第1實施形態之記憶裝置中之配線基板之配線層之模式俯視圖。
圖6係第1實施形態之記憶裝置中之配線基板之配線層之模式俯視圖。
圖7係第1實施形態之記憶裝置中之控制元件之第1元件面之模式俯視圖。
圖8係第1實施形態之記憶裝置中之控制元件之第2元件面之模式俯視圖。
圖9係第1實施形態之記憶裝置中之散熱構造之模式俯視圖。
圖10係第1實施形態之記憶裝置中之散熱構造之模式俯視圖。
圖11係第1實施形態之記憶裝置中之散熱構造之模式俯視圖。
圖12係第1實施形態之記憶裝置中之控制元件之第1元件面之模式俯視圖。
圖13係第1實施形態之記憶裝置中之控制元件之第1元件面之模式俯視圖。
圖14係第2實施形態之記憶裝置之模式剖視圖。
圖15係第3實施形態之記憶裝置之模式剖視圖。
圖16係第4實施形態之記憶裝置模組之模式俯視圖。
圖17係第5實施形態之記憶裝置之模式剖視圖。
圖18係第6實施形態之記憶裝置模組之模式俯視圖。
1:記憶裝置
10:配線基板
11:第1面
12:第2面
13:絕緣層
14:絕緣構件
16:絕緣保護膜
20:控制元件
21:第1元件面
22:第2元件面
31:第1散熱構件
31a:上表面
31b:側面
31c:側面
32:散熱構造
40:記憶體元件
41:記憶體晶片
42:基板
43:端子
44:樹脂
45:金屬導線
50:多層配線層
150:樹脂構件/多層配線層
Claims (9)
- 一種記憶裝置,其具備: 配線基板,其具有第1面、上述第1面之相反側之第2面、及多層配線層; 控制元件,其埋入上述配線基板內,且具有配置有與上述多層配線層連接之複數個電極焊墊之第1元件面、及上述第1元件面之相反側之第2元件面; 第1散熱構件,其配置於上述配線基板之上述第1面上與上述控制元件重疊之區域; 散熱構造,其與上述控制元件之上述第2元件面對向,並自上述配線基板之上述第2面露出;及 至少1個記憶體元件,其等配置於上述配線基板之上述第1面上不與上述控制元件重疊之區域,並與上述多層配線層連接;且 上述多層配線層具有:信號圖案,其電性連接上述控制元件、與上述記憶體元件或外部連接端子;及散熱導體圖案,其形成上述控制元件與上述第1散熱構件之間之散熱路徑。
- 如請求項1之記憶裝置,其中於上述配線基板之上述第2面上不與上述控制元件重疊之區域,進而配置與上述多層配線層連接之至少1個記憶體元件。
- 如請求項2之記憶裝置,其中上述散熱構造包含自上述配線基板之上述第2面突出之第3散熱構件。
- 如請求項1或2之記憶裝置,其中上述控制元件之上述電極焊墊包含電源焊墊與接地焊墊; 上述散熱導體圖案包含與上述電源焊墊連接且寬度較上述信號圖案寬之電源圖案、及與上述接地焊墊連接且寬度較上述信號圖案寬之接地圖案之至少任一者。
- 如請求項1或2之記憶裝置,其中於上述控制元件之上述第1元件面,設置有不與上述控制元件之上述電極焊墊及上述配線基板之上述信號圖案連接、而與上述散熱導體圖案連接之金屬圖案。
- 如請求項1或2之記憶裝置,其中上述散熱構造包含: 金屬層,其設置於上述控制元件之上述第2元件面;及 複數個熱導通孔,其等連接於上述金屬層,且數量多於上述電極焊墊。
- 如請求項1或2之記憶裝置,其中上述散熱構造包含埋入上述配線基板之第2散熱構件。
- 一種記憶裝置模組,其具備如請求項1之複數個記憶裝置、及冷卻構件;且 上述複數個記憶裝置排列為,於相鄰之記憶裝置中之一記憶裝置之上述散熱構造之自上述配線基板露出之面,連接另一記憶裝置之上述第1散熱構件; 上述冷卻構件沿上述複數個記憶裝置排列之方向延伸,且連接於上述第1散熱構件之側面。
- 一種記憶裝置模組,其具備如請求項3之複數個記憶裝置、及冷卻構件;且 上述複數個記憶裝置排列為,對於相鄰之記憶裝置中之一記憶裝置之上述散熱構造之自上述配線基板露出之上述第3散熱構件,連接另一記憶裝置之上述第1散熱構件; 上述冷卻構件沿上述複數個記憶裝置排列之方向延伸,且連接於上述第1散熱構件之側面及上述第3散熱構件之側面。
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