TW202111823A - 半導體裝置及其製造方法 - Google Patents
半導體裝置及其製造方法 Download PDFInfo
- Publication number
- TW202111823A TW202111823A TW109106485A TW109106485A TW202111823A TW 202111823 A TW202111823 A TW 202111823A TW 109106485 A TW109106485 A TW 109106485A TW 109106485 A TW109106485 A TW 109106485A TW 202111823 A TW202111823 A TW 202111823A
- Authority
- TW
- Taiwan
- Prior art keywords
- substrate
- resin
- semiconductor
- semiconductor wafer
- spacer
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 191
- 239000000758 substrate Substances 0.000 claims abstract description 103
- 125000006850 spacer group Chemical group 0.000 claims abstract description 83
- 239000011347 resin Substances 0.000 claims description 140
- 229920005989 resin Polymers 0.000 claims description 140
- 229910000679 solder Inorganic materials 0.000 claims description 14
- 238000004382 potting Methods 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 239000012811 non-conductive material Substances 0.000 claims description 4
- 238000000034 method Methods 0.000 claims description 2
- 235000012431 wafers Nutrition 0.000 description 147
- 238000010586 diagram Methods 0.000 description 17
- 239000000853 adhesive Substances 0.000 description 6
- 230000001070 adhesive effect Effects 0.000 description 6
- 238000007654 immersion Methods 0.000 description 5
- 239000007788 liquid Substances 0.000 description 5
- 238000000465 moulding Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000005484 gravity Effects 0.000 description 2
- 238000005470 impregnation Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/54—Providing fillings in containers, e.g. gas fillings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
- H01L2224/49176—Wire connectors having the same loop shape and height
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0651—Wire or wire-like electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06575—Auxiliary carrier between devices, the carrier having no electrical connection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Dispersion Chemistry (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
實施形態提供一種不易形成因樹脂填充不足所導致之間隙之半導體裝置及其製造方法。 實施形態之半導體裝置具有:基板;第1半導體晶片,其搭載於上述基板面上,與上述基板電性連接;複數個間隔件,其等在上述基板面上,於上述第1半導體晶片之周圍介隔空隙而相互隔開,且介隔第1非導電性材而設置;第2半導體晶片,其介隔上述複數個間隔件自上述第1半導體晶片相對於上述基板面朝上方向隔開設置,且與上述基板電性連接;及突出部,其於上述空隙之一部分具有自上述基板面上朝上方向突出之形狀。
Description
本發明之實施形態係關於一種半導體裝置及其製造方法。
將半導體晶片安裝於基板上之後,藉由樹脂將半導體晶片之周圍模塑。若因樹脂填充不足而導致半導體封裝體內存在間隙,則有產生半導體封裝體出現龜裂等不良之虞。
實施形態提供一種不易形成因樹脂填充不足所導致之間隙之半導體裝置及其製造方法。
實施形態之半導體裝置具有:基板;第1半導體晶片,其搭載於上述基板面上,與上述基板電性連接;複數個間隔件,其等在上述基板面上,於上述第1半導體晶片之周圍介隔空隙而相互隔開,且介隔第1非導電性材而設置;第2半導體晶片,其介隔上述複數個間隔件自上述第1半導體晶片相對於上述基板面朝上方向隔開設置,且與上述基板電性連接;及突出部,其於上述空隙之一部分具有自上述基板面上朝上方向突出之形狀。
以下,參照圖式說明實施形態。再者,圖式係模式性之圖式,應注意各構件之厚度與寬度之關係、各個構件之厚度之比率等與實現情況不同,當然,於圖式相互間亦包含彼此之尺寸關係或比率不同之部分。
(構成) 圖1係本實施形態之半導體裝置之俯視圖。圖2係半導體裝置之組裝圖。圖3係半導體裝置之前視圖。本實施形態之半導體裝置1係於樹脂內將複數個半導體晶片堆積於基板上,且具有與內部之各半導體晶片電性連接之外部端子群之半導體封裝體。
半導體裝置1之基板11係上表面11a具有長方形形狀之BGA(Ball Grid Array,球狀柵格陣列)封裝體基板。此處,基板11為玻璃環氧化物製之插入物。基板11經由基板之下表面11b之複數個焊球11c而連接於未圖示之電路基板上之複數個電極。
為了將各半導體晶片裝入至較薄之半導體封裝體內,而對形成有半導體電路之半導體晶圓之背面進行研削。於被研削而變薄之半導體晶圓背面,貼附用以接著於基板11之DAF(Die Attachment Film,晶粒附接膜),半導體晶圓與作為接著劑之DAF一起被切割,而以半導體晶片為單位被分割。
半導體晶片12被加熱,藉由DAF而固定於基板11之上表面11a。於基板11上堆積複數個半導體晶片,但半導體晶片12配置於最下段,於該半導體晶片12之上方載置較大之半導體晶片。
於將半導體封裝體用於行動電話等之情形時,封裝體尺寸受到限制,尤其需要抑制高度。通常,於堆積複數個半導體晶片之情形時,將較大之晶片搭載於下段且將較小之晶片搭載於上段之情形較多。然而,於插入物之配線等受到限制,或如NAND(Not AND,反及)記憶體之控制器晶片般晶片尺寸較小但接合線數量較多,於3方向或4方向之晶片之邊上打線接合之情形時,將較小之半導體晶片搭載於最下段,將較大之記憶體晶片設置於上段。
如圖1所示,半導體晶片12之上表面12a之複數個焊墊藉由金等之打線接合,而經由複數條接合線12b與設置於基板11之上表面之複數個電極連接。如上所述,半導體晶片12搭載於基板11上,且藉由複數條接合線12b與基板11電性連接。
為了於最下段之半導體晶片12之上方確保特定之間隙,而將複數個間隔構件設置於基板11上。將作為間隔件之4個間隔晶片13A、13B、13C、13D搭載於設置有複數條接合線12b之半導體晶片12周圍之基板11之上表面11a。以下,於指全部4個或任意1個以上之間隔晶片時,稱為間隔晶片13。此處,4個間隔晶片13係矽晶圓片,為相同尺寸,且具有相同之長方體形狀。
如圖1所示,將半導體晶片12配置於長方形之基板11之中央部,4個間隔晶片13配置於基板11之4個角。間隔晶片13A與13B沿著基板11之長向軸方向D1配置,間隔晶片13C與13D亦沿著基板11之長向軸方向D1配置。又,間隔晶片13A與13C沿著基板11之短向軸方向D2配置,間隔晶片13B與13D亦沿著基板11之短向軸方向D2配置。各間隔晶片13藉由DAF等接著劑而接著並固定於基板11上。
如圖3所示,基板11之上表面11a至半導體晶片12之上表面12a之高度h1低於各間隔晶片13之高度h2。
於間隔晶片13A與13C上,搭載有半導體晶片14A。同樣地,於間隔晶片13B與13D上,搭載有半導體晶片14B。如圖1所示,半導體晶片14A與14B具有長方形形狀。半導體晶片14A與14B藉由DAF等接著劑而接著並固定於間隔晶片13A、13C與13B、13D上。
以半導體晶片14A之長向軸與基板11之短向軸方向D2平行之方式,半導體晶片14A沿著基板11之短向軸方向D2搭載於間隔晶片13A與13C上。同樣地,以半導體晶片14B之長向軸與基板11之短向軸方向D2平行之方式,半導體晶片14B沿著基板11之短向軸方向D2搭載於間隔晶片13B與13D上。以各半導體晶片14A、14B之長向軸方向之兩端部之下表面由2個間隔晶片13之上表面支持之方式,各半導體晶片14A、14B載置於2個間隔晶片13上,並藉由接著劑固定。
再者,如上所述,半導體晶片12之高度h1低於各間隔晶片13之高度h2,故各半導體晶片14A、14B之下表面未與半導體晶片12及複數條接合線12b接觸。換言之,於各半導體晶片14A、14B之下表面與半導體晶片12之上表面12a之間形成有間隙。如上所述,複數個間隔晶片13搭載於基板11上之半導體晶片12之周圍,半導體晶片14A、14B隔著設置於基板11上之複數個間隔晶片13而與半導體晶片12隔開設置。
進而,於半導體晶片14A、14B上搭載有半導體晶片15。如圖1所示,半導體晶片15具有長方形形狀。此處,半導體晶片15於半導體晶片14A、14B之長向軸方向(基板11之短向軸方向D2)上偏向一側(圖1之下側)而配置。
以半導體晶片15之長向軸與基板11之長向軸方向D1平行之方式,半導體晶片15沿著基板11之長向軸方向D1搭載於半導體晶片14A與14B上。半導體晶片15藉由DAF等接著劑而接著並固定於半導體晶片14A與14B上。半導體晶片15以其長向軸方向之兩端下表面由2個半導體晶片14之上表面支持之方式載置於2個半導體晶片14上,且藉由接著劑固定。如上所述,半導體晶片15設置於複數個(此處為2個)半導體晶片14A、14B上。
半導體晶片14A、14B分別經由複數條接合線14a、14b而連接於設置在基板11之上表面11a上之複數個電極。複數條接合線14a、14b於各半導體晶片14A、14B之一緣部(圖1之上側部分),與設置於基板11之上表面11a之複數個電極連接。
半導體晶片15經由複數條接合線15a而連接於設置在基板11上之複數個電極。複數條接合線15a於半導體晶片15之一緣部(圖1之下側部分),與設置於基板11之上表面11a之複數個電極連接。
進而,於間隔晶片13A與13C之間之基板11上,形成有樹脂阻力部21。樹脂阻力部21係對樹脂填充時之樹脂之流動產生阻力,使樹脂之流速減慢之部分。如圖2所示,樹脂阻力部21由複數條接合線21a形成。如圖2所示,各接合線21a具有圓弧形狀。
具體而言,各接合線21a藉由打線接合機而沿長向軸方向D1將上表面11a上之2點間連結,且各接合線21a形成為其中央部自上表面11a隔開之圓弧形狀。各接合線21a之中央部之高度低於上述間隔晶片13之高度h12。又,複數條接合線21a沿著短向軸方向D2以特定間隔形成於間隔晶片13A之側面13Ab與間隔晶片13C之側面13Cb之間。如上所述,樹脂阻力部21構成以自基板11上突出之方式設置於複數個間隔晶片13中之相鄰之2個間隔晶片13間(對應於空隙)之突出部。該突出部包含複數條接合線21a。
如上所述,將半導體晶片12搭載於基板11上,且於基板11上形成樹脂阻力部21之後,搭載複數個半導體晶片14A等。其後,藉由樹脂將複數個半導體晶片12、14、15及複數個間隔晶片13之周圍模塑。如圖3所示,基板11上之複數個半導體晶片之周圍由樹脂16填充。
樹脂之填充係藉由在抽真空之狀態下浸漬於具有特定之凹部形狀之模具中之已溶解之液體狀樹脂中而進行。溶解之樹脂覆蓋複數個半導體晶片12等而硬化。
如圖1及圖3所示之堆積有複數個半導體晶片12等之基板11以複數個半導體晶片12等相對於基板11成為重力方向之下方之方式浸漬於液體樹脂中。圖4係表示將搭載有複數個半導體晶片之基板11浸漬於液體樹脂中時之樹脂之浸入方向之圖。
箭頭A1表示間隔晶片13A與13B之間之樹脂之浸入方向。箭頭A2表示間隔晶片13C與13D之間之浸入方向。箭頭A3表示間隔晶片13A與13C之間之浸入方向。箭頭A4表示間隔晶片13B與13D之間之浸入方向。來自箭頭A1方向之樹脂通過間隔晶片13A之側面13Aa與間隔晶片13B之側面13Ba之間的開口OP1向半導體晶片12之側流入。再者,來自箭頭A1方向之樹脂亦自半導體晶片14A與14B間之間隙浸入。
來自箭頭A2方向之樹脂自形成於間隔晶片13C之側面13Ca與間隔晶片13D之側面13Da側之開口OP2流入。來自箭頭A2方向之樹脂通過由基板11之上表面11a、半導體晶片15之下表面15b、半導體晶片14A、14B之側面14Aa、14Ba、及間隔晶片13C、13D之側面13Ca、13Da包圍所形成之隧道狀之間隙而朝向半導體晶片12浸入。
來自箭頭A3方向之樹脂自形成於間隔晶片13C之側面13Ab與間隔晶片13C之側面13Cb側之開口OP3流入。來自箭頭A3方向之樹脂通過由基板11之上表面11a、半導體晶片14A之下表面14Ab、間隔晶片13A之側面13Ab、及間隔晶片13C之側面13Cb包圍所形成之隧道狀之間隙而朝向半導體晶片12浸入。
來自箭頭A4方向之樹脂自形成於間隔晶片13B之側面13Bb與間隔晶片13D之側面13Db側之開口OP4流入。來自箭頭A4方向之樹脂通過由基板11之上表面11a、半導體晶片14B之下表面14Bb、間隔晶片13B之側面13Bb、及間隔晶片13D之側面13Db包圍所形成之隧道狀之間隙而朝向半導體晶片12浸入。即,於半導體晶片12之周圍形成有複數個隧道狀之間隙,樹脂通過複數個隧道狀之間隙而朝向半導體晶片12浸入。
再者,將如圖3所示之堆積有複數個半導體晶片12、14、15之半導體晶片部分於一片較大之基板11上設置複數個,且將該較大之基板11以半導體晶片部分側於重力方向上成為下方之方式浸漬於液體樹脂中。
於樹脂硬化之後,將複數個焊球置於基板11之下表面11b之特定之複數個位置之狀態下,藉由對基板11進行加熱而使複數個焊球11c附著於基板11。其後,藉由切割以半導體晶片部分為單位切下,藉此形成如圖3所示之1個半導體裝置、即1個半導體封裝體。
本實施形態中,如上所述,於所堆積之複數個晶片部之最下段配置有較小之半導體晶片12,於該半導體晶片12上隔開間隙而配置有較大之半導體晶片14A、14B、15。
又,複數條接合線12b並非均等地設置於半導體晶片12之周圍。
(作用) 最下段之半導體晶片12係藉由樹脂通過其周圍之隧道狀之複數個間隙而由樹脂模塑,但樹脂必須將半導體晶片12之周圍及所有接合線12b之周圍無間隙地模塑。
再者,如圖1所示,於間隔晶片13A與13B之間之空間上不存在構件。由此,二點鏈線之細長之橢圓表示樹脂流入之開口OP1、OP2、OP3、OP4,但於開口OP1,樹脂亦自半導體晶片14A與14B之間之空間流入。
其次,對樹脂之流向進行說明。圖5係表示樹脂之流向之圖。再者,以下說明之圖5與圖6表示將設置於半導體晶片12周圍之複數條接合線12b相對於半導體晶片12之長向軸及端手軸對稱且均等地設置之例。
來自箭頭A1方向之樹脂碰撞至半導體晶片12之側面,其後分為2個方向。2個方向係沿著以虛線所示之流向fl1與fl2之2個方向。流向fl1係來自箭頭A1方向之樹脂中朝向間隔晶片13A之側面13Ab與間隔晶片13C之側面13Cb之間之樹脂的流向。流向fl2係來自箭頭A1方向之樹脂中朝向間隔晶片13B之側面13Bb與間隔晶片13D之側面13Db之間之樹脂的流向。
來自箭頭A2方向之樹脂碰撞至半導體晶片12之側面,其後分為2個方向。2個方向係沿著以虛線所示之流向fl3與fl4之2個方向。流向fl3係來自箭頭A2方向之樹脂中朝向間隔晶片13A之側面13Ab與間隔晶片13C之側面13Cb之間之樹脂的流向。流向fl4係來自箭頭A2方向之樹脂中朝向間隔晶片13B之側面13Bb與間隔晶片13D之側面13Db之間之樹脂的流向。
以虛線所示之流向fl5表示自箭頭A3方向朝向半導體晶片12之樹脂之流向。以虛線所示之流向fl6表示自箭頭A4方向朝向半導體晶片12之樹脂之流向。
再者,由於在半導體晶片12之上表面12a、與半導體晶片14A、14B之2個下表面之間具有間隙,故來自各箭頭方向之樹脂亦浸入至半導體晶片12之上表面12a與半導體晶片14A、14B之2個下表面14Ab、14Bb之間之間隙。
圖6係用以說明自各箭頭方向浸入時之樹脂之前端面之移動狀態的圖。圖6中,二點鏈線表示樹脂自各箭頭方向浸入時之樹脂之前端面。
樹脂自箭頭A1方向通過間隔晶片13A之側面13Aa與間隔晶片13B之側面13Ba間之空間之後,通過半導體晶片12與間隔晶片13A之側面13Ab間之空間。如圖6所示,沿著流向fl1之樹脂之前端面fs1朝與箭頭A3方向相反之方向移動。同樣地,樹脂自箭頭A2方向通過間隔晶片13C之側面13Ca與間隔晶片13D之側面13Da間之空間之後,通過半導體晶片12與間隔晶片13C之側面13Cb間之空間。如圖6所示,沿著流向fl3之樹脂之前端面fs3朝與箭頭A3方向相反之方向移動。樹脂之前端面fs5自箭頭A3方向沿著流向fl5移動。
圖6所示之沿著流向fl2之樹脂之前端面fs2、沿著流向fl4之樹脂之前端面fs4及沿著流向fl6之樹脂之前端面fs6亦如圖6所示分別如上述前端面fs1、fs3及fs5般移動。
各前端面最後於合流點相互接觸,其結果,於半導體裝置1內,由樹脂將半導體晶片12完全模塑。
然而,流向fl5、fl6較流向fl1、fl2、fl3、fl4快,故前端面fs1、fs3及fs5之合流點及前端面fs2、fs4及fs6之合流點有時會接近半導體晶片12之側面。
圖7至圖10係用以說明樹脂之各前端面之合流點之位置的圖。圖7與圖8係用以說明將複數條接合線12b如圖1、圖2及圖4所示般不均等地配置於半導體晶片12周圍之情形時之合流點之位置之例的圖。於圖7及圖8中,半導體晶片12之箭頭A4側之接合線12b之數量少於半導體晶片12之箭頭A3側之接合線12b之數量。
圖9與圖10係用以說明將複數條接合線12b如圖5及圖6所示般均等地配置於半導體晶片12周圍之情形時之合流點之位置之例的圖。各合流點係基於樹脂浸入之隧道狀之間隙長度等,根據實驗、模擬等而預測。
圖7中,樹脂阻力部21未設置於基板11上。圖7中,所預測之前端面fs1、fs3及fs5之合流點P1及所預測之前端面fs2、fs4及fs6之合流點P2以X記號表示。然而,於實際嘗試製造時,存在如下情形,即,樹脂因半導體晶片12之複數條接合線12b之影響,合流點成為以圓記號表示之RP1之位置而非P1之位置。該情形時,樹脂之移動受到複數條接合線12b阻礙,而有於合流點RP1附近形成微小間隙之虞。
其原因在於,半導體晶片12之長向軸方向之一側(圖7之左側)之接合線12b的數量多於半導體晶片12之長向軸方向之另一側(圖7之右側)之接合線12b的數量。因此,於半導體晶片12之長向軸方向之一側(圖7之左側)之接合線12b附近,合流點RP1移動,於該合流點RP1附近容易形成微小之間隙。
另一方面,半導體晶片12之長向軸方向之另一側(圖7之右側)之接合線12b的數量少於半導體晶片12之長向軸方向之一側(圖7之左側)之接合線12b的數量。因此,較多之半導體晶片12之長向軸方向之另一側(圖7之右側)之接合線12b附近並未成為前端面fs2、fs4及fs65之合流點,而是自接合線12b隔開之部位成為合流點P2。因此,於該合流點P2不易形成微小之間隙。
因此,圖8中,如圖1至圖4所示,於基板11上設置有樹脂阻力部21。樹脂阻力部21相對於合流點RP1設置於開口OP3側。樹脂阻力部21使來自箭頭A3方向之樹脂所流入之隧道狀間隙之尺寸減小。圖8中,所預測之前端面fs1、fs3及fs5之合流點QP1以三角記號表示。樹脂阻力部21使來自開口OP3之樹脂之流動減慢,交流點RP1自半導體晶片12之側面向基板11之外周緣側移動。由此,圖8之情形與圖7相比,前端面fs1、fs3及fs5之合流點自RP1向QP1移動。因此,於該合流點QP1不易形成微小之間隙。
即,於模塑時,藉由使來自箭頭A3方向之樹脂所流入之隧道狀間隙之尺寸減小,從而來自箭頭A3方向之樹脂之流入速度與來自箭頭A4方向之樹脂之流入速度一致。其結果,合流點自RP1移動至QP1,不易形成微小之間隙。
圖9之情形時,樹脂阻力部21未設置於基板11上。圖9中,所預測之前端面fs1、fs3及fs5之合流點P1及所預測之前端面fs2、fs4及fs6之合流點P2以X記號表示。然而,於實際嘗試製造時,存在如下情形,即,樹脂因半導體晶片12之複數條接合線12b之影響,第1合流點成為以圓記號表示之RP1之位置而非P1之位置,第2合流點成為以圓記號表示之RP2之位置而非P2之位置。該情形時,樹脂之流動受到複數條接合線12b阻礙,而有於合流點RP1及RP2之附近形成微小間隙之虞。
圖9與圖10中,半導體晶片12之長向軸方向之一側(圖7之左側)之接合線12b的數量與半導體晶片12之長向軸方向之另一側(圖7之右側)之接合線12b的數量相等。因此,如圖9所示,於半導體晶片12之長向軸方向之兩側(圖7之左側與右側)之接合線12b附近,合流點RP1、RP2移動,於該合流點RP1、RP2附近容易形成微小之間隙。
因此,圖10中,將2個樹脂阻力部21設置於基板11上。樹脂阻力部21相對於合流點RP1設置於開口OP3側,相對於合流點RP2設置於開口OP4側。於圖10之情形時,所預測之前端面fs1、fs3及fs5之合流點QP1、及所預測之前端面fs2、fs4及fs6之合流點QP2以三角記號表示。2個樹脂阻力部21使來自開口OP3與OP4之樹脂之流動減慢,交流點RP1、RP2自半導體晶片12之側面向基板11之外周緣側移動。由此,於圖10之情形時,與圖9相比,前端面fs1、fs3及fs5之合流點自RP1向QP1移動,前端面fs2、fs4及fs6之合流點自RP2向QP2移動。因此,於該合流點QP1與QP2不易形成微小之間隙。
即,於模塑時,藉由使來自箭頭A3方向及箭頭A4方向之樹脂所流入之2個隧道狀間隙之尺寸減小,而降低來自箭頭A3方向及箭頭A4方向之樹脂之流入速度。其結果,合流點自RP1移動至QP1,且自RP2移動至QP2,不易形成微小之間隙。
樹脂具有吸濕性。對於無法填充樹脂而於內部具有微小間隙之半導體裝置,於出貨後吸濕之情形時,有可能水分匯集於該微小之間隙,於水分因回焊之熱而氣化時損壞。因此,必須以封裝體內無間隙之方式製造。根據本實施形態,於半導體封裝體內不易形成微小之間隙,故可防止因吸濕後之回焊導致之破壞。
如上所述,根據上述實施形態,可提供一種不易形成因樹脂填充不足所導致之間隙之半導體裝置。
尤其是藉由樹脂阻力部21調整通過形成於下段之半導體晶片12周圍之隧道狀之複數個間隙的各樹脂流入時之阻力,使來自各開口之樹脂之流入速度一致、或減慢,藉此使樹脂之前端面之合流點之位置移動,從而防止產生微小之間隙。
再者,上述實施形態中,樹脂阻力部21由複數條接合線21a構成,但作為其變化例,亦可由阻焊劑或灌封樹脂構成。所謂灌封樹脂係指藉由灌封法而模塑之樹脂。
圖11係由阻焊劑構成樹脂阻力部之基板11之立體圖。圖11中,於上述圖2之樹脂阻力部21之位置,設置有自基板11之上表面11a突出之矩形之阻焊劑部22作為樹脂阻力部。即,阻焊劑部22構成包含設置於基板11上之阻焊劑之突出部。
於製造基板11時,可藉由將塗佈於基板11之上表面11a之阻焊劑局部加厚塗佈而形成樹脂阻力部。其結果,於模塑時,可使來自箭頭A3方向之樹脂所流入之隧道狀間隙之尺寸變小,從而使來自箭頭A3方向之樹脂之流入速度與來自箭頭A4方向之樹脂之流入速度一致。
圖12係由灌封樹脂構成樹脂阻力部之基板11之立體圖。圖12中,於上述圖2之樹脂阻力部21之位置,設置有於基板11之上表面11a灌封特定厚度之樹脂而成之灌封樹脂部23作為樹脂阻力部。即,灌封樹脂部23構成包含設置於基板11上之灌封樹脂之突出部。
進而,再者,樹脂阻力部亦可將複數條接合線21a、阻焊劑部22及灌封樹脂部23中之2個以上組合而構成。
將半導體晶片12搭載於基板11之上表面11a之後,使用灌封用之樹脂,於上表面11a上形成特定厚度之樹脂之隆起部分,藉此形成樹脂阻力部23。其結果,於模塑時,可使來自箭頭A3方向之樹脂所流入之隧道狀間隙之尺寸變小,從而使來自箭頭A3方向之樹脂之流入速度與來自箭頭A4方向之樹脂之流入速度一致。
如上所述,根據上述實施形態及各變化例,可提供一種不易形成因樹脂填充不足所導致之間隙之半導體裝置。
對本發明之若干實施形態進行了說明,但該等實施形態係作為示例而舉出者,並非意欲限定發明之範圍。該等新穎之實施形態能以其他各種形態實施,且可於不脫離發明主旨之範圍內進行各種省略、替換、變更。該等實施形態或其變化包含於發明之範圍或主旨中,並且包含於申請專利範圍所記載之發明及其均等之範圍內。
[相關申請] 本申請享有以日本專利申請2019-164909號(申請日:2019年9月10日)為基礎申請之優先權。本申請藉由參照該基礎申請而包含基礎申請之全部內容。
1:半導體裝置
11:基板
11a:上表面
11b:下表面
11c:焊球
12:半導體晶片
12a:上表面
12b:接合線
13:間隔晶片
13A:間隔晶片
13Aa:側面
13Ab:側面
13B:間隔晶片
13Ba:側面
13Bb:側面
13C:間隔晶片
13Ca:側面
13Cb:側面
13D:間隔晶片
13Da:側面
13Db:側面
14:半導體晶片
14a:接合線
14A:半導體晶片
14Aa:側面
14Ab:下表面
14b:接合線
14B:半導體晶片
14Ba:側面
14Bb:下表面
15:半導體晶片
15a:接合線
15b:下表面
16:樹脂
21:樹脂阻力部
21a:接合線
22:阻焊劑部
23:灌封樹脂部
A1:箭頭
A2:箭頭
A3:箭頭
A4:箭頭
D1:長向軸方向
D2:短向軸方向
fl1:流向
fl2:流向
fl3:流向
fl4:流向
fl5:流向
fl6:流向
fs1:前端面
fs2:前端面
fs3:前端面
fs4:前端面
fs5:前端面
fs6:前端面
h1:高度
h2:高度
h12:高度
OP1:開口
OP2:開口
OP3:開口
OP4:開口
P1:合流點
P2:合流點
QP1:合流點
QP2:合流點
RP1:合流點
RP2:合流點
圖1係實施形態之半導體裝置之俯視圖。 圖2係實施形態之半導體裝置之組裝圖。 圖3係實施形態之半導體裝置之前視圖。 圖4係表示實施形態之將搭載有複數個半導體晶片之基板浸漬於液體樹脂中時之樹脂之浸入方向之圖。 圖5係表示實施形態之樹脂之流向之圖。 圖6係用以說明實施形態之自各箭頭方向浸入時之樹脂之前端面之移動狀態的圖。 圖7係用以說明實施形態之樹脂之各前端面之合流點之位置的圖。 圖8係用以說明實施形態之樹脂之各前端面之合流點之位置的圖。 圖9係用以說明實施形態之樹脂之各前端面之合流點之位置的圖。 圖10係用以說明實施形態之樹脂之各前端面之合流點之位置的圖。 圖11係實施形態之變化例之由阻焊劑構成樹脂阻力部之基板之立體圖。 圖12係實施形態之變化例之由灌封樹脂構成樹脂阻力部之基板之立體圖。
11:基板
11a:上表面
12:半導體晶片
12a:上表面
12b:接合線
13A:間隔晶片
13Aa:側面
13Ab:側面
13B:間隔晶片
13Ba:側面
13Bb:側面
13C:間隔晶片
13Ca:側面
13Cb:側面
13D:間隔晶片
13Da:側面
13Db:側面
14A:半導體晶片
14Aa:側面
14Ab:下表面
14B:半導體晶片
14Ba:側面
14Bb:下表面
15:半導體晶片
15b:下表面
21:樹脂阻力部
21a:接合線
Claims (7)
- 一種半導體裝置,其具有: 基板; 第1半導體晶片,其搭載於上述基板面上,與上述基板電性連接; 複數個間隔件,其等在上述基板面上,於上述第1半導體晶片之周圍介隔空隙而相互隔開,且介隔第1非導電性材而設置; 第2半導體晶片,其介隔上述複數個間隔件自上述第1半導體晶片相對於上述基板面朝上方向隔開設置,且與上述基板電性連接;及 突出部,其於上述空隙之一部分具有自上述基板面上朝上方向突出之形狀。
- 如請求項1之半導體裝置,其進而於上述基板與上述第2半導體晶片之間具有樹脂。
- 如請求項2之半導體裝置,其具有第3半導體晶片,該第3半導體晶片係:相對於上述基板面,於第2半導體晶片之上述上方向介隔第2非導電性材設置且與上述基板電性連接。
- 如請求項1至3中任一項之半導體裝置,其中上述突出部包含複數條接合線。
- 如請求項1至3中任一項之半導體裝置,其中上述突出部包含設置於上述基板上之阻焊劑。
- 如請求項1至3中任一項之半導體裝置,其中上述突出部包含設置於上述基板上之灌封(potting)樹脂。
- 一種半導體裝置之製造方法,其具備以下步驟: 於基板面上形成第1半導體晶片; 在上述基板面上,於上述第1半導體晶片之周圍介隔空隙而相互隔開且介隔非導電性材而形成複數個間隔件; 於上述空隙之一部分,形成具有自上述基板面上朝上方向突出之形狀的突出部; 介隔上述複數個間隔件自上述第1半導體晶片相對於上述基板面朝上述上方向隔開地形成第2半導體晶片; 將上述第2半導體晶片與上述基板電性連接;及 將樹脂填充至上述基板與上述第2半導體晶片之間。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2019-164909 | 2019-09-10 | ||
JP2019164909A JP2021044362A (ja) | 2019-09-10 | 2019-09-10 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW202111823A true TW202111823A (zh) | 2021-03-16 |
TWI787587B TWI787587B (zh) | 2022-12-21 |
Family
ID=74851168
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW109106485A TWI787587B (zh) | 2019-09-10 | 2020-02-27 | 半導體裝置及其製造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US11309236B2 (zh) |
JP (1) | JP2021044362A (zh) |
CN (1) | CN112563213B (zh) |
TW (1) | TWI787587B (zh) |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0637211A (ja) | 1992-07-16 | 1994-02-10 | Fujitsu Ltd | 半導体パッケージと半導体装置及びその製造方法 |
KR20030018204A (ko) * | 2001-08-27 | 2003-03-06 | 삼성전자주식회사 | 스페이서를 갖는 멀티 칩 패키지 |
US20050062155A1 (en) * | 2003-09-24 | 2005-03-24 | Chung-Che Tsai | Window ball grid array semiconductor package and method for fabricating the same |
JP4406300B2 (ja) * | 2004-02-13 | 2010-01-27 | 株式会社東芝 | 半導体装置及びその製造方法 |
JP2006156797A (ja) * | 2004-11-30 | 2006-06-15 | Shinko Electric Ind Co Ltd | 半導体装置 |
US8586413B2 (en) * | 2005-05-04 | 2013-11-19 | Spansion Llc | Multi-chip module having a support structure and method of manufacture |
JP2008084263A (ja) * | 2006-09-29 | 2008-04-10 | Renesas Technology Corp | メモリカードおよびその製造方法 |
JP2008270597A (ja) * | 2007-04-23 | 2008-11-06 | Toshiba Corp | 半導体装置 |
JP5162226B2 (ja) | 2007-12-12 | 2013-03-13 | 新光電気工業株式会社 | 配線基板及び半導体装置 |
JP2009177061A (ja) | 2008-01-28 | 2009-08-06 | Nec Electronics Corp | 半導体装置及び半導体装置の製造方法 |
US8399305B2 (en) | 2010-09-20 | 2013-03-19 | Stats Chippac, Ltd. | Semiconductor device and method of forming dam material with openings around semiconductor die for mold underfill using dispenser and vacuum assist |
KR101774938B1 (ko) * | 2011-08-31 | 2017-09-06 | 삼성전자 주식회사 | 지지대를 갖는 반도체 패키지 및 그 형성 방법 |
JP2015176906A (ja) * | 2014-03-13 | 2015-10-05 | 株式会社東芝 | 半導体装置および半導体装置の製造方法 |
US9418974B2 (en) * | 2014-04-29 | 2016-08-16 | Micron Technology, Inc. | Stacked semiconductor die assemblies with support members and associated systems and methods |
JP2016225484A (ja) * | 2015-06-01 | 2016-12-28 | 株式会社東芝 | 半導体装置および半導体装置の製造方法 |
JP6586036B2 (ja) * | 2016-03-15 | 2019-10-02 | 東芝メモリ株式会社 | 半導体装置の製造方法 |
WO2018063343A1 (en) * | 2016-09-30 | 2018-04-05 | Intel Corporation | Systems, methods, and apparatuses for implementing bi-layer semiconducting oxides in source and drain for low access and contact resistance of thin film transistors |
JP2019054181A (ja) | 2017-09-19 | 2019-04-04 | 東芝メモリ株式会社 | 半導体パッケージ |
US10636667B2 (en) * | 2017-11-21 | 2020-04-28 | Taiwan Semiconductor Manufacturing Company Ltd. | Method for manufacturing semiconductor devices and structures thereof |
-
2019
- 2019-09-10 JP JP2019164909A patent/JP2021044362A/ja active Pending
-
2020
- 2020-02-27 TW TW109106485A patent/TWI787587B/zh active
- 2020-02-27 CN CN202010123291.9A patent/CN112563213B/zh active Active
- 2020-02-28 US US16/805,340 patent/US11309236B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US20210074619A1 (en) | 2021-03-11 |
TWI787587B (zh) | 2022-12-21 |
JP2021044362A (ja) | 2021-03-18 |
CN112563213A (zh) | 2021-03-26 |
CN112563213B (zh) | 2024-04-05 |
US11309236B2 (en) | 2022-04-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8710647B2 (en) | Semiconductor device having a first conductive member connecting a chip to a wiring board pad and a second conductive member connecting the wiring board pad to a land on an insulator covering the chip and the wiring board | |
US6333564B1 (en) | Surface mount type semiconductor device and method of producing the same having an interposing layer electrically connecting the semiconductor chip with protrusion electrodes | |
US7342309B2 (en) | Semiconductor device and fabrication method thereof | |
US20080042253A1 (en) | Stack type ball grid array package and method for manufacturing the same | |
US20070001296A1 (en) | Bump for overhang device | |
US20110074037A1 (en) | Semiconductor device | |
KR20070088258A (ko) | 다이 위에 적층된 역전된 패키지를 구비한 멀티 칩 패키지모듈 | |
KR20050028713A (ko) | 반도체 패키지 및 그 제조방법 | |
KR101440933B1 (ko) | 범프 기술을 이용하는 ic 패키지 시스템 | |
JP2015050384A (ja) | 半導体装置 | |
KR20110124065A (ko) | 적층형 반도체 패키지 | |
KR101352814B1 (ko) | 멀티 칩 스택 패키지 | |
JP2014204082A (ja) | 半導体装置の製造方法 | |
KR20150046117A (ko) | 장치 및 그 제조 방법 | |
US20200098670A1 (en) | Integrated electronic device having a dissipative package, in particular dual side cooling package | |
KR20150125988A (ko) | 반도체 장치 | |
TW202111823A (zh) | 半導體裝置及其製造方法 | |
TW201916317A (zh) | 半導體裝置 | |
JP4889359B2 (ja) | 電子装置 | |
US8039941B2 (en) | Circuit board, lead frame, semiconductor device, and method for fabricating the same | |
KR20080020137A (ko) | 역피라미드 형상의 적층 반도체 패키지 | |
KR100650769B1 (ko) | 적층형 패키지 | |
JP2007042709A (ja) | 樹脂封止金型及び樹脂封止型電子部品 | |
KR19990034731A (ko) | 리드 온 칩형 리드 프레임과 그를 이용한 패키지 | |
KR20080084075A (ko) | 적층 반도체 패키지 |