TW201814831A - 半導體元件及其製造方法 - Google Patents

半導體元件及其製造方法 Download PDF

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TW201814831A
TW201814831A TW106101278A TW106101278A TW201814831A TW 201814831 A TW201814831 A TW 201814831A TW 106101278 A TW106101278 A TW 106101278A TW 106101278 A TW106101278 A TW 106101278A TW 201814831 A TW201814831 A TW 201814831A
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Taiwan
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dielectric layer
metal
layer
silicon
nitrogen
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TW106101278A
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TWI605541B (zh
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吳正一
朱立軒
溫慶文
洪家駿
張振涼
李錦思
劉响
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台灣積體電路製造股份有限公司
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Publication of TW201814831A publication Critical patent/TW201814831A/zh

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Abstract

本揭露是關於半導體的製造方法。本方法包含接收具有暴露出第一金屬或該第一金屬之氧化物之第一表面的元件。本方法更包含沉積具有矽(Si)、氮(N)、碳(C)及氧(O)之介電層於第一表面之上，使得介電層接近第一表面之第一部分，相較於較第一部分更遠離第一表面之介電層之第二部分，具有較高的氮及碳濃度。本方法更再包含形成導電特徵於介電層之上。此種介電層會使導電特徵及第一金屬或第一金屬之氧化物之間互相電性絕緣。

Description

半導體元件及其製造方法
本揭露提供關於一種半導體元件及其製造方法。
在半導體製程中，介電層是一個重要的元件。舉例來說，在積體電路(Integrated Circuits,IC)中，會使用層間介電(Inter-Layer Dielectric,ILD)膜來嵌入各種積體電路的金屬通孔及金屬線路。以另外一個例子來說，在互補式金屬氧化物半導體(Complementary Metal Oxide-Semiconductor,CMOS)影像感測器中，如前側受照式(Front-Side Illuminated,FSI)影像感測器及後側(Back-Side Illuminated,BSI)受照式影像感測器，會將介電層使用於深溝槽絕緣的特徵上。再以另外一個例子來說，在三維(three-dimensional)積體電路封裝的技術中，會使用介電層做為直通矽晶穿通孔(Through-Silicon Vias,TSV)中的內襯層(lining layer)。
能夠電性絕緣不同的金屬特徵是介電層的主要功能之一。舉例而言，當製作高介電係數(high-k)金屬閘極電晶 體時，在金屬閘極上沉積氧化矽膜，並且在氧化矽膜上形成金屬通孔和金屬線路是一種基本的做法。氧化矽膜應該能夠將金屬閘極絕緣於金屬通孔和金屬線路。然而，有時會產生一個問題：在沉積氧化矽膜的過程當中，金屬閘極可能會和某些化學組成物產生反應，使得最後沉積而成的氧化矽膜中會混雜一些金屬化合物。這些金屬化合物可能會在隨後製成的金屬閘極及金屬通孔之間造成電路短路的現象。
綜上所述，為半導體製程提供一種改良式的介電層，以及製作此種介電層的方法，實有其必要性。
依據本揭露之一實施例提供了一個使用於半導體製程的方法。此一方法包含接收具有第一表面之一元件，其中這第一表面暴露了第一金屬或此第一金屬的氧化物。此一方法更包含沉積出具有矽(Si)、氮(N)、碳(C)及氧(O)的介電層於第一表面之上，使得此種介電層較接近第一表面的第一部分，較之同一介電層較第一部分遠離第一表面的第二部分，具有較高的氮及碳濃度。此一方法更再包含在介電層之上形成導電特徵。
依據本揭露之另一實施例提供了另一個使用於半導體製程的方法。此一方法包含了接收具有第一表面之一元件，其中這第一表面暴露了半導體材料或此元件的第一金屬。此一方法更包含利用低溫化學氣相沉積製程沉積出具有矽、氮、碳及氧的介電層於第一表面之上，以致於此種介電 層較接近第一表面的第一部分，較之同一介電層較遠離第一表面的第二部分，具有較高的氮及碳濃度。此一方法更再包含在介電層之上沉積出第二金屬。
依據本揭露之再另一實施例提供了一種半導體元件。此種半導體元件包含了具有第一表面之第一階層，其中這第一表面暴露了第一金屬或此第一金屬的氧化物。此種半導體元件更包含直接位於第一表面上的介電層，其中這介電層包含有矽、氮、碳及氧，並且其較接近第一表面的第一部分，較其較第一部分遠離第一表面的第二部分，具有較高的氮及碳濃度。此種半導體元件更再包含位於介電層之上的導電特徵。
10‧‧‧方法
12-18‧‧‧作業步驟
98‧‧‧半導體層
99‧‧‧閘極層
100‧‧‧元件
102‧‧‧基材
104‧‧‧源/汲特徵
105‧‧‧電晶體通道
106‧‧‧矽化物特徵
107‧‧‧界面層
108‧‧‧閘極堆疊
110‧‧‧閘極介電層
112‧‧‧功函數金屬層
114‧‧‧金屬填充層
120‧‧‧層間介電層
130‧‧‧表面
132‧‧‧介電層
134‧‧‧較低部
136‧‧‧較高部
140‧‧‧頂部表面
142‧‧‧阻障層
144‧‧‧源/汲觸點
150‧‧‧介電層
152‧‧‧金屬阻障層
154‧‧‧金屬通孔
156‧‧‧金屬線路
200‧‧‧圖表
202‧‧‧曲線
204‧‧‧曲線
206‧‧‧曲線
208‧‧‧曲線
210‧‧‧曲線
300‧‧‧影像感測器
302‧‧‧基材
304‧‧‧第一側
306‧‧‧第二側
308‧‧‧第一部分
309‧‧‧第二部分
310‧‧‧金屬線路
312‧‧‧感光元件
318‧‧‧深溝槽絕緣特徵
318a‧‧‧黏著層
318b‧‧‧負電荷聚積層
318c‧‧‧改良式介電層
318d‧‧‧金屬阻障層
318e‧‧‧金屬層
320‧‧‧導電特徵
322‧‧‧直通矽穿通孔
322a‧‧‧介電層
322b‧‧‧金屬阻障層
322c‧‧‧金屬層
324‧‧‧介電層
352‧‧‧基材
354‧‧‧第一側
356‧‧‧第二側
358‧‧‧第一部分
359‧‧‧第二部分
360‧‧‧金屬線路
配合相對應之圖式閱讀以下的詳細敘述，是最能幫助了解本揭露所提供之多個態樣的方法。但在此強調，根據業界中的標準做法，並不會按比例繪製圖式中的多個特徵。事實上，為能清楚表達以下的討論，可能依需求增加或減少圖式中多個特徵的尺寸。
第1圖為依據本揭露之多個實施例所繪製之製造具有改良式介電層之半導體元件之方法流程圖。
第2A圖至第2C圖為依據若干實施例所繪製出於第1圖所示方法之若干製造步驟過程中之半導體元件之剖面圖。
第2D圖為依據若干實施例所繪製出經第1圖所示方法之製造步驟後之改良式介電層之內容物。
第3A圖為依據本揭露之多個實施例所繪製之另一種具有改良式介電層之半導體元件。
第3B圖及第3C圖為第3A圖所示元件之特定特徵之局部放大圖。
以下的揭露提供了眾多用於實施本發明主題之不同特徵的多種不同實施例或範例。為能夠精簡本揭露，以下會使用有關於元件及配置方式的特定範例。當然，這些僅為範例，並非用以限制本發明。舉例而言，「第一特徵形成在第二特徵上方或之上」的結構於隨後的描述中，可能包含了將第一特徵與第二特徵以直接接觸的方式形成的實施例，而亦可能包含了在第一特徵與第二特徵之間可形成添加的特徵，使得第一特徵及第二特徵可不直接接觸。另外，本揭露可能於多個範例中重複使用相同的數標及/或字母。此重複之目的在於讓本揭露較為簡化及明晰，此一作法並非用以指示多個實施例及/或所討論之組態之間的關係。
此外，空間相對性術語，諸如「下方(beneath)」、「以下(below)」、「低於(lower)」、「上方(above)」、「高於(upper)」等等在本文中用於簡化描述，以描述如附圖中所圖示的一個元件或特徵結構與另一元件或特徵結構的關係。除了描繪圖式之方位外，空間相對性術語也包含元件在使用中或操作下之不同方位。此設備可以其他 方式定向(旋轉90度或處於其他方位上)，並且可相對應地針對所使用之空間相對性描述詞進行解釋。
本揭露大致上與半導體製程中的介電層相關，更具體來說，係為一種具有矽(Si)、氮(N)、碳(C)及氧(O)等成分的改良式介電層。在一實施例中，此種改良式介電層較低的部分相較於較高的部分而言，具有較高的氮及碳濃度。這樣的特性有助於位於介電層下面的金屬元件(如金屬閘極)與位於介電層上面的金屬元件(如金屬通孔)互相電性絕緣。舉例而言，此種改良式介電層可以利用低溫化學氣相沉積(Low-Temperature Chemical Vapor Deposition,LT CVD)或原子層沉積(atomic layer deposition)等方法來沉積而成。依據本揭露的若干實施例，在沉積此種改良式介電層時使用到的前驅物，不會與下方的金屬元件反應，或是僅會發生無關緊要性的反應。有時會發生於氧化矽介電層的金屬洩漏現象，其發生的可能性便會因而降低。有關此種改良式介電層以及其製作方法更加詳盡的說明，請見以下結合了第1圖至第3C圖所作的討論。
請參閱第1圖，其中顯示了依據本揭露之多個態樣，用以形成具有改良式介電層(如層間介電層)的半導體元件100的方法10，其中的改良式介電層位於一電晶體層及一金屬互連層(metal interconnect layer)之間。此一方法10僅為一範例，並非被用來限制本揭露自外於申請專利範圍中所明確引述的內容。在進行方法10之前、當中及之後，可以提供額外的操作，並且也可以針對本方法額外的實施例，對某 些經過說明的操作進行取代、消除或是重新佈署的動作。以下連同半導體元件100於製程中多個階段裡的剖面圖，第2A圖、第2B圖及第2C圖，來針對方法10做解說。此外，第2D圖繪示了此種改良式介電層於一實施例中的特性。半僅被提供做為例示的目的，而非用以對本揭露中的實施例中任何元件數量、任何區域數量或是任何結構組態或區域組態進行必要性的限制。另外，第2A圖、第2B圖及第2C圖所示之半導體元件100可能為積體電路製程，或是部分製程，當中的中間產物，其可能包含了靜態隨機存取記憶體(Static Random Access Memory,SRAM)及/或邏輯電路、被動元件(如電阻、電容及電感)，以及主動元件(如P型場效電晶體(P-type Field Effect Transistors,PFET)、N型場效電晶體(N-type Field Effect Transistors,NFET)、多閘極場效電晶體(如鰭式場效電晶體(Fin Field Effect Transistors,FinFET))、金屬氧化物半導體場效電晶體(Metal-Oxide Semiconductor Field Effect Transistors,MOSFET)、互補式金屬氧化物半導體電晶體、雙極電晶體、高電壓電晶體、高頻率電晶體、其他記憶體單元，以及前述這些元件的組合物)。
請參閱第1圖，在作業步驟12中，方法10接收(或被提供)元件100的前驅物。為了方便討論起見，在此亦將元件100的前驅物以元件100的名稱表示。元件100具有一個暴露金屬或金屬氧化物的表面。而改良式介電層會被沉積在這個表面上。
第2A圖繪示了元件100之一實施例。請參閱第2A圖，元件100包含了半導體層98及閘極層99。半導體層98包含了半導體基材102以及形成於其中的多個特徵。而閘極層99包含了矽化物特徵106、閘極堆疊108、閘極間隔物116以及形成於半導體基材102之上的多個介電層118及120。閘極層99之頂部表面130暴露了多個金屬元件及/或金屬氧化物。依據本揭露所提供的改良式介電層，會被沉積在表面130上。
請繼續參閱第2A圖，基材102包含了多個電晶體源極和汲極特徵104(下方稱源/汲特徵104)以及這些源/汲特徵104之間的多個電晶體通道105。閘極堆疊108被配置在電晶體通道105的上方。而閘極間隔物116被配置在每個閘極堆疊108的側壁上。多個介電層包含了位於閘極間隔物116之側壁上以及矽化物特徵106上的接觸蝕刻終止(Contact Etch Stop,CES)層118，以及位於該接觸蝕刻終止層118上的層間介電層120。以下會再進一步說明有關元件100的多項特徵(或組成元件)。
在本實施例中，基材102為矽基材。在其他可供選用的實施例中，基材102包含了其它基礎半導體(如鍺)、合成半導體(如碳化矽、砷化鎵、砷化銦及磷化銦)或合金半導體(矽鍺碳、磷砷化鎵及磷化銦鎵)。在實施例中，基材102可能包含了矽覆絕緣(Silicon on Insulator；SOI)基材，可受應力及/或加壓以提升效能，亦可包含磊晶區，包含了絕緣區，包含了摻雜區，及/或包含了其他適合的特徵及層。
源/汲特徵104可能包含了重摻雜源極/汲極(如位於左側的源/汲特徵104)、輕摻雜源極/汲極、上升區域、應力區域、磊晶增長區域(如位於右側的源/汲特徵104)及/或其他適合的特徵。可以利用蝕刻及磊晶增長、環形佈植、源極/汲極佈植、源極/汲極活化及/或其他適合的製程來形成源/汲特徵104。矽化物特徵106直接形成於源/汲特徵104之上，以降低源極/汲極接觸電阻，並可能包含了自我對準矽化物(self-aligned silicidation(salicidation))。舉例而言，可以利用包含下列步驟的製程來形成矽化物特徵106：沉積金屬層；退火金屬層，使金屬層能夠與源/極特徵104中的半導體材料產生反應以形成矽化物或鍺矽化物；以及接著移除未產生反應的金屬層。電晶體通道105被夾置於一對源/汲特徵104之間。當半導體元件100在運作狀態時，電晶體通道105會在各個源/汲特徵104之間導通電流。在一實施例中，基材102包含了用以形成多閘極場效電晶體(如鰭式場效電晶體)的鰭狀(fin-like)活性區域。再進一步以此一實施例來說，會將源/汲特徵104及電晶體通道105形成於該些鰭狀物之中或之上。
閘極堆疊108被配置於電晶體通道105之上。每一個閘極堆疊108都具有多階層式的結構。在一實施例中，閘極堆疊108包含了界面層107、閘極介電層110、功函數金屬層112、金屬填充層114以及其它階層(未被標示於圖式中)。其中的界面層107可能包含有介電質材料(如二氧化矽(SiO2)或氮氧化矽(SiON))，並且可以使用化學氧化、熱氧 化、原子層沉積、化學氣相沉積及/或其他適當的方法來形成之。閘極介電層110可以包含高介電係數介電層(如二氧化鉿(HfO2)、二氧化鋯(ZrO2)、氧化鑭(La2O3)、二氧化鈦(TiO2)、氧化釔(Y2O3)、鈦酸鍶(SrTiO3)、其他適當的金屬氧化物或是前述這些材料的組合物)，並且可以使用原子層沉積及/或其他適當的方法形成之。功函數金屬層112可能為P型或N型功函數層。P型功函數層所包含的金屬係選擇，但不被限制，自以下列示出的材料集合：氮化鈦(TiN)、氮化鉭(TaN)、釕(Ru)、鉬(Mo)、鎢(W)、鉑(Pt)或前述這些金屬的結合物。N型功函數層所包含的金屬係選擇，但不被限制，自以下列示出的材料集合：鈦(Ti)、鋁(Al)、碳化鉭(TaC)、碳氮化鉭(TaCN)、氮化鉭矽(TaSiN)或前述這些金屬的結合物。功函數金屬層112可能包含有多個階層，並可以使用化學氣相沉積、物理氣相沉積(Physical Vapor Deposition,PVD)及/或其他適當的製程來沉積形成之。金屬填充層114可能包含有鋁(Al)、鎢、鈷(Co)、銅(Cu)及/或其它適當的材料。可以利用化學氣相沉積、物理氣象沉積、電鍍及/或其它適當的製程來形成金屬填充層114。可以利用閘極優先(gate-first)製程或閘極後製(gate-last)製程(例如代換閘極(replacement gate)製程)來形成閘極堆疊108。
閘極間隔物116可能為配置在閘極堆疊108之側壁上的單層結構或是多層結構。在一實施例中，間隔物116包含了低介電係數(如小於3.9的介電係數)介電材料。在若干實施例中，閘極間隔物116包含了介電材料(如二氧化矽 (SiO2)、氮化矽(SiN)、氮氧化矽(SiON)、其它介電材料或前述這些材料的結合物)。在一範例中，會利用毯覆沉積(blanket depositing)出用以在元件100之上做為襯墊(liner)層的第一介電層(例如厚度一致的二氧化矽層)，以及用以在該第一介電層之上做為主D形(main D-shaped)間隔物的第二介電層(例如氮化矽層)，接著再透過非等向性蝕刻製程將部分介電層去除等步驟，形成閘極間隔物116。
接觸蝕刻終止層118可以包含介電材料(例如氮化矽(SiN)、二氧化矽(SiO2)、氮氧化矽(SiON)及/或其它材料)。可以利用電漿增強化學氣相沉積(Plasma Enhanced CVD；PECVD)製程及/或其它適當的沉積或氧化製程來形成接觸蝕刻終止層118。層間介電層120可以包含如以下所例示的材料：四乙氧基矽烷(tetraethylorthosilicate,TEOS)氧化物、未摻雜矽玻璃(un-doped silicate glass)氧化物或摻雜矽玻璃(doped silicate glass)氧化物(如硼磷矽玻璃(borophosphosilicate glass,BPSG)、氟矽酸鹽玻璃(fused silica glass,FSG)、磷矽玻璃(phosphosilicate glass,PSG)、硼矽(酸鹽)玻璃(boron doped silicon glass,BSG)及/或其它適當的介電質材料)。可以利用電漿增強化學氣相沉積製程、流動式化學氣相沉積(Flowable CVD,FCVD)製程或其它適當的沉積技術來沉積出層間介電層120。
在一實施例中，蝕刻終止層118會被配置於基材102之上覆蓋多個結構，而層間介電層120則會被配置於蝕刻終止層118之上。接下來，會利用化學機械研磨(Chemical Mechanical Polishing；CMP)製程來平坦化以及部分性地移除層間介電層120及蝕刻終止層118，以產生出包含有閘極堆疊108之頂部表面的平頂表面130。其中尤其會有一個以上的金屬元件及/或一個以上的金屬氧化物透過表面130被暴露而出。舉例而言，金屬填充層114會於表面130被暴露而出，並且其可能包含有鋁、鎢、鈷、銅及/或其他適當的金屬材料。
在若干製程中，會將氧化矽膜形成於表面139之上，並接著將金屬通孔及金屬線路形成於此一氧化矽膜之中或之上。舉例而言，可使用化學氣相沉積的方法，利用氧來減少甲矽烷(SiH4)以形成氧化矽膜。有個問題有時會伴隨著這樣的製程而產生：暴露於表面130的金屬元件可能會在沉積作業的過程中，與矽游離基產生反應，因而產生了矽金屬(Si-Metal)合金。這樣的反應可以由下列化學式解釋之：甲矽烷(SiH4)+氧(O2)+金屬→二氧化矽(SiO2)+矽酸(SiOH)+水(H2O)+矽金屬 (1)
矽金屬合金可能會隨機性地散佈在二氧化矽膜之中，並且可能包含有鋁矽合金、銅矽合金或其他金屬矽合金，端視在金屬填充層114中以及在表面130所暴露出的其它積體電路特徵中的金屬元件而定。當金屬通孔(如第2C圖中的金屬通孔154)被形成於此一氧化矽膜之上時，矽金屬合金會成為金屬通孔及閘極堆疊108間的一個洩漏路徑，導致發生電路短路或其它類型的缺陷。而本揭露利用在表面130上沉積出 改良式介電層132的方式，解決了此一問題。改良式介電層132含有矽、氮、碳及氧，並且不含矽金屬於其中。這部分會連同第2B圖及第2C圖一併進行討論。
在作業步驟14中，方法10(第1圖)將改良式介電層132沉積於表面130之上。請參閱第2B圖，在本實施例中，介電層132被直接地沉積在表面130上。在一實施例中，作業步驟14包含了利用氧及有機化合物做為前驅物的低溫化學氣相沉積製程，其中的有機化合物具有矽跟氮。如一範例所示，此一有機化合物為雙(叔丁基氨基)矽烷(bis(tertiarybutylamino)silane；BTBAS)。本揭露所提供之討論主題的發明人發現在低溫環境中，利用氧來減少雙(叔丁基氨基)矽烷並不會在介電層132中產生金屬矽合金。雖然這反應機制並不會影響本專利申請的範圍，但相信在若干實施例中，下列所示的反應，或許會在具有雙(叔丁基氨基)矽烷和氧的低溫化學氣相沉積製程中，產生明顯的作用：雙(叔丁基氨基)矽烷(BTBAS)+氧(O2)+金屬→二氧化矽(SiO2)+碳氮氧化矽(SiCON)+氮化碳化矽(SiCN)+碳化矽(SiC)+金屬 (2)
在上列反應(2)中，矽游離基不會與金屬產生反應，也不會因而產生矽金屬合金。進一步來說，介電層132具備了獨特的屬性，亦即介電層132，相較於其較高部136，在其較低部134含有較高濃度的氮及/或碳。按照這樣的實施方式，會 將較低部134參照為介電層132較為接近表面130的部分，而較高部136則會被參照為介電層132距離表面130較遠的另一部分。依據一實施例，在第2D圖中，透過測量介電層132中的氧、矽、氫、氮及碳內容物，進一步顯示出這樣的特性。
請參閱第2D圖，圖表200繪示了介電層132中，氧、矽、氫、氮及碳內容物的相對濃度，此一相對濃度係於介電層132的頂部表面140及表面130之間，沿著Z軸(第2B圖)做為介電層132深度的函數。其中，可以利用化學機械研磨製程所產出的平坦表面來提供成為頂部表面140。進一步來說，曲線202顯示出介電層132中的氮內容物、曲線204顯示出介電層132中的碳內容物、曲線206顯示出介電層132中的氧內容物、曲線208顯示出介電層132中的矽內容物以及曲線210顯示出介電層132中的氫內容物。如第2D圖所示，氮及碳內容物在較低部134中的濃度遠高於其在較高部136中的濃度。在本實施例中，氮及碳在較低部134中的濃度，較它們在較高部136中的濃度都高出至少10倍。氮及碳內容物可能會以碳氮氧化矽(SiCON)、氮化碳化矽(SiCN)及/或碳化矽(SiC)的形式呈現之。實際上，較低部134為碳化矽層及/或氮化碳化矽層。此一碳化矽層及/或氮化碳化矽層的功能為表面130上的保護層，能夠在低溫化學氣相沉積製程中，防止表面130的金屬元件與矽游離基產生反應。對比之下，氧化矽是介電層132之較上部136之中比重較為明顯的內容物。
在實施例中，會將作業步驟14中的低溫化學氣相沉積製程的執行溫度，設定在表面130中之金屬元件的熔點以下。舉例來說，這裡的低溫化學氣相沉積程序的執行溫度可能會在攝氏300至400度的範圍之間，亦即低於鋁的熔點(660.3℃)及銅的熔點(1,085℃)。當金屬填充層114使用了鈷或鎢(熔點分別為1,495℃及3,422℃)的時候，可能會為低溫化學氣相沉積程序調整一個較高的執行溫度。另外，在低溫化學氣相沉積製程中，或許可以使用其它具有矽及氮的有機化合物，來配合或是取代雙(叔丁基氨基)矽烷。舉例來說，低溫化學氣相沉積程序可以使用其它的氨基矽烷類，例如雙(二乙基氨基)矽烷((bis(diethylamino)silane)；BDEAS)及三(異丙基氨基)矽烷((tris(isopropylamino)silane)；TIPAS)。以另一範例而言，這有機化合物可以為雙(二乙基氨基)乙基矽烷((bis(diethylamino)ethylsilane)；BDEAES)或三(乙胺)矽烷((tris(ethylamino)silane)；TEAS)。這些有機化合物，雙(叔丁基氨基)矽烷、雙(二乙基氨基)矽烷、三(異丙基氨基)矽烷、雙(二乙基氨基)乙基矽烷及三(乙胺)矽烷，具有下列的化學式：
再更進一步來說，作業步驟14可以使用原子層沉積製程形成介電層132。此一原子層沉積製程使用了氧及具有矽跟氮的有機化合物做為前驅物，並且執行在低於表面130中金屬元件之熔點的溫度。這裡的有機化合物可能為雙(叔丁基氨基)矽烷、雙(二乙基氨基)矽烷、三(異丙基氨基)矽烷、雙(二乙基氨基)乙基矽烷、三(乙胺)矽烷以及其它適當的有機化合物。
在作業步驟16中，方法10(第1圖)在介電層132之上形成一個以上的導電特徵。請參閱第2C圖，這些導電特徵可能包含了穿透介電層132的源/汲觸點144或閘極觸點(未被繪示於圖式中)。此外，導電特徵包含了沉積在介電層132之上的金屬通孔154及金屬線路156。在這些實施例中，除了在有意使閘極觸點與閘極堆疊108接觸的情況之外，介電層132會使一個以上的導電特徵及閘極堆疊108互相電性絕緣。以下會針對有關作業步驟16的細節進行更多的討論。
在一實施例中，用以形成源/汲觸點144的製程，包含了形成穿過介電層132、層間介電層120及蝕刻終止層118之接觸孔，藉以暴露出矽化物特徵106。其中可以利用光刻製程以及蝕刻製程來形成此一接觸孔。接著，在接觸孔的側壁上沉積出阻障層142，並且在阻障層142之上的接觸孔裡沉積出源/汲觸點144。其中，可以使用金屬做為源/汲觸點144(如鋁、鎢、銅、鈷、這些金屬的組合物或其他適當的金屬)；並且可以利用適當的製程(如化學氣相沉積、物理氣相沉積、電鍍及/或其他適當的製程)來沉積出此一源/汲觸點 144。在沉積出了源/汲觸點144之後，可以實施化學研磨程序來進行元件100頂部表面的平坦化。在此一實施例中，介電層132協同阻障層142防止了源/汲觸點144及閘極堆疊108之金屬元件之間的金屬洩漏現象。
在一實施例中，用以形成金屬通孔154及金屬線路156的製程包含了在介電層132之上沉積出一個以上的介電層150。其中這一個以上的介電層150可以包含低介電係數介電材料、極低介電係數介電材料、無氮抗反射(nitrogen-free anti-reflective)材料以及其它適當的介電材料。接著，利用單鑲嵌(single damascene)或雙鑲嵌(dual damascene)製程形成嵌入介電層150的金屬通孔154及金屬線路156。在一範例中，利用了一個以上的光刻製程及蝕刻製程來形成介電層150中的通孔洞及線路溝槽。通孔洞及線路溝槽的側壁上會形成有金屬阻障層152(如氮化鈦)。接著，會將金屬(如鋁、鎢、銅、鈷、這些金屬的組合物或其他適當的金屬)沉積進入金屬阻障層152之上的通孔洞及線路溝槽中，藉以形成金屬通孔154和金屬線路156。位於線路溝槽外面的金屬材料，可以使用化學機械研磨製程加以移除之。介電層132有效地使金屬通孔154及閘極堆疊108的金屬填充層114互相絕緣。
在作業步驟18，方法10實施了更進一步的操作以完成元件100的製作。舉例而言，方法10可以在金屬線路156之上形成一互連結構的附加層。
第3A圖、第3B圖及第3C圖繪示了得助於本揭露所述之改良式介電層之半導體元件之另一實施例。請參閱第3A圖，其依據一實施例顯示了三維堆疊後側受照式(3D stacked BSI)影像感測器300。此一影像感測器300包含第一基材(如半導體晶圓)302以及第二基材352(如另一半導體晶圓)，其中透過了晶圓級的接合方法將此二基材接合在一起。基材302和352每個都可以包含基本半導體(如矽或鍺)、合成半導體(如碳化矽、砷化鍺、砷化銦及磷化銦)或合金半導體(矽鍺碳、磷砷化鎵及磷化銦鎵)。第一基材302具有第一側304及第二側306。第二基材352具有第一側354及第二側356。在此會使用金屬接合、直接接合、混合接合或其他接合方法將這兩個第一側304及354接合在一起。基材302包含了位於第一部分308中的金屬線路310。在第二部分309中，基材302包含了多個互相為深溝槽絕緣特徵318所隔絕的感光元件(如光二極體)312。影像感測器300更包含了配置在第二側306之上的顏色過濾器314及微鏡頭316。發生在影像感測器300之上發光事件會在感光元件312中形成影像。利用深溝槽絕緣特徵318所進行的隔絕行為增強了影像感測器300的感光度及解析度。在此種深溝槽絕緣特徵318中，可以使用本揭露之改良式介電層做為內襯層。
請再參閱第3A圖，基材352包含了在第一部分358中的金屬線路360。在第二部分359中，基材352亦可以包含感光元件(未被繪示於圖式中)，舉例而言，可使影像感測器300成為一雙置影像感測器。影像感測器300更包含有互 連著金屬線路310及360的導電特徵320及直通矽穿通孔(Through-Silicon Vias,TSVs)322，用以整合基材302及352的機能。在此種直通矽穿通孔322中，可以使用本揭露之改良式介電層做為內襯層。在另一實施例中，可以利用在第一側304及354間之介面，實施金屬直接接合的方式互連基材302及352，以取代直通矽穿通孔322的使用。
請參閱第3B圖，其繪示了影像感測器300的放大示意圖，從中可以看到依據一實施例，關於深溝槽絕緣特徵318更加詳細的視圖。深溝槽絕緣特徵318包含有多個嵌入基材302的階層。舉例而言，深溝槽絕緣特徵318包含了位於被蝕刻在基材302中的深溝槽之底部與側壁上的黏著層318a、位於黏著層318a之上之一個以上的負電荷聚積層318b、位於負電荷聚積層318b之上的改良式介電層、位於改良式介電層之上的金屬阻障層318d(如氮化鈦)，以及位於金屬阻障層318d之上的金屬層318e。在一實施例中，負電荷聚積層318b包含有金屬氧化物(如五氧化二磷(Ta2O5))，以及金屬層318e包含有鎢、鋁、銅、鈷或其他適當的金屬。進一步以此實施例來說，會利用以氧及具有矽和氮之有機化合物為前驅物的化學氣相沉積或原子層沉積的方式，將改良式介電層沉積於負電荷聚積層318b之上。其中的有機化合物可能為雙(叔丁基氨基)矽烷、雙(二乙基氨基)矽烷、三(異丙基氨基)矽烷、雙(二乙基氨基)乙基矽烷、三(乙胺)矽烷及其他適當的有機化合物當中之一。此一改良式介電層含有矽、氮、碳及氧，並且不含矽金屬合金於其中。另外，如先前針對介 電層132所進行的討論，改良式介電層在其較低部分相對於其較高部分具有較高濃度的氮及/或氧。一如本文所慣用，此一較低部分被參照為改良式介電層較為接近負電荷聚積層318b的部分，而較高部分被參照為改良式介電層另一個較為遠離負電荷聚積層318b的部分。介電層有效地使位於金屬阻障層318d和318e中的金屬元件及位於負電荷聚積層318b中的金屬元件互相絕緣。
請參照第3C圖，其繪示了影像感測器300的放大示意圖，從中可以看到依據一實施例，關於直通矽穿通孔322更加詳細的視圖。直通矽穿通孔322與嵌入介電層324之導電特徵320電性接觸。直通矽穿通孔322包含了嵌入基材302/352中的多個階層。舉例而言，直通矽穿通孔322包含了至少被沉積在被蝕刻於基材302及352中的溝槽之側壁上的第一介電層322a、位於第一介電層322a之上的金屬阻障層322b以及位於金屬阻障層322b之上的金屬層322c。在一實施例中，金屬阻障層322b可以含有氮化鈦。金屬層322c可以含有鎢、鋁、銅、鈷或其他適當的金屬。在一實施例中，影像感測器300包含了位於第一介電層322a及基材302/352之間的金屬氧化物層(未被繪示出)。第一介電層322a會為以氧及具有矽和氮之有機化合物為前驅物的化學氣相沉積或原子層沉積的方式所沉積而出。其中的有機化合物可能為雙(叔丁基氨基)矽烷、雙(二乙基氨基)矽烷、三(異丙基氨基)矽烷、雙(二乙基氨基)乙基矽烷、三(乙胺)矽烷及其他適當的有機化合物當中之一。此一改良式介電層322a含有矽、氮、碳及 氧，並且不含矽金屬合金於其中。另外，如先前針對介電層132及318c所進行的討論，第一介電層322a在其較低部分較其較高部分具有較高濃度的氮及/或氧。第一介電層322a有效地使位於金屬阻障層322b和金屬層322c中的金屬元件及基材302/352互相絕緣，亦使位於金屬阻障層322b和金屬層322c中的金屬元件及位於第一介電層322a之下的任何金屬氧化物層互相絕緣。
雖然非用以對本發明加諸限制，但本揭露中的多個實施例確實為半導體製程提供了多項價值。舉例而言，依據本揭露所實施的改良式介電層在金屬元件(如金屬閘極和金屬線路)之間提供了有效的電性絕緣效果。用以沉積出改良式介電層的方法不會產生矽金屬合金，所以能夠有效地防止金屬洩漏及金屬擴散的現象。當高介電值金屬閘極被泛用於先進半導體製程的時候，此種改良式介電層針對金屬閘極短路缺陷，及透過薄介電層所產生的金屬擴散等問題提供了有效的解決方案。並且在此所提供的方法能夠輕易地被整合入現有的半導體製程的流程中。
從一個範例態樣來說，本揭露導入了一個使用於半導體製程的方法。此一方法包含了接收具有第一表面之一元件，其中透過這第一表面，暴露了第一金屬或此第一金屬的氧化物。此一方法更包含沉積出具有矽、氮、碳及氧的介電層於第一表面之上，使得此種介電層較接近第一表面的第一部分，相對於同一介電層較第一部分遠離第一表面的第 二部分，具有較高的氮及碳濃度。此一方法更再包含在介電層之上形成導電特徵。
從另一個範例態樣來說，本揭露導入了一個使用於半導體製程的方法。此一方法包含了接收具有第一表面之一元件，其中透過這第一表面，暴露了半導體材料或此元件的第一金屬。此一方法更包含利用低溫化學氣相沉積製程沉積出具有矽、氮、碳及氧的介電層於第一表面之上，使得此種介電層較接近第一表面的第一部分，相對於同一介電層較遠離第一表面的第二部分，具有較高的氮及碳濃度。此一方法更再包含在介電層之上沉積出第二金屬。
再從另一個範例態樣來說，本揭露導入了一種半導體元件。此種半導體元件包含了具有第一表面之第一階層，其中透過這第一表面，暴露了第一金屬或此第一金屬的氧化物。此種半導體元件更包含直接位於第一表面上的介電層，其中這介電層包含有矽、氮、碳及氧，並且其較接近第一表面的第一部分，相對於其較第一部分遠離第一表面的第二部分，具有較高的氮及碳濃度。此種半導體元件更再包含位於介電層之上的導電特徵。
在此種半導體元件之一實施例中，介電層之第一部分中的碳濃度，相對於介電層之第二部分中的碳濃度，至少高出10倍。在此種半導體元件之另一實施例中，介電層之第一部分中的氮濃度，相對於介電層之第二部分中的氮濃度，至少高出10倍。在此種半導體元件之再另一實施例中， 介電層之第一部分中的碳及氮濃度，相對於介電層之第二部分中的碳及氮濃度，皆至少高出10倍。
前文描述了若干實施例之特徵，使得本技術領域具有通常知識者可更加理解本發明之各種態樣。本技術領域具有通常知識者應當了解，其可輕易使用本揭露做為基礎來設計或修改其它製程及結構，以執行同於本揭露所介紹之實施例的作用及/或實現同於本揭露所介紹之實施例的優點。本技術領域具有通常知識者亦應理解，此類等效結構並未脫離本揭露之精神及範疇，且他們可以在不脫離本揭露之精神及範疇的情況下，於此進行各種變化、替代及修改。

Claims (10)

  1. 一種半導體元件之製造方法，包含：接收一元件，其中該元件具有暴露出一第一金屬或該第一金屬之一氧化物之一第一表面；沉積具有矽(Si)、氮(N)、碳(C)及氧(O)之一介電層於該第一表面之上，使得該介電層接近該第一表面之一第一部分，相對於較該第一部分更遠離該第一表面之該介電層之一第二部分，具有較高的氮及碳濃度；以及形成一導電特徵於該介電層之上。
  2. 如請求項1所述之方法，其中沉積該介電層之步驟，係利用以氧及含有矽和氮之一有機化合物做為前驅物之一低溫化學氣相沉積(Low-Temperature Chemical Vapor Deposition,LTCVD)製程執行之。
  3. 如請求項2所述之方法，其中該有機化合物為雙(叔丁基氨基)矽烷(bis(tertiarybutylamino)silane；BTBAS)、雙(二乙基氨基)矽烷((bis(diethylamino)silane)；BDEAS)、三(異丙基氨基)矽烷((tris(isopropylamino)silane)；TIPAS)，或雙(二乙基氨基)乙基矽烷((bis(diethylamino)ethylsilane)；BDEAES)。
  4. 如請求項2所述之方法，其中該低溫化學氣相沉積製程係執行於攝氏300度及攝氏400度所構成之溫度範圍中。
  5. 如請求項1所述之方法，其中該第一金屬為鋁(Al)或銅(Cu)。
  6. 如請求項1所述之方法，其中該第一表面係一溝槽之底部及側壁，且該介電層部分地填充了該溝槽，該導電特徵亦被沉積於該溝槽中。
  7. 一種半導體元件之製造方法，包含：接收一元件，其中該元件具有暴露出一半導體材料或該元件之一第一金屬之一第一表面；沉積具有矽(Si)、氮(N)、碳(C)及氧(O)之一介電層於該第一表面之上，其中係利用一低溫化學氣相沉積(Low-Temperature Chemical Vapor Deposition,LTCVD)製程沉積之，使得該介電層接近該第一表面之一第一部分，相對於遠離該第一表面之該介電層之一第二部分，具有較高的氮及碳濃度；以及沉積一第二金屬於該介電層之上。
  8. 一半導體元件，包含：一第一階層，具有暴露出一第一金屬或該第一金屬之一氧化物之一第一表面；一介電層，直接位於該第一表面之上，其中該介電層含有矽(Si)、氮(N)、碳(C)及氧(O)，且該介電層接近該第一表 面之一第一部分，相對於較該第一部分更遠離該第一表面之該介電層之一第二部分，具有較高的氮及碳濃度；以及一導電特徵，位於該介電層之上。
  9. 如請求項8所述之半導體元件，其中該介電層之該第一部分所含有之碳濃度，相較於該介電層之該第二部分所含有之碳濃度，至少高出10倍。
  10. 如請求項8所述之半導體元件，其中該介電層之該第一部分所含有之氮濃度，相較於該介電層之該第二部分所含有之氮濃度，至少高出10倍。
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US20180096936A1 (en) 2018-04-05
KR20180036549A (ko) 2018-04-09
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US11901295B2 (en) 2024-02-13
CN107887254A (zh) 2018-04-06
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US10658296B2 (en) 2020-05-19
US11296027B2 (en) 2022-04-05
US11152306B2 (en) 2021-10-19
TWI605541B (zh) 2017-11-11
US20200083168A1 (en) 2020-03-12
US20180337128A1 (en) 2018-11-22
CN107887254B (zh) 2021-08-03

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