CN107887254B - 用于半导体制造的改进的介电膜 - Google Patents
用于半导体制造的改进的介电膜 Download PDFInfo
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- CN107887254B CN107887254B CN201710624915.3A CN201710624915A CN107887254B CN 107887254 B CN107887254 B CN 107887254B CN 201710624915 A CN201710624915 A CN 201710624915A CN 107887254 B CN107887254 B CN 107887254B
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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Abstract
本发明实施例公开了一种用于半导体制造的方法。该方法包括接收具有第一表面的器件,通过该表面暴露第一金属或第一金属的氧化物。该方法还包括在第一表面上方沉积具有Si、N、C和O的介电膜,从而使得介电膜在靠近第一表面的介电膜的第一部分中具有比在介电膜的第二部分中更高的N和C浓度,该介电膜的第二部分比第一部分进一步远离第一表面。该方法还包括在介电膜上方形成导电部件。介电膜将导电部件与第一金属或第一金属的氧化物电绝缘。本发明实施例涉及用于半导体制造的改进的介电膜。
Description
技术领域
本发明实施例涉及用于半导体制造的改进的介电膜。
背景技术
介电膜是半导体制造中的必要元件。例如,集成电路(IC)中使用层间介电(ILD)膜,从而用于嵌入IC的各个金属通孔和金属引线。又例如,在诸如FSI(前照式)图像传感器和BSI(背照式)图像传感器的CMOS图像传感器中的深沟槽隔离部件中使用介电膜。又例如,介电膜用作3D(三维)IC封装中的硅通孔(TSV)中的衬垫层。
介电膜的一个主要功能是电绝缘不同的金属部件。例如,当制造具有高k金属栅极晶体管的IC时,典型的做法是在金属栅极上方沉积氧化硅膜(介电膜),并在氧化硅膜上方形成金属通孔和金属引线。假设氧化硅膜将金属栅极与金属通孔和金属引线绝缘。然而,有时会出现一个问题:在沉积氧化硅膜期间,金属栅极可能与特定的化学品反应,导致一些金属化合物混入最终沉积的氧化硅膜中。这些金属化合物可导致金属栅极和后续制造的金属通孔之间的电路短路。
因此,期望一种用于半导体制造的改进的介电膜及其制造方法。
发明内容
根据本发明的一些实施例,提供了一种用于半导体制造的方法,包括:接收具有第一表面的器件,通过所述第一表面暴露第一金属或所述第一金属的氧化物;在所述第一表面上方沉积具有Si、N、C和O的介电膜,从而使得所述介电膜在靠近所述第一表面的所述介电膜的第一部分中具有比在所述介电膜的第二部分中更高的N和C浓度,所述介电膜的第二部分比所述第一部分更远离所述第一表面;以及在所述介电膜上方形成导电部件。
根据本发明的另一些实施例,还提供了一种用于半导体制造的方法,包括:接收具有第一表面的器件,通过所述第一表面暴露半导体材料或所述器件的第一金属;通过低温化学汽相沉积(LT CVD)工艺在所述第一表面上方沉积具有Si、N、C和O的介电膜,从而使得所述介电膜在靠近所述第一表面的所述介电膜的第一部分中具有比在远离所述第一表面的所述介电膜的第二部分中更高的N和C浓度;以及在所述介电膜上方沉积第二金属。
根据本发明的又一个实施例,还提供了一种半导体器件,包括:第一层,具有第一表面,通过所述第一表面暴露第一金属或所述第一金属的氧化物;介电膜,直接位于所述第一表面上方,其中,所述介电膜包括Si、N、C和O,并且在靠近所述第一表面的所述介电膜的第一部分中具有比在所述介电膜的第二部分中的更高的C和N浓度,所述介电膜的第二部分比所述第一部分更远离所述第一表面;以及导电部件,位于所述介电膜上方。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳地理解本发明的各个方面。应该注意,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各种部件的尺寸可以被任意增大或减小。
图1是根据本发明的一个或多个实施例的制造具有改进的介电膜的半导体器件的方法的流程图。
图2A、图2B和图2C示出根据一些实施例的在图1的方法的一些制造阶段期间的半导体器件的截面图。
图2D示出根据一些实施例的在图1的方法的制造步骤之后改进的介电膜的成分。
图3A是根据本发明的一个或多个实施例的具有改进的介电膜的另一半导体器件。
图3B和图3C是图3A的器件的特定部件的放大的局部图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,在以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且,为了便于描述,在此可以使用诸如“在…下方”、“在…下面”、“下部”、“在…之上”、“上部”等空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上),并且在此使用的空间相对描述符可以同样地作出相应的解释。
本发明一般涉及用于半导体制造的介电膜,并且更具体地涉及具有Si、N、C和O成分的改进的介电膜。在一个实施例中,改进的介电膜在其下部中具有比在其上部中更高的N和C浓度。该性能有助于将位于介电膜下方的金属元件(例如,金属栅极)与位于介电膜之上的金属元件(例如,金属通孔)电绝缘。可以使用例如低温化学汽相沉积(LT CVD)或原子层沉积来沉积改进的介电膜。根据所提供的主题的一些实施例,用于沉积改进的介电膜的前体不(或不显著地)与下面的金属元件反应。因此,它减少了有时在氧化硅介电膜中看到的金属泄漏的可能性。下文中结合图1-图3C讨论改进的介电膜及其制造方法的更详细的描述。
参考图1,其中示出根据本发明的各个方面的形成具有改进的介电层作为晶体管层和金属互连层之间的层间介电(ILD)膜的半导体器件100的方法10的流程图。方法10仅为实例,并且不旨在限制本发明超出权利要求中明确列举的那些。可在方法10之前、期间和之后提供额外的操作,并且对于方法的额外的实施例,可替换、消除或重新定位所描述的一些操作。下文中结合图2A、图2B和图2C描述方法10,图2A、图2B和图2C是制造工艺的各个阶段中的半导体器件100的截面图。此外,图2D示出实施例中的改进的介电膜的特性。提供半导体器件100以用于说明目的,并且没有必要将本发明的实施例限制到器件的任何数量、区域的任何数量或者结构或区域的任何配置。此外,图2A、图2B和图2C所示的半导体器件100可以是IC或其部分的处理期间制造的中间器件,其可包括静态随机存取存储器(SRAM)和/或逻辑电路、诸如电阻器、电容器和电感器的无源组件以及诸如p-型场效应晶体管(PFET)、n-型FET(NFET)、诸如FinFET的多栅极FET、金属氧化物半导体场效应晶体管(MOSFET)、互补金属氧化物半导体(CMOS)晶体管、双极晶体管、高压晶体管、高频率晶体管的有源组件、其他存储器单元以及它们的组合。
参考图1,在操作12处,方法10接收(或提供有)器件100的前体。为了便于讨论,器件100的前体还称为器件100。器件100具有通过其暴露金属或金属氧化物的表面。在表面上沉积改进的介电膜。
在图2A中示出器件100的实施例。参考图2A,器件100包括半导体层98和栅极层99。半导体层98包括半导体衬底102和形成在其中的各个部件。栅极层99包括形成在半导体衬底102上的硅化物部件106、栅极堆叠件108、栅极间隔件116和各个介电层118和120。通过栅极层99的顶面130暴露各个金属元件和/或金属氧化物。根据本发明的改进的介电膜将沉积在表面130上。
仍然参考图2A,衬底102包括各个晶体管源极和漏极(S/D)部件104和位于S/D部件104之间的晶体管沟道105。在晶体管沟道105上方设置栅极堆叠件108。在每个栅极堆叠件108的侧壁上设置栅极间隔件116。各个介电层包括位于栅极间隔件116的侧壁上且位于硅化物部件106上的接触蚀刻停止(CES)层118,和位于CES层118上方的层间介电(ILD)层120。下文中进一步描述器件100的各个部件(或组件)。
在本实施例中衬底102是硅衬底。在可选实施例中,衬底102包括诸如锗的其他元素半导体;诸如碳化硅、砷化镓、砷化铟和磷化铟的化合物半导体;或诸如碳化硅锗、磷化镓砷以及磷铟化镓的合金半导体。在实施例中,衬底102可包括为增强性能而被应变和/或施加压力的绝缘体上硅(SOI)衬底,其包括外延区,包括隔离区,包括掺杂区,和/或包括其他合适的部件和层。
S/D部件104可以包括重掺杂的S/D(HDD)(诸如位于左侧上的S/D部件104)、轻掺杂的S/D(LDD)、凸起区域、应变区域、外延生长区域(诸如位于右侧上的两个S/D部件104)和/或其他合适的部件。可以通过蚀刻和外延生长、光晕注入、S/D注入、S/D激活和/或其他合适的工艺形成S/D部件104。硅化物部件106直接形成在S/D部件104上方,用于减小S/D接触电阻,并且可以包括自对准硅化物(硅化物)。例如,硅化物部件106可以通过以下工艺形成:包括沉积金属层,退火该金属层,从而使得金属层能够与S/D部件104中的半导体材料反应以形成硅化物或锗硅化物,然后去除未反应的金属层。晶体管沟道105夹在一对S/D部件104之间。当使用半导体器件100时,晶体管沟道105在相应的S/D部件104之间传导电流。在实施例中,衬底102包括用于形成诸如FinFET的多栅极FET的鳍状有源区。对于进一步的实施例,在鳍中或鳍上形成S/D部件104和晶体管沟道105。
在晶体管沟道105上方设置栅极堆叠件108。每个栅极堆叠件108是多层结构。在实施例中,栅极堆叠件108包括界面层107、栅极介电层110、功函金属层112、金属填充层114和其他层(未标记)。界面层107可以包括诸如氧化硅(SiO2)或氮氧化硅(SiON)的介电材料,并且可以通过化学氧化、热氧化、原子层沉积(ALD)、化学汽相沉积(CVD)和/或其他合适的方法形成。栅极介电层110可以包括诸如氧化铪(HfO2)、氧化锆(ZrO2)、氧化镧(La2O3)、氧化钛(TiO2)、氧化钇(Y2O3)、钛酸锶(SrTiO3)、其他合适的金属氧化物或它们的组合的高k介电层;并且可以通过ALD和/或其他合适的方法形成。功函金属层112可以是p型或n型功函数层。p型功函数层包括选自但不限于氮化钛(TiN)、氮化钽(TaN)、钌(Ru)、钼(Mo)、钨(W)、铂(Pt)或它们的组合的组的金属。n型功函数层包括选自但不限于钛(Ti)、铝(Al)、碳化钽(TaC)、碳氮化钽(TaCN)、氮化钽硅(TaSiN)、或它们的组合的组的金属。功函金属层112可以包括多个层并且可以通过CVD、PVD和/或其他合适的工艺沉积。金属填充层114可以包括铝(Al)、钨(W)、钴(Co)、铜(Cu)和/或其他合适的材料。可以通过CVD、PVD、镀和/或其他合适的工艺形成金属填充层114。可以在先栅极工艺或后栅极工艺(即,替换栅极工艺)中形成栅极堆叠件108。
栅极间隔件116可以是设置在栅极堆叠件108的侧壁上的单层或多层结构。在实施例中,间隔件116包括低k(例如,k<3.9)介电材料。在一些实施例中,栅极间隔件116包括诸如氧化硅(SiO2)、氮化硅(SiN)、氮氧化硅(SiON)、其他介电材料或它们的组合的介电材料。在实例中,栅极间隔件116的形成方法如下:通过在器件100上方毯式沉积作为衬垫层的第一介电层(例如,具有均匀厚度的SiO2层)以及在第一介电层上方毯式沉积作为主D形间隔件的第二介电层(例如,SiN层),并且然后,各向异性蚀刻以去除介电层的部分以形成栅极间隔件116。
CES层118可以包括诸如氮化硅(SiN)、氧化硅(SiO2)、氮氧化硅(SiON)和/或其他材料的介电材料。可以通过等离子体增强CVD(PECVD)工艺和/或其他合适的沉积或氧化工艺来形成CES层118。ILD层120可以包括诸如原硅酸四乙酯(TEOS)氧化物,未掺杂的硅酸盐玻璃,或诸如硼磷硅硅酸盐玻璃(BPSG)、熔融石英玻璃(FSG)、磷硅酸盐玻璃(PSG)、硼掺杂的硅玻璃(BSG)的掺杂的氧化硅的材料,和/或其他合适的介电材料。可以通过PECVD工艺、可流动CVD(FCVD)工艺或其他合适的沉积技术来沉积ILD层120。
在实施例中,CES层118沉积在衬底102上方,以覆盖衬底102上的各个结构,并且在CES层118上方沉积ILD层120。后续地,实施化学机械抛光(CMP)工艺以平坦化和部分地去除ILD层120和CES层118,产生包括栅极堆叠件108的顶面的平坦的顶面130。特别地,通过表面130暴露一种或多种金属元件和/或一种或多种金属氧化物。例如,金属填充层114在表面130处暴露,并且可以包括Al、W、Co、Cu和/或其他合适的金属材料。
在一些制造工艺中,在表面130上方形成氧化硅膜,并且在氧化硅膜中或上后续形成金属通孔和金属引线。例如,可以通过使用化学汽相沉积(CVD)法用氧还原硅烷(SiH4)来形成氧化硅膜。这种制造工艺有时会出现问题-在表面130处暴露的金属元件在沉积期间可能与硅自由基反应,从而形成Si-金属合金。这种反应可以解释如下:
SiH4+O2+金属→SiO2+SiOH+H2O+Si-金属 (1)
Si-金属合金可以随机分布在SiO2膜中,并且可以包括铝硅合金、铜硅合金或其他金属硅合金,这取决于金属填充层114中以及暴露在表面130处的其他IC部件中的金属元件。当在该氧化硅膜上方形成金属通孔(诸如图2C上的金属通孔154)时,Si-金属合金将成为金属通孔和金属栅极108之间的泄漏路径,导致电路短路或缺陷的其他类型。所提供的主题通过在表面130上方沉积改进的介电膜132来解决这种问题。改进的介电膜132含Si、N、C和O并且其中不含Si-金属合金。这将结合图2B和图2D进行讨论。
在操作14处,方法10(图1)在表面130上方沉积改进的介电膜132。参考图2B,在本实施例中,在表面130上直接沉积介电膜132。在实施例中,操作14包括使用氧和有机化合物作为前体的低温化学汽相沉积(LT CVD)工艺,该有机化合物具有硅和氮。作为一个实例,有机化合物是BTBAS(双(叔丁基氨基)硅烷)。所提供的主题的发明人已经发现,在低温环境中用氧还原BTBAS不会在介电膜132中产生金属硅合金。虽然反应的机理不影响权利要求的范围,可以认为在一些实施例中,以下反应在利用BTBAS和氧的LT CVD工艺中可以是主要的:
BTBAS+O2+金属→SiO2+SiCON+SiCN+SiC+金属 (2)
在上述反应(2)中,Si自由基不与金属反应。因此,不产生Si-金属合金。此外,介电膜132具有独特的性质,在介电膜132的下部134处包含比在上部136中更高的N和/或C浓度。如本文所使用的,下部134是指介电膜132的靠近表面130的部分,而上部136是指介电膜132的远离表面130的另一部分。根据实施例,该特性使用介电膜132中O、Si、H、N和C的成分的测量在图2D中进一步示出。
参考图2D,图200示出介电膜132中的O、Si、H、N和C成分的相对浓度,作为介电膜132的顶面140与表面130之间的的介电膜132沿着Z轴(图2B)的深度的函数。通过CMP工艺顶面140可以提供为平坦的表面。特别地,曲线202示出介电膜132中的N含量,曲线204示出了C含量,曲线206示出了O含量,曲线208示出了Si含量,曲线210示出了H含量。如图2D所示,N和C成分的浓度在下部134中比在上部136中高得多。在本实施例中,N和C的每个浓度在下部134中比在上部136中高至少10倍。N和C含量可以以SiCON、SiCN和/或SiC的形式存在。有效地,下部134是碳化硅和/或碳氮化硅的层。该碳化硅和/或碳氮化硅层用作表面130上方的保护层,以防止表面130的金属元件在LT CVD工艺期间与硅自由基反应。相反,在介电膜132的上部136中氧化硅是主要成分。
在实施例中,在低于表面130中的金属元件的熔点的温度处实施操作14的LT CVD工艺。例如,可以在低于铝(660.3℃)和铜(1085℃)的熔点的从300至400摄氏度的温度处实施LT CVD工艺。当金属填充层114使用Co或W(其熔点分别为1495℃和3422℃)时,可以使用更高的温度用于CVD工艺。此外,除了BTBAS之外或替代BTBAS,LT CVD工艺可以使用具有硅和氮的其他有机化合物。例如,LT CVD工艺可以使用诸如BDEAS(双(二乙基氨基)硅烷)和TIPAS(三(异丙基氨基)硅烷)的其他氨基硅烷。作为另一实例,有机化合物可以是BDEAES(双(二乙基氨基)乙基硅烷)或TEAS(三(乙基氨基)硅烷)。有机化合物BTBAS、BDEAS、TIPAS、BDEAES和TEAS具有以下结构化学式:
此外,操作14可以使用原子层沉积(ALD)工艺来形成介电膜132。ALD工艺使用氧和具有硅与氮的有机化合物作为前体,并且在低于表面130中的金属元件的熔点的温度处实施。有机化合物可以是BTBAS、BDEAS、TIPAS、BDEAES、TEAS和其他合适的有机化合物中的一种。
在操作16处,方法10(图1)在介电膜132上方形成一个或多个导电部件。参考图2C,导电部件可以包括穿透介电膜132的S/D接触件144或栅极接触件(未示出)。此外,导电部件包括沉积在介电膜132上方的金属通孔154和金属引线156。在这些实施例中,除了当栅极接触件刻意地连接至金属栅极108时,介电膜132将一个或多个导电部件与金属栅极108电绝缘。下文中讨论操作16的更多细节。
在实施例中,形成S/D接触件144的工艺包括形成穿过介电膜132、ILD层120和CES层118的接触孔,从而暴露硅化物部件106。可以使用光刻工艺和蚀刻工艺形成接触孔。后续地,在接触孔的侧壁上沉积阻挡层142,并且在阻挡层142上方的接触孔中沉积S/D接触件144。S/D接触件144可以使用金属,诸如铝(Al)、钨(W)、铜(Cu)、钴(Co)、它们的组合或其他合适的金属;并且可以使用合适的工艺来沉积,诸如CVD、PVD、镀和/或其他合适的工艺。可以在沉积S/D接触件144之后实施CMP工艺以平坦化器件100的顶面。在本实施例中,介电膜132和阻挡层142共同防止S/D接触件144和金属栅极108的金属元件之间的金属泄漏。
在实施例中,形成金属通孔154和金属引线156的工艺包括在介电膜132上方沉积一个或多个介电层150。一个或多个介电层150可以包括低k介电材料、极低k介电材料、无氮抗反射材料和其他合适的介电材料。然后,单镶嵌或双镶嵌工艺用于形成嵌入在介电层150中的金属通孔154和金属引线156。在一个实例中,通过一个或多个光刻工艺和蚀刻工艺在介电层150中形成通孔和引线沟槽。在通孔和引线沟槽的侧壁上形成诸如TiN的金属阻挡层152。后续地,在通孔和阻挡层152上方的引线沟槽中沉积诸如铝(Al)、钨(W)、铜(Cu)、钴(Co)、它们的组合或其他合适的金属的金属,因此形成金属通孔154和金属引线156。可以实施CMP工艺以去除位于引线沟槽外侧的金属材料。介电膜132有效地使金属通孔154与金属栅极108的金属填充层114绝缘。
在操作18处,方法10实施进一步的操作以完成器件100的制造。例如,方法10可以在金属引线156上方形成互连结构的额外的层。
图3A、图3B和图3C示出受益于本发明的改进的介电膜的半导体器件的另一实施例。参考图3A,其中示出根据实施例的3D堆叠的BSI图像传感器300。图像传感器300包括通过晶圆级接合而接合在一起的第一衬底(例如,半导体晶圆)302和第二衬底352(例如,另一半导体晶圆)。每个衬底302和352可以包括诸如硅或锗的元素半导体;诸如碳化硅、砷化镓、砷化铟和磷化铟的化合物半导体;或诸如碳化硅锗、磷化镓砷和磷化镓铟的合金半导体。第一衬底302具有第一(前)侧304和第二(背)侧306。第二衬底352具有第一(前)侧354和第二(背)侧356。使用金属接合、直接接合、混合接合或其他接合方法将两个前侧304和354接合在一起。衬底302包括在第一部分308中的金属引线310。在第二部分309中,衬底302包括通过深沟槽隔离(DTI)部件318彼此隔离的光敏元件(例如,光电二极管)312。图像传感器300还包括设置在背侧306上方的滤色器314和微透镜316。入射在图像传感器300上的辐射将在光敏元件312中形成图像。通过DTI部件318的隔离改进了图像传感器300的灵敏度和分辨率。本发明的改进的介电膜可以用作DTI部件318中的衬垫层。
仍参考图3A,衬底352包括第一部分358中的金属引线360。在第二部分359中,衬底352还可以包括光敏元件(未示出),例如,以使图像传感器300为双对靶图像传感器。图像传感器300还包括导电部件320和互连金属引线310和360的硅通孔(TSV)322,用于集成衬底302和352的功能。本发明的改进的介电膜可以用作TSV 322中的衬垫层。在另一实施例中,可以在304/354的界面处使用金属直接接合而不是使用TSV 322来互连衬底302和352。
参考图3B,其中示出了根据实施例的图像传感器300的放大示意图,示出了DTI318的更详细的视图。DTI 318包括嵌入在衬底302中的多个层。例如,DTI 318包括位于在衬底302中蚀刻的深沟槽的底壁和侧壁上的粘附层318a、位于粘附层318a上方的一个或多个负电荷累积层318b、位于层318b上方的改进的介电层318c、位于层318c上方的金属阻挡层318d(例如,TiN)和位于金属阻挡层318d上方的金属层318e。在实施例中,层318b包括诸如五氧化二钽(Ta2O5)的金属氧化物,并且金属层318e包括W、Al、Cu、Co或其他合适的金属。为了进一步的实施例,使用CVD或ALD方法在层318b上方沉积改进的介电层318c,其中氧和具有硅与氮的有机化合物是前体。有机化合物可以是BTBAS、BDEAS、TIPAS、BDEAES、TEAS和其他合适的有机化合物中的一种。改进的介电层318c包括Si、N、C和O而在其中不含Si-金属合金。此外,如上文中相对于介电膜132所讨论的,层318c在其下部处包括比在其上部中更高浓度的N和/或C。如本文所使用的,下部是指介电层318c的靠近层318b处的部分,而上部是指介电层318c的远离层318b的另一部分。介电层318c有效地将层318d和318e中的金属元件与层318b中的金属元件绝缘。
参考图3C,其中示出了根据实施例的图像传感器300的放大示意图,示出了TSV322的更详细的视图。TSV 322电接触嵌入在介电层324中的导电部件320。TSV 322包括嵌入在衬底302/352中的多个层。例如,TSV322包括沉积在沟槽(沟槽蚀刻于衬底302和352中)的至少侧壁上的第一介电层322a、位于第一介电层322a上方的金属阻挡层322b和位于金属阻挡层322b上方的金属层322c。在实施例中,金属阻挡层322b可以包含TiN。金属层322c可以包含W、Al、Cu、Co或其他合适的金属。在实施例中,图像传感器300包括位于第一介电层322a和衬底302/352之间的金属氧化物层(未示出)。使用CVD或ALD方法沉积第一介电层322a,其中氧和具有硅与氮的有机化合物是前体。有机化合物可以是BTBAS、BDEAS、TIPAS、BDEAES、TEAS和其他合适的有机化合物中的一种。改进的介电层322a包括Si、N、C和O而在其中不含有Si-金属合金。此外,如上文中相对于介电膜132和318c所讨论的,层322a在其下部分处包含比在其上部中更高的N和/或C浓度。第一介电层322a有效地将层322b和322c中的金属元件与衬底302/352以及第一介电层322a下面的任何金属氧化物层绝缘。
虽然不旨在限制,本发明的一个或多个实施例为半导体制造提供了许多益处。例如,根据本发明的改进的介电膜提供位于诸如金属栅极和金属通孔的金属元件之间的有效电绝缘。沉积改进的介电膜的方法不产生硅金属合金,这有效地防止金属泄漏和金属扩散。由于高k金属栅极在先进的半导体制造中变得流行,该改进的介电膜提供了对金属栅极短路缺陷和通过薄的介电膜的金属扩散的问题的有效解决方案。此外,所提供的方法可以容易地集成到现有的半导体工艺流程中。
在一个示例性方面中,本发明涉及用于半导体制造的方法。该方法包括接收具有第一表面的器件,通过该表面暴露第一金属或第一金属的氧化物。该方法还包括在第一表面上方沉积具有Si、N、C和O的介电膜,从而使得介电膜在介电膜的靠近第一表面的第一部分中具有比在介电膜的第二部分中的更高的N和C浓度,该介电膜的第二部分比第一部分更远离第一表面。该方法还包括在介电膜上方形成导电部件。
在另一示例性方面中,本发明涉及用于半导体制造的方法。该方法包括接收具有第一表面的器件,通过该第一表面暴露半导体材料或器件的第一金属。该方法还包括通过低温化学汽相沉积(LT CVD)工艺在第一表面上方沉积具有Si、N、C和O的介电膜,从而使得介电膜在靠近第一表面的介电膜的第一部分中具有比在远离第一表面的介电膜的第二部分中更高的N和C浓度。该方法还包括在介电膜上方沉积第二金属。
在又一示例性方面中,本发明涉及一种半导体器件。该半导体器件包括具有第一表面的第一层,通过该表面暴露第一金属或第一金属的氧化物。半导体器件还包括直接位于第一表面上方的介电膜,其中介电膜包括Si、N、C和O,并且在介电膜的靠近第一表面的第一部分中比在介电膜的第二部分中具有更高的C和N浓度,该介电膜的第二部分比第一部分更远离第一表面。半导体器件还包括位于介电膜上方的导电部件。
在半导体器件的实施例中,介电膜的第一部分中的C浓度比介电膜的第二部分中的C浓度至少多10倍。在半导体器件的另一实施例中,介电膜的第一部分中的N浓度比介电膜的第二部分中的C浓度至少多10倍。在半导体器件的又一实施例中,介电膜的第一部分中的每个C和N浓度比介电膜的第二部分中的每个C和N浓度至少多10倍。
根据本发明的一些实施例,提供了一种用于半导体制造的方法,包括:接收具有第一表面的器件,通过所述第一表面暴露第一金属或所述第一金属的氧化物;在所述第一表面上方沉积具有Si、N、C和O的介电膜,从而使得所述介电膜在靠近所述第一表面的所述介电膜的第一部分中具有比在所述介电膜的第二部分中更高的N和C浓度,所述介电膜的第二部分比所述第一部分更远离所述第一表面;以及在所述介电膜上方形成导电部件。
在上述方法中,通过使用氧和有机化合物作为前体的低温化学汽相沉积(LT CVD)工艺来沉积所述介电膜,所述有机化合物具有硅和氮。
在上述方法中,所述有机化合物是BTBAS(双(叔丁基氨基)硅烷)。
在上述方法中,所述有机化合物是BDEAS(双(二乙基氨基)硅烷)。
在上述方法中,所述有机化合物是TIPAS(三(异丙基氨基)硅烷)的一种。
在上述方法中,所述有机化合物是BDEAES(双(二乙基氨基)乙基硅烷)或TEAS(三(乙基氨基)硅烷)。
在上述方法中,在从300℃至400℃的范围的温度处实施所述低温化学汽相沉积工艺。
在上述方法中,所述第一金属是Al或Cu。
在上述方法中,通过使用氧和有机化合物作为前体的原子层沉积(ALD)工艺实施所述介电膜的沉积,所述有机化合物具有硅和氮。
在上述方法中,所述介电膜的所述第一部分中的C浓度比所述介电膜的所述第二部分中的C浓度至少多10倍。
在上述方法中,所述介电膜的所述第一部分中的N浓度比所述介电膜的所述第二部分中的N浓度至少多10倍。
在上述方法中,所述第一表面是沟槽的底部和侧壁,所述介电膜部分地填充所述沟槽,并且还在所述沟槽内沉积所述导电部件。
根据本发明的另一些实施例,还提供了一种用于半导体制造的方法,包括:接收具有第一表面的器件,通过所述第一表面暴露半导体材料或所述器件的第一金属;通过低温化学汽相沉积(LT CVD)工艺在所述第一表面上方沉积具有Si、N、C和O的介电膜,从而使得所述介电膜在靠近所述第一表面的所述介电膜的第一部分中具有比在远离所述第一表面的所述介电膜的第二部分中更高的N和C浓度;以及在所述介电膜上方沉积第二金属。
在上述方法中,所述低温化学汽相沉积工艺使用氧以及BTBAS(双(叔丁基氨基)硅烷)、TIPAS(三(异丙基氨基)硅烷)和BDEAS(双(二乙基氨基)硅烷)中的一种作为前体。
在上述方法中,所述低温化学汽相沉积工艺使用氧以及BDEAES(双(二乙基氨基)乙基硅烷)与TEAS(三(乙基氨基)硅烷)中的一种作为前体。
在上述方法中,所述介电膜的所述第一部分中的C和N的每个的浓度比所述介电膜的所述第二部分中的C和N的浓度至少多10倍。
根据本发明的又一个实施例,还提供了一种半导体器件,包括:第一层,具有第一表面,通过所述第一表面暴露第一金属或所述第一金属的氧化物;介电膜,直接位于所述第一表面上方,其中,所述介电膜包括Si、N、C和O,并且在靠近所述第一表面的所述介电膜的第一部分中具有比在所述介电膜的第二部分中的更高的C和N浓度,所述介电膜的第二部分比所述第一部分更远离所述第一表面;以及导电部件,位于所述介电膜上方。
在上述半导体器件中,所述介电膜的所述第一部分中的C浓度比所述介电膜的所述第二部分中的C浓度至少多10倍。
在上述半导体器件中,所述介电膜的所述第一部分中的N浓度比所述介电膜的所述第二部分中的N浓度至少多10倍。
在上述半导体器件中,所述介电膜的所述第一部分中的C和N浓度中的每个比所述介电膜的所述第二部分中的C和N浓度至少多10倍。
上面概述了若干实施例的特征,使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,在此他们可以做出多种变化、替换以及改变。
Claims (20)
1.一种用于半导体制造的方法,包括:
接收具有第一表面的器件,通过所述第一表面暴露第一金属或所述第一金属的氧化物;
在所述第一表面上方沉积具有Si、N、C和O的介电膜,从而使得所述介电膜在靠近所述第一表面的所述介电膜的第一部分中具有比在所述介电膜的第二部分中更高的N和C浓度,所述介电膜的第二部分比所述第一部分更远离所述第一表面;以及
在所述介电膜上方形成导电部件,
其中,所述介电膜的部分介于所述第一表面和所述导电部件之间,
其中,在形成所述介电膜的过程中先形成N和C浓度高的所述第一部分而后形成N和C浓度低的所述第二部分,在形成所述介电膜的过程中Si自由基不与所述第一金属或所述第一金属的氧化物中的金属反应。
2.根据权利要求1所述的方法,其中,通过使用氧和有机化合物作为前体的低温化学汽相沉积(LT CVD)工艺来沉积所述介电膜,所述有机化合物具有硅和氮。
3.根据权利要求2所述的方法,其中,所述有机化合物是BTBAS(双(叔丁基氨基)硅烷)。
4.根据权利要求2所述的方法,其中,所述有机化合物是BDEAS(双(二乙基氨基)硅烷)。
5.根据权利要求2所述的方法,其中,所述有机化合物是TIPAS(三(异丙基氨基)硅烷)的一种。
6.根据权利要求2所述的方法,其中,所述有机化合物是BDEAES(双(二乙基氨基)乙基硅烷)或TEAS(三(乙基氨基)硅烷)。
7.根据权利要求2所述的方法,其中,在从300℃至400℃的范围的温度处实施所述低温化学汽相沉积工艺。
8.根据权利要求1所述的方法,其中,所述第一金属是Al或Cu。
9.根据权利要求1所述的方法,其中,通过使用氧和有机化合物作为前体的原子层沉积(ALD)工艺实施所述介电膜的沉积,所述有机化合物具有硅和氮。
10.根据权利要求1所述的方法,其中,所述介电膜的所述第一部分中的C浓度比所述介电膜的所述第二部分中的C浓度至少多10倍。
11.根据权利要求1所述的方法,其中,所述介电膜的所述第一部分中的N浓度比所述介电膜的所述第二部分中的N浓度至少多10倍。
12.根据权利要求1所述的方法,其中,所述第一表面是沟槽的底部和侧壁,所述介电膜部分地填充所述沟槽,并且还在所述沟槽内沉积所述导电部件。
13.一种用于半导体制造的方法,包括:
接收具有第一表面的器件,通过所述第一表面暴露半导体材料或所述器件的第一金属;
通过低温化学汽相沉积(LT CVD)工艺在所述第一表面上方沉积具有Si、N、C和O的介电膜,从而使得所述介电膜在靠近所述第一表面的所述介电膜的第一部分中具有比在远离所述第一表面的所述介电膜的第二部分中更高的N和C浓度;以及
在所述介电膜上方沉积第二金属,
其中,所述介电膜的部分介于所述第一表面和所述第二金属之间,
其中,在形成所述介电膜的过程中先形成N和C浓度高的所述第一部分而后形成N和C浓度低的所述第二部分,在形成所述介电膜的过程中Si自由基不与所述第一金属反应。
14.根据权利要求13所述的方法,其中,所述低温化学汽相沉积工艺使用氧以及BTBAS(双(叔丁基氨基)硅烷)、TIPAS(三(异丙基氨基)硅烷)和BDEAS(双(二乙基氨基)硅烷)中的一种作为前体。
15.根据权利要求13所述的方法,其中,所述低温化学汽相沉积工艺使用氧以及BDEAES(双(二乙基氨基)乙基硅烷)与TEAS(三(乙基氨基)硅烷)中的一种作为前体。
16.根据权利要求13所述的方法,其中,所述介电膜的所述第一部分中的C和N的每个的浓度比所述介电膜的所述第二部分中的C和N的浓度至少多10倍。
17.一种半导体器件,包括:
衬底,所述衬底中形成有晶体管的第一源极/漏极区和第二源极/漏极区;
第一层,所述第一层位于衬底上方,所述第一层中具有栅极堆叠件,所述第一层具有第一表面,通过所述第一表面暴露所述栅极堆叠件中的第一金属或所述第一金属的氧化物,所述第一源极/漏极区和所述第二源极/漏极区位于所述栅极堆叠件的相对两侧;
介电膜,直接位于所述第一表面上方,其中,所述介电膜包括Si、N、C和O,并且在靠近所述第一表面的所述介电膜的第一部分中具有比在所述介电膜的第二部分中的更高的C和N浓度,所述介电膜的第二部分比所述第一部分更远离所述第一表面;以及
导电部件,位于所述介电膜上方,
其中,所述介电膜的部分介于所述第一表面和所述导电部件之间,
其中,所述第一部分比所述第二部分更靠近所述衬底,所述介电膜的整个区域中没有金属硅合金。
18.根据权利要求17所述的半导体器件,其中,所述介电膜的所述第一部分中的C浓度比所述介电膜的所述第二部分中的C浓度至少多10倍。
19.根据权利要求17所述的半导体器件,其中,所述介电膜的所述第一部分中的N浓度比所述介电膜的所述第二部分中的N浓度至少多10倍。
20.根据权利要求17所述的半导体器件,其中,所述介电膜的所述第一部分中的C和N浓度中的每个比所述介电膜的所述第二部分中的C和N浓度至少多10倍。
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Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110199392B (zh) * | 2017-01-24 | 2023-05-12 | 索尼半导体解决方案公司 | 半导体装置及其制造方法、固态成像元件和电子设备 |
CN108470711B (zh) * | 2018-02-12 | 2020-10-02 | 上海集成电路研发中心有限公司 | 图像传感器的深沟槽和硅通孔的制程方法 |
DE102018121897A1 (de) | 2018-09-07 | 2020-03-12 | Infineon Technologies Ag | Halbleitervorrichtung mit einem silizium und stickstoff enthaltenden bereich und herstellungsverfahren |
US11846738B2 (en) * | 2019-04-23 | 2023-12-19 | Cerium Laboratories Llc | Radiation detection systems and methods |
US12040241B2 (en) * | 2019-12-13 | 2024-07-16 | Xidian University | Package structure for semiconductor device and preparation method thereof |
US11823989B2 (en) * | 2020-07-17 | 2023-11-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multi-liner TSV structure and method forming same |
US20220310678A1 (en) * | 2021-03-26 | 2022-09-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | High reflectance isolation structure to increase image sensor performance |
US12062679B2 (en) * | 2021-04-27 | 2024-08-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Backside structure for image sensor |
US12062656B2 (en) * | 2021-10-29 | 2024-08-13 | Nanya Technology Corporation | Semiconductor device structure |
EP4261871A1 (fr) * | 2022-04-11 | 2023-10-18 | STMicroelectronics Crolles 2 SAS | Circuit intégré comportant un pilier métallique en contact avec une région en silicium sur une région de couplage ohmique, et procédé de fabrication correspondant |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1519925A (zh) * | 2003-02-04 | 2004-08-11 | 恩益禧电子股份有限公司 | 半导体器件及其制造方法 |
CN1536660A (zh) * | 2003-03-25 | 2004-10-13 | ��ʽ���������Ƽ� | 半导体器件及其制造方法 |
CN105097657A (zh) * | 2014-05-09 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法 |
Family Cites Families (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8358011B1 (en) * | 2007-09-07 | 2013-01-22 | International Business Machines Corporation | Interconnect structures with engineered dielectrics with nanocolumnar porosity |
US7144825B2 (en) * | 2003-10-16 | 2006-12-05 | Freescale Semiconductor, Inc. | Multi-layer dielectric containing diffusion barrier material |
US20060045986A1 (en) | 2004-08-30 | 2006-03-02 | Hochberg Arthur K | Silicon nitride from aminosilane using PECVD |
US7667275B2 (en) * | 2004-09-11 | 2010-02-23 | Texas Instruments Incorporated | Using oxynitride spacer to reduce parasitic capacitance in CMOS devices |
US7964422B1 (en) * | 2005-11-01 | 2011-06-21 | Nvidia Corporation | Method and system for controlling a semiconductor fabrication process |
US7780865B2 (en) * | 2006-03-31 | 2010-08-24 | Applied Materials, Inc. | Method to improve the step coverage and pattern loading for dielectric films |
US7816256B2 (en) * | 2006-07-17 | 2010-10-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Process for improving the reliability of interconnect structures and resulting structure |
CN101393862B (zh) * | 2007-09-20 | 2011-03-23 | 中芯国际集成电路制造(上海)有限公司 | 栅极侧壁层的制造方法及半导体器件的制造方法 |
JP2009260151A (ja) | 2008-04-18 | 2009-11-05 | Tokyo Electron Ltd | 金属ドープ層の形成方法、成膜装置及び記憶媒体 |
US8193586B2 (en) | 2008-08-25 | 2012-06-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Sealing structure for high-K metal gate |
JP2010182822A (ja) | 2009-02-04 | 2010-08-19 | Renesas Electronics Corp | 半導体装置およびその製造方法 |
JP2010206056A (ja) * | 2009-03-05 | 2010-09-16 | Renesas Electronics Corp | 半導体集積回路装置の製造方法 |
JP5247619B2 (ja) | 2009-07-28 | 2013-07-24 | キヤノンアネルバ株式会社 | 誘電体膜、誘電体膜を用いた半導体装置の製造方法及び半導体製造装置 |
JPWO2011033987A1 (ja) | 2009-09-17 | 2013-02-14 | 東京エレクトロン株式会社 | 成膜方法、半導体素子の製造方法、絶縁膜および半導体素子 |
US8709948B2 (en) | 2010-03-12 | 2014-04-29 | Novellus Systems, Inc. | Tungsten barrier and seed for copper filled TSV |
US8390089B2 (en) | 2010-07-27 | 2013-03-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Image sensor with deep trench isolation structure |
JP5544343B2 (ja) | 2010-10-29 | 2014-07-09 | 東京エレクトロン株式会社 | 成膜装置 |
JP5839804B2 (ja) * | 2011-01-25 | 2016-01-06 | 国立大学法人東北大学 | 半導体装置の製造方法、および半導体装置 |
US9029260B2 (en) | 2011-06-16 | 2015-05-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gap filling method for dual damascene process |
US8803322B2 (en) | 2011-10-13 | 2014-08-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through substrate via structures and methods of forming the same |
US9190316B2 (en) * | 2011-10-26 | 2015-11-17 | Globalfoundries U.S. 2 Llc | Low energy etch process for nitrogen-containing dielectric layer |
US8779600B2 (en) * | 2012-01-05 | 2014-07-15 | International Business Machines Corporation | Interlevel dielectric stack for interconnect structures |
US8779592B2 (en) * | 2012-05-01 | 2014-07-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Via-free interconnect structure with self-aligned metal line interconnections |
US8946095B2 (en) | 2012-10-25 | 2015-02-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming interlayer dielectric film above metal gate of semiconductor device |
US20140252521A1 (en) | 2013-03-11 | 2014-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Image Sensor with Improved Dark Current Performance |
US20140273516A1 (en) * | 2013-03-13 | 2014-09-18 | Applied Materials, Inc. | Vbd and tddb improvement thru interface engineering |
US9224811B2 (en) * | 2014-03-17 | 2015-12-29 | Globalfoundries Inc | Stacked semiconductor device |
CN104409419B (zh) | 2014-11-17 | 2018-01-02 | 上海集成电路研发中心有限公司 | 一种空气侧墙的制作方法 |
US9312224B1 (en) * | 2014-12-11 | 2016-04-12 | International Business Machines Corporation | Interconnect structure containing a porous low k interconnect dielectric/dielectric cap |
CN104465506B (zh) | 2014-12-24 | 2018-01-26 | 上海集成电路研发中心有限公司 | 铜互连中空气隙的形成方法 |
US9536826B1 (en) * | 2015-06-15 | 2017-01-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fin field effect transistor (finFET) device structure with interconnect structure |
US10304850B2 (en) * | 2015-09-08 | 2019-05-28 | Toshiba Memory Corporation | Semiconductor memory device |
KR102500813B1 (ko) * | 2015-09-24 | 2023-02-17 | 삼성전자주식회사 | 반도체 소자 및 이의 제조 방법 |
US9711456B2 (en) * | 2015-12-19 | 2017-07-18 | International Business Machines Corporation | Composite manganese nitride/low-K dielectric cap |
US9917121B2 (en) * | 2016-03-24 | 2018-03-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | BSI image sensor and method of forming same |
-
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- 2016-09-30 US US15/282,258 patent/US10658296B2/en active Active
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- 2017-01-13 TW TW106101278A patent/TWI605541B/zh active
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- 2022-04-04 US US17/712,306 patent/US11901295B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1519925A (zh) * | 2003-02-04 | 2004-08-11 | 恩益禧电子股份有限公司 | 半导体器件及其制造方法 |
CN1536660A (zh) * | 2003-03-25 | 2004-10-13 | ��ʽ���������Ƽ� | 半导体器件及其制造方法 |
CN105097657A (zh) * | 2014-05-09 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法 |
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