TW201735278A - 陶瓷基板、積層體及表面聲波元件 - Google Patents

陶瓷基板、積層體及表面聲波元件 Download PDF

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TW201735278A
TW201735278A TW105113988A TW105113988A TW201735278A TW 201735278 A TW201735278 A TW 201735278A TW 105113988 A TW105113988 A TW 105113988A TW 105113988 A TW105113988 A TW 105113988A TW 201735278 A TW201735278 A TW 201735278A
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substrate
main surface
ceramic substrate
less
ceramic
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TW105113988A
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TWI590393B (zh
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下司慶一郎
中山茂
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住友電氣工業股份有限公司
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    • C04B35/443—Magnesium aluminate spinel
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Abstract

陶瓷基板係由多晶陶瓷構成，具有支持主面。支持主面之粗度Sa在0.01nm以上3.0nm以下。支持主面中，一邊50μm之正方形區域中1nm以上的凹凸平均小於5個，而且2nm以上的凹凸平均小於1個。

Description

陶瓷基板、積層體及表面聲波元件
本發明關於陶瓷基板、積層體及SAW元件(Surface Acostic Wave Device，表面聲波元件)元件，更特定則為關於適用於壓電體基板之支持的陶瓷基板、包含壓電體基板與陶瓷基板的積層體、及包含該積層體的SAW元件者。
在行動電話等通信機器之內部，為了除去內含於電氣信號的雜訊之目的，而配置SAW元件(Surface Acoustic Wave Device；表面聲波元件)。SAW元件具有由輸入的電氣信號之中僅取出所要之頻率之電氣信號的機能。SAW元件具有在壓電體基板上形成有電極之構造。為了使用時之散熱目的，壓電體基板被配置於由散熱性高的材料形成之底材基板上。
底材基板例如可以採用由單晶藍寶石形成之基板。但是，採用由單晶藍寶石形成之基板作為底材基板時，有SAW元件之製造成本上昇問題。針對此而提案之SAW元件，係採用由多晶尖晶石形成之陶瓷基板作為底 材基板，具有藉由凡德瓦力(Van der waals force)將壓電體基板與減少表面粗度Ra(算術平均粗度)的陶瓷基板予以結合的構造。如此則可以抑制SAW元件之製造成本(例如參照專利文獻1)。
[先行技術文獻] [專利文獻]
[專利文獻1]特開2011-66818號公報
依據本揭示的陶瓷基板，係由多晶陶瓷構成，具有支持主面的陶瓷基板。支持主面之粗度Sa在0.01nm以上3.0nm以下。支持主面中，一邊50μm之正方形區域中1nm以上的凹凸平均小於5個，而且2nm以上的凹凸平均小於1個。
1‧‧‧積層體
10‧‧‧底材基板
100‧‧‧SAW元件
11‧‧‧支持主面
20‧‧‧壓電體基板
21‧‧‧露出主面
22‧‧‧結合主面
30‧‧‧輸入側電極
31‧‧‧第1部分
31A‧‧‧底材部
31B‧‧‧突出部
32‧‧‧第2部分
32A‧‧‧底材部
32B‧‧‧突出部
40‧‧‧輸出側電極
41‧‧‧第1部分
41A‧‧‧底材部
41B‧‧‧突出部
42‧‧‧第2部分
42A‧‧‧底材部
42B‧‧‧突出部
51‧‧‧輸入側配線
61‧‧‧輸出側配線
[圖1]包含陶瓷基板及壓電體基板的積層體之構造的概略斷面圖。
[圖2]陶瓷基板、積層體及SAW元件之製造方法之概略流程圖。
[圖3]陶瓷基板、積層體及SAW元件之製造方法說 明用的概略斷面圖。
[圖4]積層體及SAW元件之製造方法說明用的概略斷面圖。
[圖5]積層體及SAW元件之製造方法說明用的概略斷面圖。
[圖6]積層體及SAW元件之製造方法說明用的概略圖。
[圖7]SAW元件之構造之概略圖。
[揭示所欲解決之課題]
為了進一步減少SAW元件之製造成本，而要求更增大壓電體基板與陶瓷基板間之結合力。於此，目的之一在於提供可以充分的結合力結合壓電體基板之陶瓷基板、壓電體基板與陶瓷基板藉由充分的結合力結合之積層體、及包含該積層體的SAW元件。
[本揭示之效果]
依據上述陶瓷基板，可以提供可以充分的結合力結合壓電體基板的陶瓷基板。
首先，以下對本發明之實施態樣進行說明。本發明之陶瓷基板，係由多晶陶瓷構成，具有支持主面的陶瓷基板。支持主面之粗度Sa在0.01nm以上3.0nm以 下。支持主面中，一邊50μm之正方形區域中1nm以上的凹凸平均小於5個，而且2nm以上的凹凸平均小於1個。
本發明人針對藉由凡德瓦力將壓電體基板與減少表面之算術平均粗度的陶瓷基板(底材基板)進行結合時，發生結合力不足之原因進行檢討。結果發現，就算術平均粗度之觀點而言即使粗度充分減少時，較大的凹凸、具體言之1nm以上的凹凸在一邊50μm之正方形區域內存在5個以上時，或2nm以上的凹凸在一邊50μm之正方形區域內存在1個以上時，發現結合力不足。亦即，欲獲得充分的結合力時，不只針對算術平均粗度之觀點(平均粗度之觀點)充分減少粗度，如上述說明，亦需要減少稀少存在的較大的凹凸。
本發明之陶瓷基板中，藉由將支持主面之粗度Sa設為0.01nm以上3.0nm以下，而充分減少算術平均粗度之觀點中的表面粗度。另外，本發明之陶瓷基板中設為，在支持主面之一邊50μm之正方形區域中1nm以上的凹凸平均小於5個，而且2nm以上的凹凸平均小於1個。亦即，本發明之陶瓷基板中，不僅就算術平均粗度之觀點充分減少支持主面之粗度，支持主面上稀少存在的較大的凹凸亦被減少。結果，依據本發明之陶瓷基板，可以提供可以充分的結合力與壓電體基板進行結合的陶瓷基板。
上述陶瓷基板中，支持主面之粗度Sq在 0.5nm以下亦可。如此則，能更確實確保與壓電體基板之間之充分的結合力。
上述陶瓷基板可以由多晶陶瓷構成，該多晶陶瓷係由尖晶石(MgAl2O4)、氧化鋁(Al2O3)、氧化鎂(MgO)、二氧化矽(SiO2)、莫來石(3Al2O3．2SiO2)、堇青石(2MgO．2Al2O3．5SiO2)、氧化鈣(CaO)、二氧化鈦(TiO2)、氮化矽(Si3N4)、氮化鋁(AlN)及碳化矽(SiC)形成之群所選擇的1種以上之材料形成者。彼等材料適合作為構成本發明之陶瓷基板的材料。
本發明之積層體具備：上述陶瓷基板；及配置於支持主面上，由壓電體形成之壓電體基板。陶瓷基板與壓電體基板藉由凡德瓦力結合。
本發明之積層體中，不僅就算術平均粗度之觀點充分減少支持主面之粗度，在支持主面上稀少存在的較大的凹凸亦被減少之上述陶瓷基板與壓電體基板係藉由凡德瓦力結合。因此，依據本發明之積層體，可以提供可以充分的結合力將壓電體基板與陶瓷基板進行結合的積層體。
上述積層體中，陶瓷基板與壓電體基板之接合強度在0.5J/m2以上亦可。如此則，壓電體基板與陶瓷基板更確實被結合。壓電體基板與陶瓷基板間之結合力小於0.5J/m2時，SAW元件之製造中被實施的電極形成工程或晶片化工程中有可能發生基板之剝離、缺損等。另外， 就達成確實的壓電體基板與陶瓷基板之結合觀點而言，陶瓷基板與壓電體基板之接合強度在1.0J/m2以上為較佳，1.3J/m2以上更佳，進一步1.5J/m2以上再更佳。
本發明之SAW元件具備：上述本發明之積層體；及在壓電體基板之與陶瓷基板相反側的主面上被形成的電極。本發明之SAW元件包含本發明之積層體，該本發明之積層體中壓電體基板與多晶陶瓷所形成之陶瓷基板係藉由充分的結合力結合者。因此，可以提供可以抑制製造成本之同時，壓電體基板與陶瓷基板藉由充分的結合力結合之SAW元件。
又，粗度Sa、Sq及Sz分別意味著基於ISO25178的算術平均高度Sa，均方根高度Sq及最大高度Sz。彼等表面粗度之參數例如可以使用3維表面粗度測定器進行測定。
接著，參照圖面之同時說明本發明的陶瓷基板及積層體之一實施形態。又，以下之圖面中同一或相當的部分附加同一之參照編號並省略重複說明。
參照圖1，本實施形態中積層體1具備：作為陶瓷基板之底材基板10；及壓電體基板20。壓電體基板20例如由鉭酸鋰(LiTaO3)、鈮酸鋰(LiNbO3)等之壓電體形成。底材基板10由多晶陶瓷形成，該多晶陶瓷係由尖晶石、氧化鋁、氧化鎂、二氧化矽、莫來石、堇青石、氧化鈣、二氧化鈦、氮化矽、氮化鋁及碳化矽形成之群所選擇的一種以上，較好是由其中任一種材料構成。
底材基板10具有支持主面11。壓電體基板20具有：一方之主面亦即露出主面21；及露出主面21的相反側之主面亦即結合主面22。壓電體基板20係以結合主面22接觸底材基板10之支持主面11的方式被配置。底材基板10與壓電體基板20藉由凡德瓦力結合。
底材基板10之支持主面11中，粗度Sa在0.01nm以上3.0nm以下。又，支持主面11中，一邊50μm之正方形區域中1nm以上的凹凸之個數平均小於5個，而且2nm以上的凹凸之個數平均小於1個。
積層體1中，藉由支持主面11之粗度Sa設為0.01nm以上3.0nm以下，則就算術平均粗度之觀點而言表面粗度被充分減少。另外，積層體1中，將支持主面11之一邊50μm之正方形區域中1nm以上的凹凸設為平均小於5個，而且將2nm以上的凹凸設為平均小於1個。亦即，積層體1中，不僅算術平均粗度之觀點中粗度被充分減少，稀少存在的較大的凹凸亦被減少。結果，積層體1成為壓電體基板20與底材基板10藉由充分的結合力結合之積層體。
又，本發明中1nm以上的凹凸意味著算出測定區域(一邊50μm之正方形區域)中之平均面(平均高度)，該平均面起至頂點(或底)之間之距離為1nm以上的凹凸。同樣地，2nm以上的凹凸意味著算出測定區域(一邊50μm之正方形區域)中之平均面(平均高度)，該平均面起至頂點(或底)之間之距離為2nm以上的凹 凸。支持主面11之中藉由顯微鏡等計數複數個測定區域(一邊50μm之正方形區域)中凹凸之數目，將其平均值設為凹凸之平均數。
就更確實獲得壓電體基板20與底材基板10之間之充分的結合力觀點而言，支持主面之粗度Sa在2.0nm以下為較佳，1.0nm以下為更佳。又，支持主面11之一邊50μm之正方形區域中1nm以上的凹凸設為平均小於4個為較佳，小於3個為更佳，小於2個為再更佳。
支持主面11之粗度Sq較好是在0.5nm以下。如此則，能更確實確保壓電體基板20與底材基板10之間之充分的結合力。
底材基板10與壓電體基板20之接合強度在0.5J/m2以上為較佳。如此則，能更確實結合壓電體基板20與底材基板10。
接著，說明本實施形態中作為陶瓷基板的底材基板10、積層體1及使用積層體1的SAW元件之製造方法。參照圖2，本實施形態之底材基板10、積層體1及SAW元件之製造方法中，首先，作為工程(S10)而實施底材基板準備工程。該工程(S10)中，參照圖3準備由多晶陶瓷形成之底材基板10，該多晶陶瓷係由尖晶石、氧化鋁、氧化鎂、二氧化矽、莫來石、堇青石、氧化鈣、二氧化鈦、氮化矽、氮化鋁及碳化矽形成之群所選擇的一種以上材料構成。例如準備由上述群所選擇的任一種材料構成的多晶陶瓷所形成之底材基板10。具體言之，例如 準備由多晶尖晶石形成之底材基板10時，係準備混合氧化鎂粉末與氧化鋁粉末而成的原料粉末，藉由成形而製作成形體。成形體例如藉由沖壓成形實施預備成形後，藉由實施CIP(Cold Isostatic Press)來製作。接著，對成形體實施燒結處理。燒結處理例如可以藉由真空燒結法、HIP(Hot Isostatic Press)等之方法實施。如此而獲得燒結體。之後，對燒結體實施切片加工，獲得具有所要之形狀(厚度)的底材基板10(圖3)。
接著，實施作為工程(S20)的第1研磨工程。該工程(S20)中，參照圖3，係針對工程(S10)中準備的底材基板10之支持主面11進行粗研磨。具體言之，例如使用磨粒之粒度為#800~#2000之GC(Green Silicon Carbide)磨石對支持主面11進行粗研磨。
接著，實施作為工程(S30)的第2研磨工程。該工程(S30)中，係對工程(S20)中被實施粗研磨的支持主面11實施通常研磨。具體言之，例如使用磨粒之粒徑為3~5μm之鑽石磨石對支持主面11進行通常研磨。
接著，實施作為工程(S40)的第3研磨工程。該工程(S40)中，係對工程(S30)中被實施通常研磨的支持主面11實施最終研磨。具體言之，例如使用粒徑為0.5~1.0μm之鑽石磨粒對支持主面11實施最終研磨。如此則，可以達成Sa為0.01nm以上3.0nm以下之支持主面11之粗度。但是，支持主面11基於鑽石磨粒會產 生划痕。因此，支持主面11中雖達成Sa在0.01nm以上3.0nm以下之粗度，但是存在划痕引起的較大的凹凸。
接著，實施作為工程(S50)的第4研磨工程。該工程(S50)中，係對工程(S40)中被實施最終研磨的支持主面11實施划痕除去研磨。具體言之，例如對支持主面11實施些許研磨量之CMP(Chemical Mechanical Polishing)。CMP之研磨量設為數百nm左右。如此則，支持主面11之粗度可以維持Sa在0.01nm以上3.0nm以下之同時，支持主面11中可以達成一邊50μm之正方形區域中1nm以上的凹凸平均小於5個，而且2nm以上的凹凸平均小於1個。如此而完成本實施形態中作為陶瓷基板的底材基板10。
接著，實施作為工程(S60)的貼合工程。該工程(S60)中，係將在工程(S20)~(S50)中支持主面11被研磨後的底材基板10，與另外準備的壓電體基板20進行貼合。具體言之，參照圖3及圖1，準備由鉭酸鋰、鈮酸鋰等之壓電體形成之壓電體基板20，以使壓電體基板20之結合主面22與底材基板10之支持主面11接觸的方式，將底材基板10與壓電體基板20予以貼合。如此則，底材基板10與壓電體基板20藉由凡德瓦力被結合。結果，獲得本實施形態之積層體1。
於此，本實施形態中，不僅從算術平均粗度之觀點充分減少支持主面之粗度，在支持主面上雖稀少但存在的較大凹凸(划痕)亦被減少。結果，依據上述積層 體1之製造方法，可以製造壓電體基板20與底材基板10藉由充分的結合力結合之積層體1。
接著，對使用積層體1的SAW元件之製造方法進行說明。參照圖2，接續工程(S60)而實施作為工程(S70)的減厚工程。該工程(S70)中，係參照圖1及圖4，對工程(S60)中獲得的積層體1之壓電體基板20實施減少厚度的加工。具體言之，例如對壓電體基板20之露出主面21實施研削處理。如此則，壓電體基板20之厚度減少為適合SAW元件之厚度。
接著，實施作為工程(S80)的電極形成工程。該工程(S80)中，參照圖4~圖6，而在壓電體基板20之露出主面21形成梳齒型之電極。圖5係沿圖6之V-V線的斷面圖。具體言之，參照圖5及圖6，在工程(S70)中被調整為適當厚度的壓電體基板20之露出主面21上，形成由Al等之導電體形成之導電體膜。導電體膜之形成例如可以藉由濺鍍來實施。之後，在導電體膜上塗布阻劑形成阻劑膜後，藉由實施曝光及現像而在和所要之輸入側電極30及輸出側電極40之形狀對應的區域以外之區域形成開口。之後，以形成有開口的阻劑膜作為遮罩使用例如藉由濕蝕刻，而如圖5及圖6所示，形成複數個由輸入側電極30與輸出側電極40形成之對。又，圖5及圖6表示和一對之輸入側電極30及輸出側電極40對應的區域。輸入側電極30及輸出側電極40中梳齒型電極之電極間隔，可以對應於應輸出的信號之頻率適當決定。
接著，實施作為工程(S90)的晶片化工程。該工程(S90)中，係將形成有複數個由輸入側電極30與輸出側電極40形成之對的積層體1沿厚度方向切斷，分離成為包含1對之輸入側電極30及輸出側電極40的複數個晶片。
之後，參照圖6及圖7，對工程(S90)中製作的晶片形成輸入側配線51及輸出側配線61，完成實施形態1之SAW元件100(SAW濾波器)。
參照圖7，本實施形態之SAW元件100具備：包含藉由凡德瓦力被結合的底材基板10與壓電體基板20的積層體1；具有以接觸壓電體基板20之露出主面21上的方式被形成的1對梳齒形狀的電極亦即輸入側電極30及輸出側電極40；連接於輸入側電極30的輸入側配線51；及連接於輸出側電極40的輸出側配線61。
輸入側電極30包含第1部分31與第2部分32。第1部分31包含：直線狀之底材部31A；及在和底材部31A之延伸方向垂直的方向由底材部31A突出的直線狀之複數個突出部31B。第2部分32包含：和底材部31A平行延伸的直線狀之底材部32A；及在和底材部32A之延伸方向垂直的方向由底材部32A突出，且進入相鄰的突出部31B之間的直線狀之複數個突出部32B。突出部31B與突出部32B隔開事先決定的一定之間隔配置。
輸出側電極40包含第1部分41與第2部分42。第1部分41包含：直線狀之底材部41A；及在和底 材部41A之延伸方向垂直的方向由底材部41A突出的直線狀之複數個突出部41B。第2部分42包含：和底材部41A呈平行延伸的直線狀之底材部42A；在和底材部42A之延伸方向呈垂直的方向由底材部42A突出，進入相鄰的突出部41B之間的直線狀之複數個突出部42B。突出部41B與突出部42B隔開事先決定的一定之間隔被配置。
當由輸入側配線51對輸入側電極30施加輸入信號之交流電壓時，藉由壓電效應而於壓電體基板20之露出主面21(表面)產生彈性表面波，傳送至輸出側電極40側。此時，如圖1所示，輸入側電極30及輸出側電極40具有梳齒形狀，突出部31B與突出部32B間之間隔以及突出部41B與突出部42B間之間隔一定。因此，由輸入側電極30朝向輸出側電極40的方向中，壓電體基板20之露出主面21之中形成有電極的區域存在著特定周期(電極周期)。因此，基於輸入信號而產生的彈性表面波在其波長與電極周期一致時被最強激振，隨著越偏離電極周期被衰減越大。結果，僅接近電極周期之波長之信號透過輸出側電極40及輸出側配線61被輸出。
於此，上述動作中壓電體基板20之溫度上昇。本實施形態之SAW元件100中，係將散熱性高的材料所形成之底材基板10以接觸壓電體基板20的方式配置。因此，SAW元件100具有高的可靠性。另外，本實施形態之SAW元件100中，壓電體基板20與底材基板10藉由充分的結合力結合。因此，SAW元件100成為具 有高可靠性的元件。
[實施例]
針對積層體中底材基板之支持主面之粗度及凹凸之存在狀態與接合強度間之關係進行調査實驗。實驗之方法如以下。
準備由多晶尖晶石形成之底材基板10，依據和上述實施形態同樣之順序製作SAW元件(實施例A、B及C)。又，作為底材基板10準備由多晶氧化鋁形成之底材基板10及準備由多晶莫來石形成之底材基板10，分別同樣地製作SAW元件(實施例D及E)。另外，作為比較之用而製作準備由多晶尖晶石形成之底材基板，在同樣之順序中省略工程(S50)者(比較例A~F)，準備由多晶氧化鋁形成之底材基板，在同樣之順序中省略工程(S50)者(比較例G及H)，準備由多晶莫來石形成之底材基板，在同樣之順序中省略工程(S50)者(比較例I及J)。在與壓電體基板之接合前針對底材基板之支持主面進行Sa(算術平均粗度)、Sq(均方根高度)、Sz(最大高度)之測定之同時，針對一邊50μm之正方形區域中1nm以上小於2nm的凹凸，2nm以上小於3nm的凹凸及3nm以上的凹凸之數目進行確認。粗度及凹凸之數目之確認係在支持主面之中央附近及外周附近之2處實施。接合後對接合狀態進行確認之同時，測定接合強度。接合強度係藉由裂縫寬度(crack opening)法測定。採用 由多晶尖晶石形成之底材基板時之實施例之實驗結果表示於表1，比較例之實驗結果表示於表2，採用由多晶氧化鋁形成之底材基板時之實施例及比較例之實驗結果表示於表3，採用由多晶莫來石形成之底材基板時之實施例及比較例之實驗結果表示於表4。又，表1~表4中，在最下段針對電極形成工程及晶片化工程可以良好實施者表示為「良好」，該工程中在積層體產生剝離者表示為「不良」。
參照表1，多晶尖晶石所形成之底材基板之支持主面之粗度Sa在0.01nm以上3.0nm以下，支持主面中一邊50μm之正方形區域中1nm以上的凹凸平均小於5個，而且2nm以上的凹凸平均小於1個之實施例A~C可以獲得0.5J/m2以上之接合強度，而且遍及主面之全面可以獲得良好的接合。另外，參照表2，在比較例A~F，底材基板之支持主面之粗度Sa在0.01nm以上3.0nm以下，但接合強度小，無法獲得良好的接合狀態。其原因推測為，在比較例A~F，一邊50μm之正方形區域中1nm以上的凹凸平均有5個以上，而在比較例A、D、E及F，一邊50μm之正方形區域中2nm以上的凹凸平均有1個以上。
又，參照表3，多晶氧化鋁所形成之底材基板之支持主面之粗度Sa在0.01nm以上3.0nm以下，支持主面中一邊50μm之正方形區域中1nm以上的凹凸平均小於5個，而且2nm以上的凹凸平均小於1個的實施例D，可以獲得0.5J/m2以上之接合強度，而且遍及主面之全面可以獲得良好的接合。另外，關於比較例G及H，雖然底材基板之支持主面之粗度Sa在0.01nm以上3.0nm以下，但是接合強度小，無法獲得良好的接合狀態。其原因推測為，和上述多晶尖晶石形成之底材基板時同樣地，在比較例G及H，一邊50μm之正方形區域中1nm以上的凹凸平均有5個以上，關於比較例H，一邊50μm之正方形區域中2nm以上的凹凸平均有1個以上。
另外，參照表4，多晶莫來石所形成之底材基板之支持主面之粗度Sa在0.01nm以上3.0nm以下，支持主面中一邊50μm之正方形區域中1nm以上的凹凸平均小於5個，而且2nm以上的凹凸平均小於1個之實施例E，可以獲得0.5J/m2以上之接合強度，而且遍及主面之全面可以獲得良好的接合。另外，在比較例I及J，雖然底材基板之支持主面之粗度Sa在0.01nm以上3.0nm以下，但接合強度小，無法獲得良好的接合狀態。其原因推測為，和上述多晶尖晶石形成之底材基板時同樣地，在比較例I及J，一邊50μm之正方形區域中1nm以上的凹凸平均有5個以上，在比較例J，2nm以上的凹凸平均有1個以上。
由以上之實驗結果可以確認，依據不僅從算術平均粗度之觀點而充分減少支持主面之粗度，就連支持主面上稀少存在的較大凹凸亦被減少的本發明之積層體，可以獲得壓電體基板與底材基板藉由充分的結合力被結合之積層體。
此次揭示的實施形態及實施例就全部之點而言僅為例示，並非用來限定者。本發明之範圍非由上述說明，而由申請專利範圍規定，亦包含和申請專利範圍具有均等意義及範圍內之全部變更。
1‧‧‧積層體
10‧‧‧底材基板
11‧‧‧支持主面
20‧‧‧壓電體基板
21‧‧‧露出主面
22‧‧‧結合主面

Claims (6)

  1. 一種陶瓷基板，係由多晶陶瓷構成，具有支持主面的陶瓷基板，上述支持主面之粗度Sa在0.01nm以上3.0nm以下，上述支持主面中，一邊50μm之正方形區域中1nm以上的凹凸平均小於5個，而且2nm以上的凹凸平均小於1個。
  2. 如申請專利範圍第1項之陶瓷基板，其中上述支持主面之粗度Sq在0.5nm以下。
  3. 如申請專利範圍第1或2項之陶瓷基板，其中上述多晶陶瓷係由尖晶石(Spinel)、氧化鋁、氧化鎂、二氧化矽、莫來石(Mullite)、堇青石(Cordierite)、氧化鈣、二氧化鈦、氮化矽、氮化鋁及碳化矽形成之群所選擇的1種以上之材料構成。
  4. 一種積層體，具備：如申請專利範圍第1至3項之中任一項之陶瓷基板；及壓電體基板，配置於上述支持主面上，由壓電體形成；上述陶瓷基板與上述壓電體基板係藉由凡德瓦力結合。
  5. 如申請專利範圍第4項之積層體，其中上述陶瓷基板與上述壓電體基板的接合強度在0.5J/m2以上。
  6. 一種SAW元件，具備：如申請專利範圍第4或5項之積層體；及電極，形成於上述壓電體基板之與上述陶瓷基板相反側的主面上。
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