WO2016159393A1 - セラミック基板、積層体およびsawデバイス - Google Patents

セラミック基板、積層体およびsawデバイス Download PDF

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WO2016159393A1
WO2016159393A1 PCT/JP2016/062959 JP2016062959W WO2016159393A1 WO 2016159393 A1 WO2016159393 A1 WO 2016159393A1 JP 2016062959 W JP2016062959 W JP 2016062959W WO 2016159393 A1 WO2016159393 A1 WO 2016159393A1
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substrate
ceramic substrate
main surface
roughness
average
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PCT/JP2016/062959
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English (en)
French (fr)
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慶一郎 下司
中山 茂
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住友電気工業株式会社
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Priority to DE112016006627.9T priority Critical patent/DE112016006627T5/de
Priority to KR1020167035330A priority patent/KR20170110500A/ko
Priority to JP2017510278A priority patent/JPWO2016159393A1/ja
Priority to US15/317,563 priority patent/US10340886B2/en
Priority to CN201680001823.3A priority patent/CN107406335B/zh
Priority to TW105113988A priority patent/TWI590393B/zh
Publication of WO2016159393A1 publication Critical patent/WO2016159393A1/ja

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Definitions

  • the present invention relates to a ceramic substrate, a laminate, and a SAW device, and more particularly to a ceramic substrate suitable for supporting a piezoelectric substrate, a laminate including a piezoelectric substrate and a ceramic substrate, and a SAW device including the laminate. It is.
  • a SAW device Surface Acoustic Wave Device
  • the SAW device has a function of taking out only an electric signal having a desired frequency from among inputted electric signals.
  • the SAW device has a structure in which electrodes are formed on a piezoelectric substrate.
  • the piezoelectric substrate is disposed on a base substrate made of a material with high heat dissipation.
  • a substrate made of single crystal sapphire As the base substrate, for example, a substrate made of single crystal sapphire can be adopted.
  • a substrate made of single crystal sapphire is employed as the base substrate, there is a problem that the manufacturing cost of the SAW device increases.
  • a ceramic substrate made of polycrystalline spinel is used as a base substrate, and a piezoelectric substrate and a ceramic substrate with reduced surface roughness Ra (arithmetic mean roughness) are combined by van der Waals force.
  • SAW devices have been proposed. Thereby, the manufacturing cost of a SAW device can be suppressed (for example, refer patent document 1).
  • the ceramic substrate according to the present disclosure is a ceramic substrate made of polycrystalline ceramic and having a main support surface.
  • the support main surface has a roughness Sa of 0.01 nm to 3.0 nm.
  • the number of irregularities of 1 nm or more in a square region having a side of 50 ⁇ m on average is less than 5, and the number of irregularities of 2 nm or more is less than 1 on average.
  • the ceramic substrate it is possible to provide a ceramic substrate that can be bonded to the piezoelectric substrate with a sufficient bonding force.
  • the ceramic substrate of the present application is a ceramic substrate made of polycrystalline ceramic and having a main support surface.
  • the support main surface has a roughness Sa of 0.01 nm to 3.0 nm.
  • the number of irregularities of 1 nm or more in a square region having a side of 50 ⁇ m on average is less than 5, and the number of irregularities of 2 nm or more is less than 1 on average.
  • the inventors of the present invention cause a case where the bonding force becomes insufficient when the piezoelectric substrate and the ceramic substrate (base substrate) having a reduced arithmetic average roughness of the surface are bonded by van der Waals force.
  • the bonding force is insufficient. That is, in order to obtain a sufficient bonding force, not only the roughness is sufficiently reduced in terms of arithmetic average roughness (in terms of average roughness), but also the large unevenness that is rarely present as described above. Need to be reduced.
  • the ceramic substrate of the present application when the roughness of the main support surface is 0.01 nm to 3.0 nm in Sa, the surface roughness from the viewpoint of arithmetic average roughness is sufficiently reduced. Furthermore, in the ceramic substrate of the present application, the number of irregularities of 1 nm or more in the square region of 50 ⁇ m on one side of the main support surface is less than 5 on average and the number of irregularities of 2 nm or more is less than 1 on average. That is, in the ceramic substrate of the present application, not only the roughness of the support main surface is sufficiently reduced from the viewpoint of arithmetic average roughness, but also large irregularities that rarely exist on the support main surface are reduced. As a result, according to the ceramic substrate of the present application, it is possible to provide a ceramic substrate that can be bonded to the piezoelectric substrate with a sufficient bonding force.
  • the main support surface may have a roughness of Sq of 0.5 nm or less. By doing so, a sufficient bonding force with the piezoelectric substrate is more reliably ensured.
  • the ceramic substrate includes spinel (MgAl 2 O 4 ), alumina (Al 2 O 3 ), magnesia (MgO), silica (SiO 2 ), mullite (3Al 2 O 3 .2SiO 2 ), cordierite (2MgO ⁇ 2Al 2).
  • One or more materials selected from the group consisting of O 3 ⁇ 5SiO 2 ), calcia (CaO), titania (TiO 2 ), silicon nitride (Si 3 N 4 ), aluminum nitride (AlN), and silicon carbide (SiC) You may be comprised with the polycrystalline ceramic which consists of. These materials are suitable as materials constituting the ceramic substrate of the present application.
  • the laminate of the present application includes the ceramic substrate and a piezoelectric substrate that is disposed on the main support surface and is made of a piezoelectric material.
  • the ceramic substrate and the piezoelectric substrate are bonded together by van der Waals force.
  • the laminated body of the present application not only the roughness of the support main surface is sufficiently reduced in terms of arithmetic average roughness, but also the ceramic substrate and piezoelectric element in which large irregularities that are rarely present on the support main surface are reduced.
  • the body substrate is coupled to the body substrate by van der Waals force. Therefore, according to the laminate of the present application, it is possible to provide a laminate in which the piezoelectric substrate and the ceramic substrate are bonded with a sufficient bonding force.
  • the bonding strength between the ceramic substrate and the piezoelectric substrate may be 0.5 J / m 2 or more. By doing so, the piezoelectric substrate and the ceramic substrate are more reliably coupled.
  • the bonding force between the piezoelectric substrate and the ceramic substrate is less than 0.5 J / m 2 , the substrate may be peeled off or applied in the electrode forming process or the chip forming process performed in the manufacture of the SAW device.
  • the bonding strength between the ceramic substrate and the piezoelectric substrate is 1.0 J / m 2 or more, 1.3 J / m 2 or more, Furthermore, it is more preferable that it is 1.5 J / m 2 or more.
  • the SAW device of the present application includes the laminate of the present application and an electrode formed on the main surface of the piezoelectric substrate opposite to the ceramic substrate.
  • the SAW device of the present application includes the laminate of the present application in which a piezoelectric substrate and a ceramic substrate made of polycrystalline ceramic are bonded with a sufficient bonding force. Therefore, it is possible to provide a SAW device in which the piezoelectric substrate and the ceramic substrate are bonded with a sufficient bonding force while suppressing the manufacturing cost.
  • roughness Sa, Sq, and Sz mean arithmetic mean height Sa, root mean square height Sq, and maximum height Sz based on ISO25178, respectively.
  • surface roughness parameters can be measured using, for example, a three-dimensional surface roughness measuring instrument.
  • laminated body 1 in the present embodiment includes a base substrate 10 and a piezoelectric substrate 20 as ceramic substrates.
  • the piezoelectric substrate 20 is made of a piezoelectric material such as lithium tantalate (LiTaO 3 ) or lithium niobate (LiNbO 3 ).
  • the base substrate 10 is made of one or more materials selected from the group consisting of spinel, alumina, magnesia, silica, mullite, cordierite, calcia, titania, silicon nitride, aluminum nitride and silicon carbide, preferably any one material. Made of polycrystalline ceramic.
  • the base substrate 10 has a support main surface 11.
  • the piezoelectric substrate 20 has an exposed main surface 21 that is one main surface and a coupling main surface 22 that is a main surface opposite to the exposed main surface 21.
  • the piezoelectric substrate 20 is disposed so as to be in contact with the support main surface 11 of the base substrate 10 at the coupling main surface 22.
  • the base substrate 10 and the piezoelectric substrate 20 are coupled by van der Waals force.
  • the support main surface 11 of the base substrate 10 has a roughness Sa of 0.01 nm to 3.0 nm. Further, in the main support surface 11, the number of irregularities of 1 nm or more in a square region having a side of 50 ⁇ m on average is less than 5, and the number of irregularities of 2 nm or more is less than 1 on average.
  • the roughness of the support main surface 11 is set to 0.01 nm to 3.0 nm in Sa, so that the surface roughness from the viewpoint of arithmetic average roughness is sufficiently reduced. Furthermore, in the laminated body 1, the unevenness
  • the unevenness of 1 nm or more is an unevenness in which the average surface (average height) is calculated in the measurement region (a square region having a side of 50 ⁇ m) and the distance from the average surface to the apex (or the bottom) is 1 nm or more.
  • the unevenness of 2 nm or more is an unevenness in which the average surface (average height) is calculated in the measurement region (a square region having a side of 50 ⁇ m), and the distance from the average surface to the apex (or the bottom) is 2 nm or more.
  • the number of irregularities is counted with a microscope or the like in a plurality of measurement regions (a square region having a side of 50 ⁇ m) on the main support surface 11, and the average value is taken as the average number of irregularities.
  • the roughness of the support main surface is preferably 2.0 nm or less, preferably 1.0 nm or less, in Sa. Is more preferable. Further, the unevenness of 1 nm or more in the square region having a side of 50 ⁇ m on one side of the support main surface 11 is preferably less than 4 on average, more preferably less than 3, and further preferably less than 2. .
  • the support main surface 11 preferably has a roughness Sq of 0.5 nm or less. Thereby, sufficient coupling force between the piezoelectric substrate 20 and the base substrate 10 is ensured more reliably.
  • the bonding strength between the base substrate 10 and the piezoelectric substrate 20 is preferably 0.5 J / m 2 or more. Thereby, the piezoelectric substrate 20 and the base substrate 10 are more reliably coupled.
  • a base substrate preparation step is first performed as a step (S ⁇ b> 10).
  • this step (S10) referring to FIG. 3, one or more materials selected from the group consisting of spinel, alumina, magnesia, silica, mullite, cordierite, calcia, titania, silicon nitride, aluminum nitride and silicon carbide
  • a base substrate 10 made of a polycrystalline ceramic is prepared.
  • a base substrate 10 made of a polycrystalline ceramic composed of any one material selected from the above group is prepared.
  • a magnesia powder and an alumina powder are mixed to prepare a raw material powder, and a molded body is manufactured by molding.
  • the molded body can be manufactured by performing CIP (Cold Isostatic Press) after preforming, for example, by press molding.
  • CIP Cold Isostatic Press
  • a sintering process is implemented with respect to a molded object.
  • the sintering treatment can be performed by a method such as vacuum sintering or HIP (Hot Isostatic Press). Thereby, a sintered compact is obtained.
  • the base substrate 10 having a desired shape (thickness) is obtained by performing dicing on the sintered body (see FIG. 3).
  • a first polishing step is performed as a step (S20).
  • step (S20) referring to FIG. 3, rough polishing is performed on support main surface 11 of base substrate 10 prepared in step (S10). Specifically, for example, rough grinding is performed on the main support surface 11 using a GC (Green Silicon Carbide) grindstone whose abrasive grain number is # 800 to # 2000.
  • GC Green Silicon Carbide
  • a second polishing step is performed as a step (S30).
  • this step (S30) normal polishing is performed on the main support surface 11 on which rough polishing has been performed in step (S20).
  • the support main surface 11 is usually polished using a diamond grindstone having an abrasive grain diameter of 3 to 5 ⁇ m.
  • a third polishing step is performed as a step (S40).
  • final polishing is performed on the main support surface 11 that has been normally polished in step (S30).
  • finish polishing is performed on support main surface 11 using, for example, diamond abrasive grains having a particle size of 0.5 to 1.0 ⁇ m.
  • the roughness of the support main surface 11 of 0.01 nm or more and 3.0 nm or less can be achieved by Sa.
  • scratches due to diamond abrasive grains are generated on the main support surface 11. Therefore, although the roughness of 0.01 nm or more and 3.0 nm or less is achieved by Sa in the support main surface 11, there are large irregularities due to scratches.
  • a fourth polishing step is performed as a step (S50).
  • scratch scratch removal polishing is performed on the main support surface 11 that has been subjected to final polishing in step (S40).
  • a slight polishing amount of CMP is performed on the support main surface 11.
  • the amount of polishing by CMP is about several hundred nm.
  • a bonding step is performed as a step (S60).
  • the base substrate 10 having the main support surface 11 polished in steps (S20) to (S50) and the separately prepared piezoelectric substrate 20 are bonded together.
  • a piezoelectric substrate 20 made of a piezoelectric material such as lithium tantalate or lithium niobate is prepared, and the bonding main surface 22 of the piezoelectric substrate 20 and the base substrate 10 are The base substrate 10 and the piezoelectric substrate 20 are bonded together so that the main support surface 11 is in contact.
  • the base substrate 10 and the piezoelectric substrate 20 are coupled by van der Waals force.
  • the laminated body 1 of this Embodiment is obtained.
  • the laminate 1 in which the piezoelectric substrate 20 and the base substrate 10 are bonded with a sufficient bonding force is manufactured.
  • a thickness reduction process is implemented as process (S70) following process (S60).
  • process (S70) referring to FIG. 1 and FIG. 4, a process for reducing the thickness of piezoelectric substrate 20 of laminate 1 obtained in step (S60) is performed. Specifically, for example, a grinding process is performed on the exposed main surface 21 of the piezoelectric substrate 20. Thereby, the thickness of the piezoelectric substrate 20 is reduced to a thickness suitable for the SAW device.
  • an electrode forming step is performed as a step (S80).
  • this step (S80) referring to FIGS. 4 to 6, comb-shaped electrodes are formed on the exposed main surface 21 of the piezoelectric substrate 20.
  • FIG. 5 is a sectional view taken along line VV in FIG.
  • a conductor film made of a conductor such as Al is formed on exposed main surface 21 of piezoelectric substrate 20 that has been adjusted to an appropriate thickness in step (S70). It is formed.
  • the conductor film can be formed, for example, by sputtering.
  • a chip forming process is performed as a process (S90).
  • the laminated body 1 in which a plurality of pairs of the input side electrode 30 and the output side electrode 40 are formed is cut in the thickness direction, whereby a pair of the input side electrode 30 and the output side electrode A plurality of chips including 40 are separated.
  • input side wiring 51 and output side wiring 61 are formed on the chip manufactured in step (S90), so that SAW device 100 (SAW device 100) according to the first embodiment is formed. Filter) is completed.
  • SAW device 100 includes laminated body 1 including base substrate 10 and piezoelectric substrate 20 bonded by van der Waals force, and exposed main surface 21 of piezoelectric substrate 20.
  • the input side electrode 30 and the output side electrode 40 which are electrodes having a pair of comb teeth formed so as to be in contact with each other, the input side wiring 51 connected to the input side electrode 30, and the output side electrode 40
  • the output side wiring 61 connected is provided.
  • the input side electrode 30 includes a first portion 31 and a second portion 32.
  • the first portion 31 includes a linear base portion 31A and a plurality of linear protruding portions 31B protruding from the base portion 31A in a direction perpendicular to the extending direction of the base portion 31A.
  • the second portion 32 protrudes from the base portion 32A in a direction perpendicular to the extending direction of the base portion 32A, and enters between the adjacent protruding portions 31B.
  • the linear base portion 32A extends in parallel with the base portion 31A.
  • a plurality of linear protrusions 32B are arranged at a predetermined fixed interval.
  • the output side electrode 40 includes a first portion 41 and a second portion 42.
  • the first portion 41 includes a linear base portion 41A and a plurality of linear protrusion portions 41B protruding from the base portion 41A in a direction perpendicular to the extending direction of the base portion 41A.
  • the second portion 42 protrudes from the base portion 42A in a direction perpendicular to the extending direction of the base portion 42A, and enters between the adjacent protruding portions 41B.
  • the linear base portion 42A extends in parallel with the base portion 41A. And a plurality of linear protrusions 42B.
  • the protrusion 41B and the protrusion 42B are arranged at a predetermined constant interval.
  • the input side electrode 30 and the output side electrode 40 have a comb-teeth shape as shown in FIG. 1, and the interval between the protruding portion 31B and the protruding portion 32B and the interval between the protruding portion 41B and the protruding portion 42B. Is constant.
  • the region where the electrode is formed on the exposed main surface 21 of the piezoelectric substrate 20 exists at a predetermined cycle (electrode cycle). Therefore, the surface acoustic wave generated by the input signal is most strongly excited when the wavelength matches the electrode period, and attenuates as the deviation from the electrode period increases. As a result, only a signal having a wavelength close to the electrode period is output via the output side electrode 40 and the output side wiring 61.
  • the temperature of the piezoelectric substrate 20 rises.
  • the base substrate 10 made of a material with high heat dissipation is disposed in contact with the piezoelectric substrate 20. Therefore, the SAW device 100 has high reliability. Furthermore, in the SAW device 100 of the present embodiment, the piezoelectric substrate 20 and the base substrate 10 are bonded with a sufficient bonding force. Therefore, the SAW device 100 is a highly reliable device.
  • a base substrate 10 made of polycrystalline spinel was prepared, and a SAW device was fabricated in the same procedure as in the above embodiment. (Examples A, B and C).
  • a base substrate 10 made of polycrystalline alumina and a base substrate 10 made of polycrystalline mullite were prepared as the base substrate 10, and SAW devices were produced in the same manner (Examples D and E).
  • a base substrate made of polycrystalline spinel was prepared, and in the same procedure, the step (S50) was omitted (Comparative Examples A to F), and a base substrate made of polycrystalline alumina was prepared.
  • Table 1 shows the experimental results of the examples when the base substrate made of polycrystalline spinel is adopted
  • Table 2 shows the experimental results of the comparative examples
  • Table 3 shows the experimental results of Examples and Comparative Examples when a base substrate made of polycrystalline mullite was employed.
  • Tables 1 to 4 regarding the lowest stage, “good” is obtained when the electrode forming process and the chip forming process can be performed satisfactorily, and “bad” when the laminate is peeled off in the process. Is displayed.
  • the roughness of the support main surface of the base substrate made of polycrystalline spinel is 0.01 nm or more and 3.0 nm or less in Sa, and the support main surface has an unevenness of 1 nm or more in a square region having a side of 50 ⁇ m.
  • Examples A to C in which the average is less than 5 and the unevenness of 2 nm or more is less than 1 on average, a bonding strength of 0.5 J / m 2 or more is obtained and the entire main surface is covered. Good bonding is obtained.
  • Comparative Examples A to F although the roughness of the main support surface of the base substrate is 0.01 nm or more and 3.0 nm or less in Sa, the bonding strength is small and the bonding state is good. Is not obtained. This is because, in Comparative Examples A to F, the average irregularity of 1 nm or more in a square region having a side of 50 ⁇ m was 5 or more on average, and in Comparative Examples A, D, E, and F, in a square region having a side of 50 ⁇ m. It is considered that the reason is that there were 1 or more irregularities of 2 nm or more on average.
  • the roughness of the main support surface of the base substrate made of polycrystalline alumina is 0.01 nm to 3.0 nm in Sa, and the support main surface has a roughness of 1 nm or more in a square region having a side of 50 ⁇ m. less than five irregularities on average, and for example D 2 nm or more irregularities is less than one on average, 0.5 J / m 2 or more bonding strength is obtained, and the entire surface of the main surface Good bonding is obtained.
  • Comparative Examples G and H although the roughness of the support main surface of the base substrate is 0.01 nm or more and 3.0 nm or less in Sa, the bonding strength is small and a good bonding state is not obtained.
  • the roughness of the support main surface of the base substrate made of polycrystalline mullite is 0.01 nm or more and 3.0 nm or less in Sa, and 1 nm or more in a square region having a side of 50 ⁇ m on the support main surface. less than five irregularities on average, and for example E 2 nm or more irregularities is less than one on average, 0.5 J / m 2 or more bonding strength is obtained, and the entire surface of the main surface Good bonding is obtained.
  • Comparative Examples I and J although the roughness of the main support surface of the base substrate is 0.01 nm or more and 3.0 nm or less in Sa, the bonding strength is small and a good bonding state is not obtained.
  • Comparative Examples I and J had an average of 5 or more irregularities of 1 nm or more in a square region with a side of 50 ⁇ m. Is considered to be caused by an average of 1 or more irregularities of 2 nm or more.
  • the laminate of the present application not only the roughness of the main support surface is sufficiently reduced in terms of arithmetic average roughness, but also the large unevenness that rarely exists on the main support surface is reduced. For example, it is confirmed that a laminated body in which the piezoelectric substrate and the base substrate are bonded with a sufficient bonding force can be obtained.

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Abstract

 セラミック基板は、多結晶セラミックから構成され、支持主面を有する。支持主面は、粗さがSaで0.01nm以上3.0nm以下である。支持主面において、一辺50μmの正方形領域における1nm以上の凹凸が平均で5個未満、かつ2nm以上の凹凸が平均で1個未満である。

Description

セラミック基板、積層体およびSAWデバイス
 本発明はセラミック基板、積層体およびSAWデバイスに関し、より特定的には圧電体基板の支持に適したセラミック基板、圧電体基板とセラミック基板とを含む積層体および当該積層体を含むSAWデバイスに関するものである。
 携帯電話機などの通信機器の内部には、電気信号に含まれるノイズを除去する目的で、SAWデバイス(Surface Acoustic Wave Device;表面弾性波素子)が配置される。SAWデバイスは、入力された電気信号のうち、所望の周波数の電気信号のみを取り出す機能を有する。SAWデバイスは、圧電体基板上に電極が形成された構造を有する。そして、使用時の放熱を目的として、圧電体基板は放熱性の高い材料からなるベース基板上に配置される。
 ベース基板としては、たとえば単結晶サファイアからなる基板を採用することができる。しかし、単結晶サファイアからなる基板をベース基板として採用すると、SAWデバイスの製造コストが上昇するという問題がある。これに対し、ベース基板として多結晶スピネルからなるセラミック基板を採用し、圧電体基板と表面粗さRa(算術平均粗さ)を低減したセラミック基板とをファンデルワールス力により結合させた構造を有するSAWデバイスが提案されている。これにより、SAWデバイスの製造コストを抑制することができる(たとえば、特許文献1参照)。
特開2011-66818号公報
 本開示に従ったセラミック基板は、多結晶セラミックから構成され、支持主面を有するセラミック基板である。支持主面は、粗さがSaで0.01nm以上3.0nm以下である。支持主面において、一辺50μmの正方形領域における1nm以上の凹凸が平均で5個未満、かつ2nm以上の凹凸が平均で1個未満である。
セラミック基板および圧電体基板を含む積層体の構造を示す概略断面図である。 セラミック基板、積層体およびSAWデバイスの製造方法の概略を示すフローチャートである。 セラミック基板、積層体およびSAWデバイスの製造方法を説明するための概略断面図である。 積層体およびSAWデバイスの製造方法を説明するための概略断面図である。 積層体およびSAWデバイスの製造方法を説明するための概略断面図である。 積層体およびSAWデバイスの製造方法を説明するための概略図である。 SAWデバイスの構造を示す概略図である。
[本開示が解決しようとする課題]
 SAWデバイスの製造コストをさらに低減するために、圧電体基板とセラミック基板との結合力を一層増大させることが求められている。そこで、圧電体基板と十分な結合力で結合することが可能なセラミック基板、圧電体基板とセラミック基板とが十分な結合力で結合した積層体、および当該積層体を含むSAWデバイスを提供することを目的の1つとする。
[本開示の効果]
 上記セラミック基板によれば、圧電体基板と十分な結合力で結合することが可能なセラミック基板を提供することができる。
 [本願発明の実施形態の説明]
 最初に本願発明の実施態様を列記して説明する。本願のセラミック基板は、多結晶セラミックから構成され、支持主面を有するセラミック基板である。支持主面は、粗さがSaで0.01nm以上3.0nm以下である。支持主面において、一辺50μmの正方形領域における1nm以上の凹凸が平均で5個未満、かつ2nm以上の凹凸が平均で1個未満である。
 本発明者らは、圧電体基板と表面の算術平均粗さを低減したセラミック基板(ベース基板)とをファンデルワールス力により結合させた場合に、結合力が不十分となる場合が発生する原因について検討を行った。その結果、算術平均粗さの観点において十分に粗さが低減されている場合であっても、大きな凹凸、具体的には1nm以上の凹凸が一辺50μmの正方形領域内に5個以上存在する場合、または2nm以上の凹凸が一辺50μmの正方形領域内に1個以上存在する場合、結合力が不十分となることを見出した。すなわち、十分な結合力を得るためには、算術平均粗さの観点(平均的な粗さの観点)において十分に粗さを低減するだけでなく、上記のような稀に存在する大きな凹凸をも低減する必要がある。
 本願のセラミック基板においては、支持主面の粗さがSaで0.01nm以上3.0nm以下とされることにより、算術平均粗さの観点からの表面粗さが十分に低減される。さらに、本願のセラミック基板においては、支持主面の一辺50μmの正方形領域における1nm以上の凹凸が平均で5個未満、かつ2nm以上の凹凸が平均で1個未満とされる。すなわち、本願のセラミック基板においては、算術平均粗さの観点において十分に支持主面の粗さが低減されるだけでなく、支持主面に稀に存在する大きな凹凸も低減されている。その結果、本願のセラミック基板によれば、圧電体基板と十分な結合力で結合することが可能なセラミック基板を提供することができる。
 上記セラミック基板において、支持主面は、粗さがSqで0.5nm以下であってもよい。このようにすることにより、圧電体基板との間の十分な結合力がより確実に確保される。
 上記セラミック基板は、スピネル(MgAl)、アルミナ(Al)、マグネシア(MgO)、シリカ(SiO)、ムライト(3Al・2SiO)、コージェライト(2MgO・2Al・5SiO)、カルシア(CaO)、チタニア(TiO)、窒化珪素(Si)、窒化アルミニウム(AlN)および炭化珪素(SiC)からなる群から選択される1種以上の材料からなる多結晶セラミックで構成されていてもよい。これらの材料は、本願のセラミック基板を構成する材料として好適である。
 本願の積層体は、上記セラミック基板と、支持主面上に配置され、圧電体からなる圧電体基板と、を備える。セラミック基板と圧電体基板とは、ファンデルワールス力により結合されている。
 本願の積層体においては、算術平均粗さの観点において十分に支持主面の粗さが低減されるだけでなく、支持主面に稀に存在する大きな凹凸も低減されている上記セラミック基板と圧電体基板とが、ファンデルワールス力により結合されている。そのため、本願の積層体によれば、圧電体基板とセラミック基板とが十分な結合力で結合した積層体を提供することができる。
 上記積層体において、セラミック基板と圧電体基板との接合強度が0.5J/m以上であってもよい。このようにすることにより、圧電体基板とセラミック基板とがより確実に結合される。圧電体基板とセラミック基板との結合力が0.5J/m未満の場合、SAWデバイスの製造において実施される電極形成工程やチップ化工程において基板の剥離、かけなどが発生するおそれがある。さらに確実な圧電体基板とセラミック基板との結合を達成する観点から、セラミック基板と圧電体基板との接合強度は1.0J/m以上であることが好ましく、1.3J/m以上、さらには1.5J/m以上であることがより好ましい。
 本願のSAWデバイスは、上記本願の積層体と、圧電体基板のセラミック基板とは反対側の主面上に形成される電極と、を備える。本願のSAWデバイスは、圧電体基板と多結晶セラミックからなるセラミック基板とが十分な結合力で結合した本願の積層体を含む。そのため、製造コストを抑制しつつ、圧電体基板とセラミック基板とが十分な結合力で結合したSAWデバイスを提供することができる。
 なお、粗さSa、SqおよびSzとは、それぞれ、ISO25178に基づく算術平均高さSa、二乗平均平方根高さSqおよび最大高さSzを意味する。これらの表面粗さのパラメータは、たとえば、3次元表面粗さ測定器を用いて測定できる。
 [本願発明の実施形態の詳細]
 次に、本発明にかかるセラミック基板および積層体の一実施の形態を、以下に図面を参照しつつ説明する。なお、以下の図面において同一または相当する部分には同一の参照番号を付しその説明は繰返さない。
 図1を参照して、本実施の形態における積層体1は、セラミック基板としてのベース基板10と圧電体基板20とを備える。圧電体基板20は、たとえばタンタル酸リチウム(LiTaO)、ニオブ酸リチウム(LiNbO)などの圧電体からなる。ベース基板10は、スピネル、アルミナ、マグネシア、シリカ、ムライト、コージェライト、カルシア、チタニア、窒化珪素、窒化アルミニウムおよび炭化珪素からなる群から選択される一種以上、好ましくはいずれか1つの材料から構成される多結晶セラミックからなる。
 ベース基板10は、支持主面11を有する。圧電体基板20は、一方の主面である露出主面21と、露出主面21とは反対側の主面である結合主面22とを有する。圧電体基板20は、ベース基板10の支持主面11に結合主面22において接触するように配置される。ベース基板10と圧電体基板20とは、ファンデルワールス力により結合されている。
 ベース基板10の支持主面11は、粗さがSaで0.01nm以上3.0nm以下となっている。また、支持主面11において、一辺50μmの正方形領域における1nm以上の凹凸は平均で5個未満、かつ2nm以上の凹凸が平均で1個未満である。
 積層体1においては、支持主面11の粗さがSaで0.01nm以上3.0nm以下とされることにより、算術平均粗さの観点からの表面粗さが十分に低減されている。さらに、積層体1においては、支持主面11の一辺50μmの正方形領域における1nm以上の凹凸が平均で5個未満、かつ2nm以上の凹凸が平均で1個未満とされる。すなわち、積層体1においては、算術平均粗さの観点において十分に粗さが低減されるだけでなく、稀に存在する大きな凹凸も低減されている。その結果、積層体1は、圧電体基板20とベース基板10とが十分な結合力で結合した積層体となっている。
 なお、本願において1nm以上の凹凸とは、測定領域(一辺50μmの正方形領域)において平均面(平均高さ)を算出し、当該平均面から頂点(または底)までの距離が1nm以上である凹凸を意味する。同様に、2nm以上の凹凸とは、測定領域(一辺50μmの正方形領域)において平均面(平均高さ)を算出し、当該平均面から頂点(または底)までの距離が2nm以上である凹凸を意味する。支持主面11において複数の測定領域(一辺50μmの正方形領域)で凹凸の数を顕微鏡などでカウントし、その平均値を平均での凹凸の数とする。
 圧電体基板20とベース基板10との間の十分な結合力をより確実に得る観点から、支持主面の粗さはSaで2.0nm以下とすることが好ましく、1.0nm以下とすることがより好ましい。また、支持主面11の一辺50μmの正方形領域における1nm以上の凹凸は、平均で4個未満とすることが好ましく、3個未満とすることがより好ましく、さらには2個未満とすることが好ましい。
 支持主面11は、粗さがSqで0.5nm以下であることが好ましい。これにより、圧電体基板20とベース基板10との間の十分な結合力がより確実に確保される。
 ベース基板10と圧電体基板20との接合強度は0.5J/m以上であることが好ましい。これにより、圧電体基板20とベース基板10とがより確実に結合される。
 次に、本実施の形態におけるセラミック基板としてのベース基板10、積層体1および積層体1を用いたSAWデバイスの製造方法を説明する。図2を参照して、本実施の形態のベース基板10、積層体1およびSAWデバイスの製造方法では、まず工程(S10)としてベース基板準備工程が実施される。この工程(S10)では、図3を参照してスピネル、アルミナ、マグネシア、シリカ、ムライト、コージェライト、カルシア、チタニア、窒化珪素、窒化アルミニウムおよび炭化珪素からなる群から選択される1種以上の材料から構成される多結晶セラミックからなるベース基板10が準備される。たとえば、上記群から選択されるいずれか1つの材料から構成される多結晶セラミックからなるベース基板10が準備される。具体的には、たとえば多結晶スピネルからなるベース基板10を準備する場合、マグネシア粉末とアルミナ粉末とを混合して原料粉末を準備し、成形することにより成形体を作製する。成形体は、たとえばプレス成形により予備成形を実施した後、CIP(Cold Isostatic Press)を実施することにより作製することができる。次に、成形体に対して焼結処理を実施する。焼結処理は、たとえば真空焼結法、HIP(Hot Isostatic Press)などの方法により実施することができる。これにより、焼結体が得られる。その後、焼結体に対してダイシング加工を実施することにより、所望の形状(厚み)を有するベース基板10が得られる(図3参照)。
 次に、工程(S20)として第1研磨工程が実施される。この工程(S20)では、図3を参照して、工程(S10)において準備されたベース基板10の支持主面11に対して粗研磨が実施される。具体的には、たとえば砥粒の番手が#800~#2000のGC(Green Silicon Carbide)砥石を用いて支持主面11に対して粗研磨を実施する。
 次に、工程(S30)として第2研磨工程が実施される。この工程(S30)では、工程(S20)において粗研磨が実施された支持主面11に対して通常研磨が実施される。具体的には、たとえば砥粒の粒径が3~5μmのダイヤモンド砥石用いて支持主面11に対して通常研磨を実施する。
 次に、工程(S40)として第3研磨工程が実施される。この工程(S40)では、工程(S30)において通常研磨が実施された支持主面11に対して仕上げ研磨が実施される。具体的には、たとえば粒径が0.5~1.0μmのダイヤモンド砥粒を用いて支持主面11に対して仕上げ研磨を実施する。これにより、Saで0.01nm以上3.0nm以下の支持主面11の粗さを達成することができる。しかし、支持主面11にはダイヤモンド砥粒によるスクラッチ傷が発生する。そのため、支持主面11においてはSaで0.01nm以上3.0nm以下の粗さが達成されているものの、スクラッチ傷に起因する大きな凹凸が存在する。
 次に、工程(S50)として第4研磨工程が実施される。この工程(S50)では、工程(S40)において仕上げ研磨が実施された支持主面11に対してスクラッチ傷除去研磨が実施される。具体的には、たとえば支持主面11に対してわずかな研磨量のCMP(Chemical Mechanical Polishing)を実施する。CMPによる研磨量は、数百nm程度とされる。これにより、支持主面11の粗さをSaで0.01nm以上3.0nm以下に維持しつつ、支持主面11において、一辺50μmの正方形領域における1nm以上の凹凸を平均で5個未満、かつ2nm以上の凹凸を平均で1個未満とすることができる。これにより、本実施の形態におけるセラミック基板としてのベース基板10が完成する。
 次に、工程(S60)として貼り合わせ工程が実施される。この工程(S60)では、工程(S20)~(S50)において支持主面11が研磨されたベース基板10と、別途準備された圧電体基板20とが貼り合わされる。具体的には、図3および図1を参照して、タンタル酸リチウム、ニオブ酸リチウムなどの圧電体からなる圧電体基板20が準備され、圧電体基板20の結合主面22とベース基板10の支持主面11とが接触するように、ベース基板10と圧電体基板20とが貼り合わされる。これにより、ベース基板10と圧電体基板20とは、ファンデルワールス力により結合する。その結果、本実施の形態の積層体1が得られる。
 ここで、本実施の形態においては、算術平均粗さの観点において十分に支持主面11の粗さが低減されるだけでなく、支持主面11に稀に存在する大きな凹凸(スクラッチ傷)も低減されている。その結果、上記積層体1の製造方法によれば、圧電体基板20とベース基板10とが十分な結合力で結合した積層体1が製造される。
 引き続き、積層体1を用いたSAWデバイスの製造方法について説明する。図2を参照して、工程(S60)に続いて、工程(S70)として減厚工程が実施される。この工程(S70)では、図1および図4を参照して、工程(S60)において得られた積層体1の圧電体基板20の厚みを小さくする加工が実施される。具体的には、たとえば圧電体基板20の露出主面21に対して研削処理が実施される。これにより、圧電体基板20の厚みが、SAWデバイスに適した厚みにまで低減される。
 次に、工程(S80)として電極形成工程が実施される。この工程(S80)では、図4~図6を参照して、圧電体基板20の露出主面21に櫛歯型の電極が形成される。図5は、図6の線分V-Vに沿う断面図である。具体的には、図5および図6を参照して、工程(S70)において適切な厚みに調整された圧電体基板20の露出主面21上に、Alなどの導電体からなる導電体膜が形成される。導電体膜の形成は、たとえばスパッタリングにより実施することができる。その後、導電体膜上にレジストが塗布されてレジスト膜が形成された後、露光および現像が実施されることにより、所望の入力側電極30および出力側電極40の形状に対応する領域以外の領域に開口が形成される。そして、開口が形成されたレジスト膜をマスクとして用いて、たとえばウェットエッチングを実施することにより、図5および図6に示すように入力側電極30と出力側電極40とからなる対が複数形成される。なお、図5および図6は、一対の入力側電極30および出力側電極40に対応する領域を表している。入力側電極30および出力側電極40における櫛歯型電極の電極間隔は、出力すべき信号の周波数に応じて適宜決定することができる。
 次に、工程(S90)としてチップ化工程が実施される。この工程(S90)では、入力側電極30と出力側電極40とからなる対が複数形成された積層体1が厚さ方向に切断されることにより、1対の入力側電極30および出力側電極40を含む複数のチップに分離される。
 その後、図6および図7を参照して、工程(S90)において作製されたチップに対して入力側配線51および出力側配線61が形成されることにより、実施の形態1におけるSAWデバイス100(SAWフィルター)が完成する。
 図7を参照して、本実施の形態におけるSAWデバイス100は、ファンデルワールス力により結合されたベース基板10と圧電体基板20とを含む積層体1と、圧電体基板20の露出主面21上に接触するように形成された1対の櫛歯形状を有する電極である入力側電極30および出力側電極40と、入力側電極30に接続された入力側配線51と、出力側電極40に接続された出力側配線61とを備えている。
 入力側電極30は、第1部分31と第2部分32とを含む。第1部分31は、直線状のベース部31Aと、ベース部31Aの延在方向に垂直な方向にベース部31Aから突出する直線状の複数の突出部31Bとを含む。第2部分32は、ベース部31Aと平行に延在する直線状のベース部32Aと、ベース部32Aの延在方向に垂直な方向にベース部32Aから突出し、隣り合う突出部31Bの間に進入する直線状の複数の突出部32Bとを含む。突出部31Bと突出部32Bとは、予め定められた一定の間隔をおいて配置される。
 出力側電極40は、第1部分41と第2部分42とを含む。第1部分41は、直線状のベース部41Aと、ベース部41Aの延在方向に垂直な方向にベース部41Aから突出する直線状の複数の突出部41Bとを含む。第2部分42は、ベース部41Aと平行に延在する直線状のベース部42Aと、ベース部42Aの延在方向に垂直な方向にベース部42Aから突出し、隣り合う突出部41Bの間に進入する直線状の複数の突出部42Bとを含む。突出部41Bと突出部42Bとは、予め定められた一定の間隔をおいて配置される。
 入力側配線51から入力側電極30に入力信号である交流電圧が印加されると、圧電効果により圧電体基板20の露出主面21(表面)に弾性表面波が生じ、出力側電極40側に伝達される。このとき、入力側電極30および出力側電極40は図1に示すように櫛歯形状を有しており、突出部31Bと突出部32Bとの間隔、および突出部41Bと突出部42Bとの間隔は一定である。したがって、入力側電極30から出力側電極40に向かう方向において、圧電体基板20の露出主面21のうち電極が形成された領域は所定の周期(電極周期)で存在する。そのため、入力信号により発生した弾性表面波は、その波長が電極周期に一致する場合に最も強く励振され、電極周期とのずれが大きいほど減衰する。その結果、電極周期に近い波長の信号のみが出力側電極40および出力側配線61を介して出力される。
 ここで、上記動作において、圧電体基板20の温度が上昇する。本実施の形態のSAWデバイス100においては、圧電体基板20に、放熱性の高い材料からなるベース基板10が接触するように配置されている。そのため、SAWデバイス100は高い信頼性を有している。さらに、本実施の形態のSAWデバイス100においては、圧電体基板20とベース基板10とが十分な結合力で結合している。そのため、SAWデバイス100は高い信頼性を有するデバイスとなっている。
 積層体におけるベース基板の支持主面の粗さおよび凹凸の存在状態と接合強度との関係を調査する実験を行った。実験の方法は以下の通りである。
 多結晶スピネルからなるベース基板10を準備し、上記実施の形態と同様の手順にてSAWデバイスを作製した。(実施例A、BおよびC)。また、ベース基板10として多結晶アルミナからなるベース基板10および多結晶ムライトからなるベース基板10を準備し、それぞれ同様にSAWデバイスを作製した(実施例DおよびE)。一方、比較のため、多結晶スピネルからなるベース基板を準備し、同様の手順において工程(S50)を省略したもの(比較例A~F)、多結晶アルミナからなるベース基板を準備し、同様の手順において工程(S50)を省略したもの(比較例GおよびH)、多結晶ムライトからなるベース基板を準備し、同様の手順において工程(S50)を省略したもの(比較例IおよびJ)も作製した。圧電体基板との接合前にベース基板の支持主面についてSa(算術平均粗さ)、Sq(二乗平均平方根高さ)、Sz(最大高さ)を測定するとともに、一辺50μmの正方形領域における1nm以上2nm未満の凹凸、2nm以上3nm未満の凹凸および3nm以上の凹凸の数を確認した。粗さおよび凹凸の数の確認は、支持主面の中央付近および外周付近の2箇所で実施した。そして、接合後、接合状態を確認するとともに、接合強度を測定した。接合強度は、クラックオープニング法により測定した。多結晶スピネルからなるベース基板を採用した場合の実施例の実験結果を表1、比較例の実験結果を表2、多結晶アルミナからなるベース基板を採用した場合の実施例および比較例の実験結果を表3、多結晶ムライトからなるベース基板を採用した場合の実施例および比較例の実験結果を表4に示す。なお、表1~表4において、最下段に関しては、電極形成工程およびチップ化工程が良好に実施できたものについては「良好」、当該工程において積層体に剥離が生じたものについては「不良」と表示されている。
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000002
Figure JPOXMLDOC01-appb-T000003
Figure JPOXMLDOC01-appb-T000004
 表1を参照して、多結晶スピネルからなるベース基板の支持主面の粗さがSaで0.01nm以上3.0nm以下であり、支持主面において、一辺50μmの正方形領域における1nm以上の凹凸が平均で5個未満、かつ2nm以上の凹凸が平均で1個未満である実施例A~Cについては、0.5J/m以上の接合強度が得られており、かつ主面の全面にわたって良好な接合が得られている。一方、表2を参照して、比較例A~Fについては、ベース基板の支持主面の粗さがSaで0.01nm以上3.0nm以下であるものの、接合強度が小さく、良好な接合状態が得られていない。これは、比較例A~Fについては、一辺50μmの正方形領域における1nm以上の凹凸が平均で5個以上であったこと、比較例A、D、EおよびFについては、一辺50μmの正方形領域における2nm以上の凹凸が平均で1個以上であったことが原因であると考えられる。
 また、表3を参照して、多結晶アルミナからなるベース基板の支持主面の粗さがSaで0.01nm以上3.0nm以下であり、支持主面において、一辺50μmの正方形領域における1nm以上の凹凸が平均で5個未満、かつ2nm以上の凹凸が平均で1個未満である実施例Dについては、0.5J/m以上の接合強度が得られており、かつ主面の全面にわたって良好な接合が得られている。一方、比較例GおよびHについては、ベース基板の支持主面の粗さがSaで0.01nm以上3.0nm以下であるものの、接合強度が小さく、良好な接合状態が得られていない。これは、上記多結晶スピネルからなるベース基板の場合と同様に、比較例GおよびHについては、一辺50μmの正方形領域における1nm以上の凹凸が平均で5個以上であったこと、比較例Hについては、一辺50μmの正方形領域における2nm以上の凹凸が平均で1個以上であったことが原因であると考えられる。
 さらに、表4を参照して、多結晶ムライトからなるベース基板の支持主面の粗さがSaで0.01nm以上3.0nm以下であり、支持主面において、一辺50μmの正方形領域における1nm以上の凹凸が平均で5個未満、かつ2nm以上の凹凸が平均で1個未満である実施例Eについては、0.5J/m以上の接合強度が得られており、かつ主面の全面にわたって良好な接合が得られている。一方、比較例IおよびJについては、ベース基板の支持主面の粗さがSaで0.01nm以上3.0nm以下であるものの、接合強度が小さく、良好な接合状態が得られていない。これは、上記多結晶スピネルからなるベース基板の場合と同様に、比較例IおよびJについては、一辺50μmの正方形領域における1nm以上の凹凸が平均で5個以上であったこと、比較例Jについては、2nm以上の凹凸が平均で1個以上であったことが原因であると考えられる。
 以上の実験結果から、算術平均粗さの観点において十分に支持主面の粗さが低減されるだけでなく、支持主面に稀に存在する大きな凹凸も低減されている本願の積層体によれば、圧電体基板とベース基板とが十分な結合力で結合した積層体が得られることが確認される。
 今回開示された実施の形態および実施例はすべての点で例示であって、どのような面からも制限的なものではないと理解されるべきである。本発明の範囲は上記した説明ではなく、請求の範囲によって規定され、請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。
1 積層体
10 ベース基板
100 SAWデバイス
11 支持主面
20 圧電体基板
21 露出主面
22 結合主面
30 入力側電極
31 第1部分
31A ベース部
31B 突出部
32 第2部分
32A ベース部
32B 突出部
40 出力側電極
41 第1部分
41A ベース部
41B 突出部
42 第2部分
42A ベース部
42B 突出部
51 入力側配線
61 出力側配線
 

Claims (6)

  1.  多結晶セラミックから構成され、支持主面を有するセラミック基板であって、
     前記支持主面は、粗さがSaで0.01nm以上3.0nm以下であり、
     前記支持主面において、一辺50μmの正方形領域における1nm以上の凹凸が平均で5個未満、かつ2nm以上の凹凸が平均で1個未満である、セラミック基板。
  2.  前記支持主面は、粗さがSqで0.5nm以下である、請求項1に記載のセラミック基板。
  3.  前記多結晶セラミックは、スピネル、アルミナ、マグネシア、シリカ、ムライト、コージェライト、カルシア、チタニア、窒化珪素、窒化アルミニウムおよび炭化珪素からなる群から選択される1種以上の材料から構成される、請求項1または2に記載のセラミック基板。
  4.  請求項1~3のいずれか1項に記載のセラミック基板と、
     前記支持主面上に配置され、圧電体からなる圧電体基板と、を備え、
     前記セラミック基板と前記圧電体基板とは、ファンデルワールス力により結合されている、積層体。
  5.  前記セラミック基板と前記圧電体基板との接合強度が0.5J/m以上である、請求項4に記載の積層体。
  6.  請求項4または5に記載の積層体と、
     前記圧電体基板の前記セラミック基板とは反対側の主面上に形成される電極と、を備えるSAWデバイス。
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TWI801785B (zh) * 2019-12-18 2023-05-11 日商日本碍子股份有限公司 振動板接合體及振動板接合體的製造方法

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JP2017175618A (ja) 2017-09-28
TWI590393B (zh) 2017-07-01
US10340886B2 (en) 2019-07-02
JPWO2016159393A1 (ja) 2019-01-31
DE112016006627T5 (de) 2018-12-06
KR20170110500A (ko) 2017-10-11
JP7033852B2 (ja) 2022-03-11
CN107406335B (zh) 2020-12-08
US20170279435A1 (en) 2017-09-28
JP7095785B2 (ja) 2022-07-05
TW201735278A (zh) 2017-10-01
JP2021170782A (ja) 2021-10-28

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