TW201735158A - 混合式階梯蝕刻 - Google Patents

混合式階梯蝕刻 Download PDF

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TW201735158A
TW201735158A TW106102765A TW106102765A TW201735158A TW 201735158 A TW201735158 A TW 201735158A TW 106102765 A TW106102765 A TW 106102765A TW 106102765 A TW106102765 A TW 106102765A TW 201735158 A TW201735158 A TW 201735158A
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substrate
mask
forming
hard mask
steps
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TWI735522B (zh
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華 相
仁德 裵
聲振 姜
策 秦
謙 符
葉子 山口
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蘭姆研究公司
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Abstract

提供用以在基板中形成階梯結構的方法，其中基板具有有機遮罩，方法包含至少一循環，其中各循環包含下列步驟：a) 在有機遮罩上方沉積硬遮罩；b) 修整有機遮罩；c) 蝕刻基板；d) 修整有機遮罩，其中在蝕刻基板之步驟與修整有機遮罩之步驟之間無沉積硬遮罩之步驟；e)蝕刻基板；並且f) 重複執行步驟a-e複數次，而形成階梯結構。

Description

混合式階梯蝕刻
本發明係關於半導體裝置的形成。更具體而言，本發明係關於階梯半導體裝置的形成。
在半導體晶圓處理期間，有時需要階梯特徵部。例如，在3D快閃記憶體裝置中，複數單元(cells)以連鎖的型式(chain format)堆疊在一起以節省空間並提高堆積密度。階梯結構允許與每一閘極層的電氣接觸。
由Fu 等人於2013年9月17日提申的美國專利案US 8,535,549揭露在形成階梯結構時沉積硬遮罩於有機遮罩上方，該案為所有目的併入作為參考資料。
為達到先前所述以及根據本發明之目的，提供用以在基板中形成階梯結構的方法，其中該基板具有一有機遮罩，該方法包含至少一循環，其中各該循環包含下列步驟：a) 在該有機遮罩上方沉積一硬遮罩；b) 修整該有機遮罩；c) 蝕刻該基板；d) 修整該有機遮罩，其中在蝕刻該基板之步驟與修整該有機遮罩之步驟之間無沉積硬遮罩之步驟；e)蝕刻該基板；並且f) 重複執行步驟a-e複數次，而形成該階梯結構。
在另一表現(manifestation)中，提供用以從包含複數層的記憶體疊層形成三維度記憶體結構的方法，其中各該層包含至少兩子層且其中一有機遮罩位於該記憶體疊層上。a) 在該有機遮罩之頂部上方沉積一硬遮罩。b) 修整該有機遮罩。c) 蝕刻該記憶體疊層，使得該記憶體疊層之未被該有機遮罩遮蓋的部分被蝕刻。d) 修整該有機遮罩，其中在步驟c與d之間無沉積硬遮罩之步驟。e) 蝕刻該記憶體疊層。f)重複執行步驟a-e複數次，而形成該三維度記憶體結構。
在另一表現(manifestation)中，提供用以在電漿處理腔室中之基板中形成階梯結構的方法，其中該基板具有一有機遮罩。提供至少一循環，其中該至少一循環包含一保護蝕刻階段及一未保護蝕刻階段。
於下列本發明的細節描述中，將結合附圖而詳細說明本發明之該等與其他特徵。
現將參照如附圖所繪示之若干較佳實施例而詳細說明本發明。為提供對本發明之全面性了解，下列敘述中將闡述許多具體的細節。然而很明顯地，對於該技術領域中具有通常知識者而言，本發明毋需一些或全部該等細節即可實施。另外，為了避免不必要地混淆本發明，熟知的製程步驟及/或結構將不再贅述。
為促進理解，圖1為可用於本發明之實施例中之在基板中形成階梯結構的處理的高階流程圖。在基板上形成有機遮罩(步驟104)。在有機遮罩上沉積硬遮罩(步驟108)。修整硬遮罩(步驟112)。修整有機遮罩(步驟116)。蝕刻階梯(步驟120)。週期性地重複執行修整有機遮罩(步驟116)及蝕刻階梯(步驟120)至少一次。若階梯之蝕刻未完成(步驟128)，則進行處理以沉積硬遮罩(步驟108)。否則，完成處理並可執行其他步驟。
在本發明之實施例的範例中，蝕刻階梯記憶體陣列。在此種記憶體陣列中，在晶圓上形成記憶體疊層。圖2A為形成在晶圓208上的複數層的記憶體疊層204的剖面圖。在此實施例中，複數記憶體疊層中的各個記憶體疊層係由一層矽氧化物(SiO2 )216位於一層矽氮化物(SiN)212之頂部上方的雙層所形成，而形成ONON基板。在記憶體疊層204上形成有機遮罩220(步驟104)。有機遮罩可為使用旋塗處理及光微影圖案化形成的光阻劑遮罩。在替代例中，有機遮罩可為以旋塗或以其他方式塗佈(未使用光微影圖案化)的有機層。
晶圓208可放置在處理工具中以執行後續步驟。圖3圖解可用於本發明之實施例中的處理工具。圖3為電漿處理系統300的一示意圖，其包括電漿處理工具301。電漿處理工具301係一電感耦合式電漿蝕刻工具且其包括電漿反應器302，而在電漿反應器302中具有電漿處理腔室304。變壓器耦合式功率(TCP)控制器350以及偏壓功率控制器355分別地控制TCP功率供應器351以及偏壓功率供應器356，俾影響在電漿腔室304中所生成之電漿324。
TCP功率控制器350為TCP功率供應器351設定一設定值，而TCP功率供應器351係配置以將13.56MHz的射頻訊號(透過TCP匹配網路352調諧)，供應到TCP線圈353 (位在靠近電漿腔室304之處)。設置RF透明窗354以將TCP線圈353與電漿腔室304隔開，但允許能量從TCP線圈353傳遞到電漿腔室304。
偏壓功率控制器355為偏壓功率供應器356設定一設定值，而偏壓功率供應器356係配置以將RF訊號(透過偏壓匹配網路357調諧)，供應到卡盤電極308(位在電漿腔室304之中)，俾在電極308之上方產生直流(DC)偏壓，而電極308適於接收被處理的晶圓200(例如半導體晶圓工件)。
氣體供應機制或氣體來源310包括氣體(或複數氣體)的來源(或複數來源)316，其透過氣體分歧管317而附接，以將該製程所需的適當化學品供應到電漿腔室304之內側。氣體排氣機制318包括壓力控制閥319與排氣泵浦320，且其用以將微粒從電漿腔室304之中移除並用以維持電漿腔室304之中的特定壓力。
溫度控制器380透過控制冷卻功率供應器384，來控制設置在卡盤電極308之內的一冷卻再循環系統。電漿處理系統亦包括電子控制電路370。電漿處理系統亦具有一端點偵測器。此種電感耦合式系統的一範例為美國加州佛蒙特(Fremont, CA)的蘭姆研究公司(Lam Research Corporation)所開發出的Kiyo，除了介電質與有機材料，Kiyo亦用於蝕刻矽、多晶矽、以及傳導層。在本發明的其他實施例中可使用電容耦合式系統。
圖4為一高階方塊圖，其顯示合適於實現用於本發明之實施例中的控制電路370的電腦系統400。該電腦系統可具有許多實體形式，範圍從積體電路、印刷電路板、以及小型手持式裝置，直到巨大超級電腦。電腦系統400包含一或更多的處理器402，且進一步可包含電子顯示裝置404(用來顯示圖表、文字，或其他資料)、主記憶體406(例如隨機存取記憶體(RAM))、儲存裝置408(例如硬碟機)、可攜式儲存裝置410(例如光碟機)、使用者介面裝置412(例如鍵盤、觸控螢幕、輔助鍵盤、滑鼠或其他指向裝置等)，以及通訊介面414(例如無線網路介面)。通訊介面414幫助軟體和資料透過一聯結，在電腦系統400與外接裝置之間傳輸。該系統亦可包含通訊基礎設備416(例如通信匯流排、交流桿、或網路)，前面提及的裝置/模組連接到通訊基礎設備416。
透過通訊介面414所傳輸的資訊，可以例如為下列訊號的形式，例如電子的、電磁的、光學的、或其他可以被通訊介面414接收的訊號(透過一攜帶訊號的通訊聯結)，該通訊聯結可使用電線或纜線、光纖、電話線、行動電話聯結、射頻聯結、及/或其他通訊管道來執行。有了此種通訊介面，吾人認為該一或更多的處理器402可從網路接收資訊，或可在執行上述之方法步驟期間，將資訊輸出到網路。進一步而言，本發明之方法實施例，可在該處理器上單獨地執行，或可結合遠端處理器(分擔一部分的處理)通過網路(例如網際網路)而執行。
「非暫態電腦可讀取媒體」這個用語，通常用於指稱媒體如主記憶體、輔助記憶體、可攜式儲存器，以及儲存裝置，諸如硬碟、快閃記憶體、碟片驅動機記憶體、CD-ROM或其他形式的永久記憶體，並且不應被解釋為涵蓋暫態的主體(如載波或訊號)。電腦碼的範例包含機器碼(例如由編譯器產生)、以及含高階碼的文件，其使用直譯器由電腦執行。電腦可讀媒體亦可為經由電腦資料訊號發送的電腦碼，其收錄在載波中，並呈現一連串可經由處理器執行的指令。
在此範例中，硬遮罩224沉積在有機遮罩220上，如圖2B所示 (步驟108)。用以形成硬遮罩224之配方的範例提供10 毫托的壓力。13.56 MHz 的RF功率來源提供300瓦的 TCP功率。偏壓來源提供75伏的偏壓。氣體來源提供包含50 sccm的SiCl4 及100 sccm的O2 的硬遮罩沉積氣體。應注意的係，在形成硬遮罩時可提供偏壓，以促使頂部層的厚度較側壁層的厚度更厚。在此範例中，硬遮罩224在此循環中未沉積在有機遮罩220的側壁上，而略過硬遮罩之修整(步驟112)。修整有機遮罩(步驟116)。圖5為修整有機遮罩之步驟(步驟116)的更詳細流程圖。修整氣體從氣體來源316流進電漿腔室304中(步驟504)。修整氣體包含O2 及N2 。將修整氣體形成電漿(步驟508)。在有機遮罩220被充分地修整之後，停止修整氣體(步驟512)。
用以修整有機遮罩之配方的範例提供介於80到400毫托的壓力。修整氣體從氣體來源316流進電漿腔室304中(步驟504)，其中修整氣體為1000sccm的O2 、30sccm的N2 、及50sccm的NF3 。將修整氣體形成電漿(步驟508)。在此範例中，以13.56 MHz 提供1800瓦的RF功率。提供0伏的偏壓。維持電漿達20到60秒，然後停止修整氣體(步驟512)。圖2C為修整有機遮罩220之後的疊層的剖面圖。有機遮罩220的修整亦將位於被整修之部分有機遮罩220上方的部分硬遮罩224移除。
使用有機遮罩作為遮罩來蝕刻階梯(步驟120)。圖2D為蝕刻階梯之後的疊層的剖面圖。用以蝕刻階梯之矽氧化物子層216的配方提供10毫托的壓力。從氣體來源提供蝕刻氣體流量(40sccm的O2 、300sccm的Ar、及60sccm的C4 F6 )。RF功率來源提供1320瓦的 TCP功率。提供500伏的偏壓。提供該處理達10秒。用以蝕刻階梯之矽氮化物子層212的配方提供30毫托的壓力。從氣體來源提供蝕刻氣體流量(100sccm的O2 、140sccm的CH3 F、及30sccm的CF4 )。RF功率來源提供1800瓦的 TCP功率。提供500伏的偏壓。提供該處理達14秒。
硬遮罩在階梯蝕刻期間已被蝕刻掉。判定需要額外的階梯且不需要新的硬遮罩(步驟124)，故再次修整有機遮罩220(步驟116)。圖2E為修整有機遮罩220(步驟116)之後的疊層的剖面圖。蝕刻階梯(步驟120)，如圖2F所示，而形成第一階梯240及第二階梯244。
判定需要額外的階梯且需要新的硬遮罩(步驟128)，故沉積新的硬遮罩(步驟108)。圖2G為沉積新的硬遮罩228(步驟108)之後的疊層200的剖面圖。在此範例中，若干硬遮罩材料已沉積在有機遮罩220的側壁上。硬遮罩228經受硬遮罩修整(步驟112)。用以修整硬遮罩之配方的範例提供70 毫托的壓力。提供修整氣體(500sccm的NF3 及200sccm的He)到電漿處理腔室中。提供800瓦的TCP RF訊號以將修整氣體轉換成修整電漿。圖2H為硬遮罩修整(步驟112)之後的疊層200的剖面圖。
修整有機遮罩(步驟116)。圖2I為修整有機遮罩(步驟116)之後的疊層200的剖面圖。蝕刻階梯(步驟120)，如圖2J所示，而形成位於第一階梯240及第二階梯244上方的第三階梯248。硬遮罩在階梯蝕刻期間已被蝕刻掉。判定需要額外的階梯且不需要新的硬遮罩(步驟124)，故再次修整有機遮罩220(步驟116)。圖2K為修整有機遮罩220(步驟116)之後的疊層的剖面圖。蝕刻階梯(步驟120)，如圖2L所示，而形成位於第一階梯240、第二階梯244及、第三階梯248上方的第四階梯252。
若不需要額外的階梯(步驟128)，則完成循環處理。可提供額外步驟以進行進一步處理。例如，可剝除有機遮罩220而產生包含頂部層在內共具有五個階梯的記憶體疊層。可在將基板從腔室中移除之前於相同的腔室中完成額外步驟(例如剝除有機遮罩)，或可將基板從腔室中移除以執行額外步驟。此實施例允許有機遮罩的修整、殘餘物的移除、及基板的蝕刻在相同的腔室中執行，使在所有的步驟中得使用相同的電漿反應器、功率供應器、線圈/電極、及卡盤電極。
硬遮罩允許在有機遮罩較少薄化的情況下修整有機遮罩，故可提供更多數量的階梯。較佳地，重複執行循環至少3次而提供至少五個階梯。更佳地，可以單次有機遮罩形成處理來提供至少八個階梯。更佳地，可使用單次有機遮罩處理來提供二十個以上的階梯。在其他實施例中，可在一或更多方向上形成階梯。在一範例中，可以三十二個階梯來建立一個階梯結構。
在此實施例中，有機遮罩的修整具有低於0.8的垂直對側向比。更佳地，有機遮罩的修整具有低於0.5的垂直對側向比。相較於有機遮罩的側壁，硬遮罩選擇性地沉積在有機遮罩的頂部上，使得在有機遮罩的頂部上的沉積層比在有機遮罩的側壁上的沉積層更厚。在一些實施例中，沉積硬遮罩而在有機遮罩的頂部上沉積頂部層，並且在有機遮罩的側部上沉積側壁，其中硬遮罩的頂部層具有大於側壁之厚度的一厚度。更佳地，頂部層之厚度為側壁之厚度的至少1.5倍。
在其他實施例中，待蝕刻的基板可由其他材料製成，或基板可為單一材料的固件。在一較佳實施例中，基板包含用以形成基板之記憶體疊層的複數層，其中各層包含至少兩子層。在一範例中，至少一子層為矽氧化物。在另一範例中，各層包含三子層。在其他實施例中，可使用其他修整氣體來取代O2 或除了O2 之外又使用其他修整氣體。圖6為已使用一實施例加以蝕刻之晶圓604上之階梯結構的剖面圖，其中各階梯包含第一子層608、第二子層612、第三子層616、及第四子層620。在另一實施例中，基板可為連續的單層。在不同的實施例中，基板可為矽氧化物與多晶矽之子層的交替層(OPOP)。在另一實施例中，各階梯可由三子層形成。
在一些實施例中，執行循環使得硬遮罩沉積至少三次。在其他實施例中，執行循環使得硬遮罩沉積至少五次。
由於各種實施例可提供不同的在硬遮罩沉積之間的蝕刻循環次數，且由於在一實施例中，在硬遮罩沉積之間的蝕刻循環次數可有所不同，故在硬遮罩沉積之間的蝕刻循環次數可為額外的控制參數。此控制參數可用以修改配方以使蝕刻要求明確。
一實施例包含至少一循環，其中至少一循環包含一保護蝕刻階段及一未保護蝕刻階段。在一實施例中，保護蝕刻階段包含：在有機遮罩上沉積硬遮罩；修整有機遮罩；並且蝕刻基板。未保護蝕刻階段包含：修整有機遮罩，其中有機遮罩未受硬遮罩保護；並且蝕刻基板。在一實施例中，重複執行循環至少五次。在一些實施例中，保護蝕刻階段先於未保護蝕刻階段。在其他實施例中，未保護蝕刻階段先於保護蝕刻階段。
在每一次有機遮罩修整之前沉積硬遮罩的處理中，需要後續的硬遮罩移除與有機遮罩平滑化步驟。在無平滑化步驟之情況下，每一次蝕刻循環的硬遮罩沉積會導致每一次循環的有機遮罩粗糙化。粗糙化的一原因為，在無硬遮罩清潔與平滑化步驟之情況下可能擴大針孔。增加有機遮罩平滑化步驟會增加處理時間。業已發現，在上述實施例中，當有機遮罩上不存在硬遮罩時，缺少硬遮罩移除步驟且要求有機遮罩修整及有機遮罩層的垂直蝕刻，使有機遮罩平滑化，因此不需要一單獨的有機遮罩平滑化步驟。更具體而言，業已發現，在無硬遮罩之情況下修整有機遮罩，使有機遮罩平滑化，因此不需要一單獨的有機遮罩平滑化步驟。如此的修整將導致有機遮罩薄化。業已發現，與每一次蝕刻循環提供硬遮罩的處理相比，各種實施例提供較低的側向對垂直蝕刻比。
相較於每一次蝕刻循環在有機遮罩層上提供硬遮罩的處理，在本發明之一實施例中的處理亦提供更快的處理。這係透過刪除若干蝕刻循環的硬遮罩形成步驟而完成。這提供更快的產出。降低的有機遮罩薄化情況允許使用給定的一有機遮罩層來蝕刻更多的階梯或允許減少有機遮罩厚度(提高解析度(resolution))。移除部分階梯蝕刻的硬遮罩消除了移除硬遮罩所需的時間。
雖然本發明已經用許多優選的實施例來描述，但仍有其他變化、排列置換或其他替代的等價態樣，也在本發明的範圍中。須注意仍有許多執行本發明的方法和儀器之替代方式。因此申請人意欲將下列申請專利範圍解釋為包含所有落入本發明之真正精神與範圍中之此等變化、排列置換或其他替代的等價態樣。
104‧‧‧步驟
108‧‧‧步驟
112‧‧‧步驟
116‧‧‧步驟
120‧‧‧步驟
124‧‧‧步驟
128‧‧‧步驟
200‧‧‧晶圓
204‧‧‧記憶體疊層
208‧‧‧晶圓
212‧‧‧矽氮化物(子層)
216‧‧‧矽氧化物(子層)
220‧‧‧有機遮罩
224‧‧‧硬遮罩
228‧‧‧硬遮罩
240‧‧‧第一階梯
244‧‧‧第二階梯
248‧‧‧第三階梯
252‧‧‧第四階梯
300‧‧‧電漿處理系統
301‧‧‧電漿處理工具
302‧‧‧電漿反應器
304‧‧‧電漿(處理)腔室
308‧‧‧電極
310‧‧‧氣體供應機制或氣體來源
316‧‧‧氣體來源
317‧‧‧氣體分歧管
318‧‧‧氣體排氣機制
319‧‧‧壓力控制閥
320‧‧‧排氣泵浦
324‧‧‧電漿
350‧‧‧TCP(功率)控制器
351‧‧‧TCP功率供應器
352‧‧‧TCP匹配網路
353‧‧‧TCP線圈
354‧‧‧RF透明窗
355‧‧‧偏壓功率控制器
356‧‧‧偏壓功率供應器
357‧‧‧偏壓匹配網路
370‧‧‧控制電路
380‧‧‧溫度控制器
384‧‧‧冷卻功率供應器
400‧‧‧電腦系統
402‧‧‧處理器
404‧‧‧電子顯示裝置
406‧‧‧主記憶體
408‧‧‧儲存裝置
410‧‧‧可攜式儲存裝置
412‧‧‧使用者介面裝置
414‧‧‧通訊介面
416‧‧‧通訊基礎設備
504‧‧‧步驟
508‧‧‧步驟
512‧‧‧步驟
604‧‧‧晶圓
608‧‧‧第一子層
612‧‧‧第二子層
616‧‧‧第三子層
620‧‧‧第四子層
本發明係藉由舉例方式(非限制性)而繪示於隨附圖示中，其中類似之參考數字指涉相同的元件，其中：
圖1為可用於本發明之實施例中之處理的高階流程圖。
圖2A-L為根據本發明之實施例而形成的記憶體疊層之示意剖面圖。
圖3為可用於實施本發明的電漿處理腔室之示意圖。
圖4圖解一電腦系統，其合適於實現用於本發明之實施例中的控制器。
圖5為修整有機遮罩之步驟的更詳細流程圖。
圖6為根據另一實施例而形成的記憶體疊層之示意剖面圖。
104‧‧‧步驟
108‧‧‧步驟
112‧‧‧步驟
116‧‧‧步驟
120‧‧‧步驟
124‧‧‧步驟
128‧‧‧步驟

Claims (23)

  1. 一種用以在電漿處理腔室中之基板中形成階梯結構的方法，其中該基板具有一有機遮罩，該方法包含至少一循環，其中各循環包含下列步驟： a)    在該有機遮罩上方沉積一硬遮罩； b)    修整該有機遮罩； c)    蝕刻該基板； d)    修整該有機遮罩，其中在蝕刻該基板之步驟與修整該有機遮罩之步驟之間無沉積硬遮罩之步驟；並且 e)    蝕刻該基板。
  2. 如申請專利範圍第1項之用以在電漿處理腔室中之基板中形成階梯結構的方法，更包含重複執行步驟a-e複數次，而形成該階梯結構。
  3. 如申請專利範圍第2項之用以在電漿處理腔室中之基板中形成階梯結構的方法，其中針對步驟a-e之各循環，週期性地重複執行步驟d及e至少一次。
  4. 如申請專利範圍第3項之用以在電漿處理腔室中之基板中形成階梯結構的方法，其中重複執行步驟a-e之各循環至少五次。
  5. 如申請專利範圍第4項之用以在電漿處理腔室中之基板中形成階梯結構的方法，其中沉積該硬遮罩之步驟在該有機遮罩的側壁上沉積該硬遮罩；且更包含在步驟a與b之間修整該硬遮罩。
  6. 如申請專利範圍第5項之用以在電漿處理腔室中之基板中形成階梯結構的方法，其中該有機遮罩為光阻劑遮罩。
  7. 如申請專利範圍第6項之用以在電漿處理腔室中之基板中形成階梯結構的方法，其中步驟a-e係在單一電漿處理腔室中執行。
  8. 如申請專利範圍第7項之用以在電漿處理腔室中之基板中形成階梯結構的方法，其中該基板包含複數層，其中各層包含至少兩子層。
  9. 如申請專利範圍第8項之用以在電漿處理腔室中之基板中形成階梯結構的方法，其中該至少兩子層中之至少一者為含矽氧化物層。
  10. 如申請專利範圍第1項之用以在電漿處理腔室中之基板中形成階梯結構的方法，其中沉積該硬遮罩之步驟在該有機遮罩的頂部上沉積一頂部層，並且在該有機遮罩的側部上沉積一側壁，且其中該硬遮罩的頂部層具有比該硬遮罩的側壁的厚度更厚之一厚度；且更包含在步驟a與b之間修整該硬遮罩。
  11. 如申請專利範圍第1項之用以在電漿處理腔室中之基板中形成階梯結構的方法，其中步驟d使該有機遮罩平滑化。
  12. 如申請專利範圍第1項之用以在電漿處理腔室中之基板中形成階梯結構的方法，其中步驟c將該硬遮罩完全地移除；且其中步驟d與e係在無硬遮罩的情況下執行；且其中步驟d部分地蝕刻該有機遮罩。
  13. 一種用以從包含複數層的記憶體疊層形成三維度記憶體結構的方法，其中各層包含至少兩子層且其中一有機遮罩位於該記憶體疊層上，該方法包含下列步驟： a)    在該有機遮罩之頂部上方沉積一硬遮罩； b)    修整該有機遮罩； c)    蝕刻該記憶體疊層，使得該記憶體疊層之未被該有機遮罩遮蓋的部分被蝕刻該複數層中之至少一層的厚度之一深度； d)    修整該有機遮罩，其中在步驟c與d之間無沉積硬遮罩之步驟； e)    蝕刻該記憶體疊層；並且 f)     重複執行步驟a-e複數次，而形成該三維度記憶體結構。
  14. 如申請專利範圍第13項之用以從包含複數層的記憶體疊層形成三維度記憶體結構的方法，更包含在執行步驟f之前週期性地重複執行步驟d與e至少一次。
  15. 如申請專利範圍第13項之用以從包含複數層的記憶體疊層形成三維度記憶體結構的方法，其中沉積該硬遮罩之步驟在該有機遮罩的側壁上沉積一側壁層；且更包含將該硬遮罩之側壁層移除。
  16. 如申請專利範圍第15項之用以從包含複數層的記憶體疊層形成三維度記憶體結構的方法，其中該硬遮罩的一頂部層的厚度大於該硬遮罩的側壁層的厚度。
  17. 如申請專利範圍第16項之用以從包含複數層的記憶體疊層形成三維度記憶體結構的方法，其中該有機遮罩為光阻劑遮罩。
  18. 如申請專利範圍第17項之用以從包含複數層的記憶體疊層形成三維度記憶體結構的方法，其中步驟a-f係在單一電漿處理腔室中執行。
  19. 一種用以在電漿處理腔室中之基板中形成階梯結構的方法，其中該基板具有一有機遮罩，該方法包含至少一循環，其中各循環包含： 一保護蝕刻階段；及 一未保護蝕刻階段。
  20. 如申請專利範圍第19項之用以在電漿處理腔室中之基板中形成階梯結構的方法， 其中該保護蝕刻階段包含下列步驟： 在該有機遮罩上方沉積一硬遮罩； 修整該有機遮罩；並且 蝕刻該基板； 且其中該未保護蝕刻階段包含下列步驟： 修整該有機遮罩，其中在該有機遮罩上方無硬遮罩；並且 蝕刻該基板。
  21. 如申請專利範圍第19項之用以在電漿處理腔室中之基板中形成階梯結構的方法，其中重複執行該循環至少五次。
  22. 如申請專利範圍第19項之用以在電漿處理腔室中之基板中形成階梯結構的方法，其中該保護蝕刻階段先於該未保護蝕刻階段。
  23. 如申請專利範圍第19項之用以在電漿處理腔室中之基板中形成階梯結構的方法，其中該未保護蝕刻階段先於該保護蝕刻階段。
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