TW201705386A - 以封膠體取代基板核心之多晶片封裝構造 - Google Patents

以封膠體取代基板核心之多晶片封裝構造 Download PDF

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TW201705386A
TW201705386A TW104124602A TW104124602A TW201705386A TW 201705386 A TW201705386 A TW 201705386A TW 104124602 A TW104124602 A TW 104124602A TW 104124602 A TW104124602 A TW 104124602A TW 201705386 A TW201705386 A TW 201705386A
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wafer
circuit layer
chip
encapsulant
sealant
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張家維
林國鼎
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力成科技股份有限公司
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Abstract

揭示一種以封膠體取代基板核心之多晶片封裝構造，包含晶片堆疊體、內重配置線路層、晶片互連元件、在內重配置線路層上之金屬柱、密封晶片堆疊體與晶片互連元件之封膠體、外重配置線路層以及複數個設置封膠體周邊之縱向導通機構。內重配置線路層形成於晶片堆疊體之一主動面上，晶片互連元件具有一超過主動面之線弧段，外重配置線路層完整形成於封膠體之平坦面上。封膠體具有一覆蓋於內重配置線路層之覆線厚度，藉以密封線弧段與金屬柱並使金屬柱之端面顯露於平坦面，達到省略基板厚度之超薄型晶片堆疊並可應用於封裝堆疊裝置之功效。

Description

以封膠體取代基板核心之多晶片封裝構造
本發明係有關於多晶片封裝領域，特別係有關於一種以封膠體取代基板核心之多晶片封裝構造，以應用於封裝堆疊裝置(Package-On-Package device,POP)。
在傳統的多晶片封裝構造中，係將複數個晶片堆疊整合在一封裝構造中，以有效利用空間，可稱之為「晶片在晶片上」(Die-On-Die,DOD)裝置。而封裝堆疊(Package-On-Package,POP)裝置則是將多個晶片封裝構造進行堆疊結合。現行產品中同時運用DOD與POP技術，可將16層晶片密封在一封裝構造中，再將二顆內含16層晶片的封裝構造堆疊，最終高度約在2毫米(mm)。然而，高度2毫米的封裝規格已無法滿足現階段客戶的需求，而且因此一結構的製造良率低，導致成本過高。
PCT國際專利公開編號WO 2015/042886 A1揭示一種「堆疊半導體裝置的互連方法」，在其圖9揭示一種習知超薄型多晶片封裝構造。如第1圖所示，一種習知多晶片封裝構造200係包含一晶片堆疊體210、一封膠體250、一外重配置線路層260、複數個不等深之導通孔241、242、243以及複數個銲球280。該些 銲球280係連接在該外重配置線路層260，以作為對外連接的接點。
該晶片堆疊體210係由複數個晶片211所堆疊構成，該些晶片211係為階梯式錯位堆疊。該晶片堆疊體210係具有一不被該些晶片211堆疊覆蓋之主動面213。該封膠體250係密封該晶片堆疊體210。該封膠體250係具有一下表面251，該下表面251係位於該主動面213之周邊。該外重配置線路層260係完整形成於該封膠體250之該下表面251上。該主動面213與該封膠體250之下表面共同構成為一供形成該外重配置線路層260之表面。該外重配置線路層260同時形成於該下表面251與主動面213上，故該下表面251無法研磨為一平坦面。每一晶片211未被堆疊覆蓋之局部表面上係形成有複數個銲墊(圖未繪出)，為使晶片211之銲墊與該外重配置線路層260形成電路連結，利用鑽孔技術形成該些導通孔241、242、243，由於每一晶片211至該下表面251之距離不相同，故該些導通孔241、242、243的孔深不一，故會增加模封貫孔(TMV)之製程難度，而使製程良率下降。此外，該些導通孔241、242、243之間距必須對應晶片211之銲墊間距而為密集排列，亦會造成對位困難。
另外，該封膠體250之下表面251係為熱固性絶緣材質，該些晶片211係為半導體材質，兩者膨脹係數不一。同時形成於該封膠體250之下表面251與該些晶片211之該主動面213之該外重配置線路層260係必須為跨材料界面的形成。在熱循環測 試或產品運算時，該外重配置線路層260在不同材料界面處容易熱應力而斷裂或裂痕，造成產品失效。
為了解決上述之問題，本發明之主要目的係在於提供一種以封膠體取代基板核心之多晶片封裝構造，可達到省略基板厚度之超薄型晶片堆疊並可應用於POP封裝堆疊之功效。
本發明之次一目的係在於提供一種以封膠體取代基板核心之多晶片封裝構造，可使扇出重配置線路層為平坦化形成並防止在晶片與封膠體間界面處產生斷裂。
本發明的目的及解決其技術問題是採用以下技術方案來實現的。本發明揭示一種以封膠體取代基板核心之多晶片封裝構造，包含一晶片堆疊體、一內重配置線路層、複數個晶片互連元件、複數個金屬柱、一封膠體、一外重配置線路層以及複數個縱向導通機構。該晶片堆疊體係主要由複數個晶片堆疊所組成，每一晶片係具有複數個銲墊，該晶片堆疊體係可具有一不被該些晶片堆疊覆蓋之主動面。該內重配置線路層係可形成於該晶片堆疊體之該主動面上。該些晶片互連元件係可電性連接該些晶片之該些銲墊，該些晶片互連元件係具有一超過該主動面之線弧段。該些金屬柱係設置於該內重配置線路層上，該些金屬柱係具有複數個端面，其係較高於該線弧段。該封膠體係可密封該晶片堆疊體與該些晶片互連元件，該封膠體係具有一平坦面，該平坦面係位於該主動面上且鄰近於該內重配置線路層，並且該封膠體 係具有一覆蓋於該內重配置線路層之覆線厚度，藉以密封該線弧段與該些金屬柱並使該些金屬柱之該些端面顯露於該平坦面。該外重配置線路層係可完整形成於該封膠體之該平坦面上，該外重配置線路層係為往周邊扇出之線路型態，並經由該些金屬柱電性連接至該內重配置線路層。該些縱向導通機構係設置於該封膠體之周邊並電性連接該外重配置線路層至該封膠體相對於該平坦面之一封裝堆疊接合面。藉此，達到省略基板厚度之超薄型晶片堆疊並可應用於POP封裝堆疊之功效。本發明另揭示一種以封膠體取代基板核心之多晶片封裝構造之製造方法。
本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。
在前述多晶片封裝構造中，該些晶片係可為階梯式錯位堆疊，以不遮蓋該些銲墊，故該些銲墊不受晶片堆疊之遮蓋並可供該些晶片之間電性連接。
在前述多晶片封裝構造中，該些晶片互連元件係可包含銲線。
在前述多晶片封裝構造中，該封膠體係可具有一不大於500微米之基板核心厚度，該封膠體在該主動面上之覆線厚度係介於25至200微米之間，故可大幅減少POP整體堆疊厚度。
在前述多晶片封裝構造中，該些縱向導通機構係具體地包含複數個貫穿該封膠體之模封貫孔以及複數個填入該些模封貫孔內之導電材料，以電性連接該外重配置線路層，故可藉 由該些導電材料進行POP縱向電性傳導。
在前述多晶片封裝構造中，該些導電材料係可突出於該封裝堆疊接合面並迴焊成銲球狀。
在前述多晶片封裝構造中，該些金屬柱係可為銅柱，該些晶片互連元件係為金線，使得該些金屬柱之硬度大於該些晶片互連元件之硬度，以避免該些金屬柱之變形而導致該些晶片互連元件顯露於該封膠體之該平坦面。
在前述多晶片封裝構造中，該些金屬柱之該些端面係可經研磨而共平面於該平坦面，以利該外重配置線路層的平坦化形成並更確實地連接該些金屬柱。
藉由上述的技術手段，本發明可以達成省略基板厚度之超薄型晶片堆疊並可應用於POP封裝堆疊之功效，在一具體應用中，POP封裝堆疊在4個封裝堆疊的32個晶片組合中，整體厚度可下降至不超過1.9毫米，並且利用封膠體覆蓋主動面以填滿內外雙層重配置線路層之間隙，外重配置線路層不與晶片主動面有直接連接，故扇出線路在晶片主動面上方的中央扇入部份不易斷裂，故外重配置線路層之扇出線路不會受到晶片與封裝材料的跨材質界面影響以及不會受到晶片堆疊的水平偏差影響。
10‧‧‧晶圓承載系統
20‧‧‧研磨頭
100‧‧‧多晶片封裝構造
110‧‧‧晶片堆疊體
111‧‧‧晶片
112‧‧‧銲墊
113‧‧‧主動面
114‧‧‧黏晶層
120‧‧‧內重配置線路層
130、130a‧‧‧晶片互連元件
131‧‧‧線弧段
140‧‧‧金屬柱
141‧‧‧端面
150‧‧‧封膠體
151‧‧‧平坦面
152‧‧‧覆線厚度
153‧‧‧封裝堆疊接合面
160‧‧‧外重配置線路層
161‧‧‧扇入凸塊接墊
162‧‧‧扇出接墊
170‧‧‧模封貫孔
171‧‧‧導電材料
172‧‧‧突出部位
180‧‧‧銲球
200‧‧‧多晶片封裝構造
210‧‧‧晶片堆疊體
211‧‧‧晶片
213‧‧‧主動面
241、242、243‧‧‧導通孔
250‧‧‧封膠體
251‧‧‧下表面
260‧‧‧外重配置線路層
280‧‧‧銲球
300‧‧‧多晶片封裝構造
第1圖：PCT國際專利公開編號WO 2015/042886 A1揭示之一種習知超薄型多晶片封裝構造之截面示意圖。
第2圖：依據本發明之一較佳實施例，一種以封膠體取代基板核心之多晶片封裝構造之截面示意圖。
第3圖：依據本發明之一較佳實施例，上述以封膠體取代基板核心之多晶片封裝構造在金屬柱處之局部放大截面示意圖。
第4圖：依據本發明之一較佳實施例，利用複數個以封膠體取代基板核心之多晶片封裝構造組合成一封裝堆疊裝置(POP)之截面示意圖。
第5A至5J圖：依據本發明之一較佳實施例，在製造上述以封膠體取代基板核心之多晶片封裝構造之各製程步驟中之元件截面示意圖。
以下將配合所附圖示詳細說明本發明之實施例，然應注意的是，該些圖示均為簡化之示意圖，僅以示意方法來說明本發明之基本架構或實施方法，故僅顯示與本案有關之元件與組合關係，圖中所顯示之元件並非以實際實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例與其他相關尺寸比例或已誇張或是簡化處理，以提供更清楚的描述。實際實施之數目、形狀及尺寸比例為一種選置性之設計，詳細之元件佈局可能更為複雜。
依據本發明之一較佳實施例，一種以封膠體取代基板核心之多晶片封裝構造舉例說明於第2圖之截面示意圖、第3圖之局部放大截面示意圖以及第4圖利用複數個以封膠體取代基 板核心之多晶片封裝構造組合成一封裝堆疊裝置(POP)之截面示意圖。如第2圖所示，該多晶片封裝構造100係包含一晶片堆疊體110、一內重配置線路層120、複數個晶片互連元件130、複數個金屬柱140、一封膠體150、一外重配置線路層160以及複數個縱向導通機構。在本實施例中，該些縱向導通機構係為複數個模封貫孔170與複數個導電材料171之組合。
該晶片堆疊體110係主要由複數個晶片111堆疊所組成，每一晶片111係具有複數個銲墊112，該些銲墊112與晶片111內部積體電路的金屬內連線(未繪示)電性連接，該晶片堆疊體110係可具有一不被該些晶片111堆疊覆蓋之主動面113。每一晶片111係可藉由一黏晶層114而黏貼固定於另一晶片。在完成晶片堆疊之後，該些晶片111之複數個主動面中產生一主動面，不被其它晶片所堆疊覆蓋，即為上述所指之主動面113。在本實施例中，該主動面113係朝向該外重配置線路層160。具體地，該些晶片111係可為階梯式錯位堆疊，以不遮蓋該些銲墊112，故該些銲墊112因不受晶片堆疊之遮蓋並可供該些晶片互連元件130對該些晶片111間做電性連接。
該內重配置線路層120係可形成於該晶片堆疊體110之該主動面113上。重配置線路層係為可使用半導體晶圓沉積設備形成之微線路層，重配置線路層不需要形成於基板，並且重配置線路層的厚度薄化與微間距化皆優於印刷電路板之線路層，並且重配置線路層之形成係可利用先沉積、圖案化電鍍再蝕 刻之製程或是直接圖案化沉積之製程，皆不需要習知印刷電路板之電鍍線結構。在一實施例中，該內重配置線路層120可包括銅、鋁、金、鉑、鎳、錫或前述之組合，或可為導電高分子材料、導電陶瓷材料(例如，氧化銦錫或氧化銦鋅)或其他適合的導電材料。較佳地，該內重配置線路層120可以只形成在最下層之晶片111之主動面113上，其餘之主動面可不需形成，以節省製程與成本。
如第2與3圖所示，該些晶片互連元件130係可電性連接該些晶片111之該些銲墊112。在本實施例中，該些晶片互連元件130係可包含打線形成之銲線。詳細而言，如第3圖所示，該些晶片互連元件130係具有一超過該主動面113之線弧段131，該些晶片互連元件130中具有線弧段131之銲線係標示為130a。該線弧段131係跨過該主動面113往鄰近堆疊之晶片延伸，該些晶片互連元件130a並與延伸晶片側保持一適當距離，以避免該些晶片互連元件130a碰觸晶片側邊而受損。此外，在一變化實施例中，該些晶片互連元件130亦可包含矽穿孔或晶側線路。
該些金屬柱140係設置於該內重配置線路層120上，該些金屬柱140係具有複數個端面141，其係較高於該線弧段131，該些金屬柱140之高度係約為25~200um。具體而言，該些金屬柱140係電性連接一扇入凸塊接墊161，該扇入凸塊接墊161係屬於該外重配置線路層160之一部分
如第2及3圖所示，該封膠體150係密封該晶片堆疊 體110與該些晶片互連元件130，該封膠體150係可為一環氧模封化合物(epoxy molding compound,EMC)，通常為熱固性絕緣材料。該封膠體150係具有一平坦面151，該平坦面151係位於該主動面113上且鄰近於該內重配置線路層120，並且該封膠體150係具有一覆蓋於該內重配置線路層120之覆線厚度152，藉以密封該線弧段131與該些金屬柱140並使該些金屬柱140之該些端面141顯露於該平坦面151，以供連接該外重配置線路層160。該線弧段131係不超過該覆線厚度152，以避免後續模封與研磨製程中，該些晶片互連元件130外露於該平坦面151。
該外重配置線路層160係完整形成於該封膠體150之該平坦面151上，該外重配置線路層160係為往周邊扇出之線路型態，並經由該些金屬柱140電性連接至該內重配置線路層120。較佳地，該些金屬柱140之該些端面141係可經研磨而共平面於該平坦面151，以利該外重配置線路層160的平坦化形成並更確實地連接該些金屬柱140。
該些縱向導通機構係設置於該封膠體150之周邊並電性連接該外重配置線路層160至該封膠體150相對於該平坦面151之一封裝堆疊接合面153。再如第2圖所示，該些縱向導通機構係包含複數個貫穿該封膠體150之模封貫孔170以及複數個填入該些模封貫孔170內之導電材料171，以電性連接該外重配置線路層160之複數個扇出接墊162。藉此，達到省略基板厚度之超薄型晶片堆疊並可應用於POP封裝堆疊之功效。具體而言，該些導 電材料171之材質除了可以是焊料，亦可為銅、鋁、鋁銅合金、銅合金、或其他已知導電材料。在一變化實施例中，該些縱向導通機構係可為貼附金屬柱(attach metal pillar)，或是任何已知的縱向導通元件，如垂直導線。由於本發明的上述特定結構，該些縱向導通機構在該封膠體150之孔徑可盡可能接近於POP堆疊裝置的連接端點，故該些縱向導通機構以模封貫孔170與導電材料171之組合為最佳。
如第2圖所示，該封膠體150係可具有一不大於500微米之基板核心厚度，該封膠體150在該主動面113上之覆線厚度152係介於25至200微米之間，故可大幅減少POP整體堆疊厚度。詳細而言，該些導電材料171係可突出於該封膠體150之該封裝堆疊接合面153並迴焊成銲球狀，該些晶片堆疊體110經由迴焊製程後透過該些導電材料171而達成堆疊封裝構造之縱向電性連接。
因此，如第4圖所示，可藉由該些導電材料171進行縱向封裝堆疊，並達到縱向電性傳導，複數個多晶片封裝構造100可堆疊組成為一POP封裝堆疊裝置，其中最頂部之多晶片封裝構造300係大致相同於上述多晶片封裝構造100，但可不需要製作模封貫孔170與填入導電材料171。此外，最底部之多晶片封裝構造100係可另包含複數個銲球180，係設置在對應多晶片封裝構造之該外重配置線路層160之下方，並作為POP封裝堆疊裝置之表面接合端子。較佳地，可在該外重配置線路層160外另鋪一層防銲層，以提供絕緣保護。
關於上述以封膠體取代基板核心之多晶片封裝構造之製造方法係可見於如第5A至5J圖所示之各製程步驟中之元件截面示意圖，其主要步驟說明如後。
首先，如第5A與5B圖所示，提供一晶圓承載系統10(Wafer Support System,WSS)，該晶圓承載系統10係可為具有可剝離黏性之玻璃晶圓。首先，將一晶片111置放在該晶圓承載系統10上，陸續再將多個晶片111堆疊設置於下方晶片上，以提供一晶片堆疊體110。詳細而言，該些晶片111係可利用該黏晶層114相互黏合以固定位置，該黏晶層114係可為晶片貼合材料(DAM)，可避免溢膠污染至該些銲墊112。在完成晶片堆疊之後，最頂部晶片將會有一朝上主動面113。較佳地，該些晶片111係為階梯式錯位堆疊，以不遮蓋該些銲墊112。
之後，如第5C圖所示，利用晶圓製程形成該內重配置線路層120在該晶片堆疊體110之該主動面113上。之後，如第5D圖所示，形成該些晶片互連元件130，其係電性連接上下堆疊晶片111之該些銲墊112，可藉由現行的打線機之銲針(圖未繪出)打線形成。
之後，如第5E圖所示，在該內重配置線路層120上方形成該些金屬柱140，在該些金屬柱140之形成係可在該些晶片互連元件130形成之前或之後，該些金屬柱140形成在後係可防止金屬柱影響打線。不受限制地，在另一實施例中，設置該些金屬柱140之步驟亦可在形成該些晶片互連元件130步驟之前，以利該 些金屬柱140之電鍍形成。較佳地，再如第3圖所示，該些金屬柱140係為銅柱(Cu pillar bump)，該些晶片互連元件130係為金線，使得該些金屬柱140之硬度大於該些晶片互連元件130之硬度，在模封時可以避免該些金屬柱140變形而使該些晶片互連元件130顯露於該封膠體150之該平坦面151。
之後，如第5F圖所示，形成該封膠體150密封該晶片堆疊體110與該些晶片互連元件130，該封膠體150係能以轉移成型(transfer molding)或稱壓模的技術加以形成，或者該封膠體150亦可使用其他已知的模封製程形成，例如壓縮模封、使用一模具之印刷或噴塗等等。
之後，如第5G圖所示，可藉由一研磨頭20使該封膠體150上方研磨出該平坦面151，該平坦面151係位於該主動面113上且鄰近於該內重配置線路層120。該些金屬柱140之該些端面141顯露於該平坦面151。
之後，如第5H圖所示，完整形成該外重配置線路層160於該封膠體150之該平坦面151上。較佳地，該外重配置線路層160係可為往周邊扇出之線路型態，並經由該些金屬柱140電性連接至該內重配置線路層120，該外重配置線路層160可調整線路的佈局密度，以將該些金屬柱140由較密集的配置密度扇出成較疏鬆的配置密度，有助於提升模封貫孔(TMV)之製作良率。
因此，上述「提供一晶片堆疊體」、「形成一內重配置線路層」、「形成複數個晶片互連元件」、「設置複數個金屬柱」 與「形成一封膠體」之步驟係實施於一晶圓承載系統10(Wafer Supporting System,WSS)。如第5I圖所示，完成上述步驟後可移除該晶圓承載系統10。
之後，設置縱向導通機構於該封膠體150之周邊並電性連接該外重配置線路層160至該封膠體150相對於該平坦面151之一封裝堆疊接合面153，一具體實施方法如第5I與5J圖所示，形成複數個模封貫孔170，貫穿該封膠體150之周邊，並利用電鍍、網版印刷或鋼版印刷方式在該些模封貫孔170之內部填入導電材料171，以電性連接該外重配置線路層160。並且，該外重配置線路層160係具有複數個扇出接墊162，其係對準該些模封貫孔170。該些導電材料171係電性連接該些扇出接墊162。具體而言，該些導電材料171係可突出於該封裝堆疊接合面153，該外重配置線路層160用以接合該些金屬柱140之複數個扇入凸塊接墊係電性連接該些間距擴大的扇出接墊162，該外重配置線路層160可調整線路的佈局密度，以將該些金屬柱140由較密集的配置密度扇出成較疏鬆的配置密度，有助於提升製作良率。最後，可迴焊該些導電材料171之突出部位成銲球狀，並經單離切割以製作成如第2圖所示之多晶片封裝構造100。
因此，本發明提供一種以封膠體取代基板核心之多晶片封裝構造，可達到省略基板厚度之超薄型晶片堆疊並可應用於POP封裝堆疊之功效。
以上所揭露的僅為本發明較佳實施例而已，當然不 能以此來限定本發明之權利範圍，因此依本發明權利要求所作的等同變化，仍屬本發明所涵蓋的範圍。
100‧‧‧多晶片封裝構造
110‧‧‧晶片堆疊體
111‧‧‧晶片
112‧‧‧銲墊
113‧‧‧主動面
114‧‧‧黏晶層
120‧‧‧內重配置線路層
130、130a‧‧‧晶片互連元件
140‧‧‧金屬柱
141‧‧‧端面
150‧‧‧封膠體
151‧‧‧平坦面
153‧‧‧封裝堆疊接合面
160‧‧‧外重配置線路層
162‧‧‧扇出接墊
170‧‧‧模封貫孔
171‧‧‧導電材料
172‧‧‧突出部位

Claims (10)

  1. 一種以封膠體取代基板核心之多晶片封裝構造，包含：一晶片堆疊體，主要係由複數個晶片堆疊所組成，每一晶片係具有複數個銲墊，該晶片堆疊體係具有一不被該些晶片堆疊覆蓋之主動面；一內重配置線路層，係形成於該晶片堆疊體之該主動面上；複數個晶片互連元件，係電性連接該些晶片之該些銲墊，該些晶片互連元件係具有一超過該主動面之線弧段；複數個金屬柱，係設置於該內重配置線路層上，該些金屬柱係具有複數個端面，其係較高於該線弧段；一封膠體，係密封該晶片堆疊體與該些晶片互連元件，該封膠體係具有一平坦面，該平坦面係位於該主動面上且鄰近於該內重配置線路層，並且該封膠體係具有一覆蓋於該內重配置線路層之覆線厚度，藉以密封該線弧段與該些金屬柱並使該些金屬柱之該些端面顯露於該平坦面；一外重配置線路層，係完整形成於該封膠體之該平坦面上，該外重配置線路層係為往周邊扇出之線路型態，並經由該些金屬柱電性連接至該內重配置線路層；以及複數個縱向導通機構，係設置於該封膠體之周邊並電性連接該外重配置線路層至該封膠體相對於該平坦面之一封裝堆疊接合面。
  2. 如申請專利範圍第1項所述之以封膠體取代基板核心之多晶片封裝構造，其中該些晶片係為階梯式錯位堆疊，以不遮蓋該些銲墊。
  3. 如申請專利範圍第1項所述之以封膠體取代基板核心之多晶片封裝構造，其中該些晶片互連元件係包含銲線。
  4. 如申請專利範圍第1項所述之以封膠體取代基板核心之多晶片封裝構造，其中該封膠體係具有一不大於500微米之基板核心厚度，該封膠體在該主動面上之覆線厚度係介於25至200微米之間。
  5. 如申請專利範圍第1項所述之以封膠體取代基板核心之多晶片封裝構造，其中該些縱向導通機構係包含複數個貫穿該封膠體之模封貫孔以及複數個填入該些模封貫孔內之導電材料，以電性連接該外重配置線路層。
  6. 如申請專利範圍第5項所述之以封膠體取代基板核心之多晶片封裝構造，其中該些導電材料係突出於該封裝堆疊接合面並迴焊成銲球狀。
  7. 如申請專利範圍第1項所述之以封膠體取代基板核心之多晶片封裝構造，其中該些金屬柱係為銅柱，該些晶片互連元件係為金線，使得該些金屬柱之硬度大於該些晶片互連元件之硬度。
  8. 如申請專利範圍第1項所述之以封膠體取代基板核心之多晶片封裝構造，其中該些金屬柱之該些端面係經研磨而共平面於該平坦面。
  9. 一種以封膠體取代基板核心之多晶片封裝構造之製造方法，包含以下步驟：提供一晶片堆疊體，主要係由複數個晶片堆疊所組成，每一晶片係具有複數個銲墊，該晶片堆疊體係具有一不被該些 晶片堆疊覆蓋之主動面；形成一內重配置線路層於該晶片堆疊體之該主動面上；形成複數個晶片互連元件，係電性連接該些晶片之該些銲墊，該些晶片互連元件係具有一超過該主動面之線弧段；設置複數個金屬柱，係設置於該內重配置線路層上，該些金屬柱係具有複數個端面，其係較高於該線弧段；形成一封膠體，係密封該晶片堆疊體與該些晶片互連元件，該封膠體係具有一平坦面，該平坦面係位於該主動面上且鄰近於該內重配置線路層，並且該封膠體係具有一覆蓋於該內重配置線路層之覆線厚度，藉以密封該線弧段與該些金屬柱並使該些金屬柱之該些端面顯露於該平坦面；完整形成一外重配置線路層於該封膠體之該平坦面上，該外重配置線路層係為往周邊扇出之線路型態，並經由該些金屬柱電性連接至該內重配置線路層；以及設置複數個縱向導通機構於該封膠體之周邊並電性連接該外重配置線路層至該封膠體相對於該平坦面之一封裝堆疊接合面。
  10. 如申請專利範圍第9項所述之以封膠體取代基板核心之多晶片封裝構造之製造方法，其中上述「提供一晶片堆疊體」、「形成一內重配置線路層」、「形成複數個晶片互連元件」、「設置複數個金屬柱」與「形成一封膠體」之步驟係實施於一晶圓承載系統(Wafer Supporting System,WSS)。
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