TWI833306B - 半導體裝置及半導體裝置之製造方法 - Google Patents

半導體裝置及半導體裝置之製造方法 Download PDF

Info

Publication number
TWI833306B
TWI833306B TW111128377A TW111128377A TWI833306B TW I833306 B TWI833306 B TW I833306B TW 111128377 A TW111128377 A TW 111128377A TW 111128377 A TW111128377 A TW 111128377A TW I833306 B TWI833306 B TW I833306B
Authority
TW
Taiwan
Prior art keywords
semiconductor device
resin layer
mentioned
wide
wire
Prior art date
Application number
TW111128377A
Other languages
English (en)
Other versions
TW202335113A (zh
Inventor
脇岡寛之
Original Assignee
日商鎧俠股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商鎧俠股份有限公司 filed Critical 日商鎧俠股份有限公司
Publication of TW202335113A publication Critical patent/TW202335113A/zh
Application granted granted Critical
Publication of TWI833306B publication Critical patent/TWI833306B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4885—Wire-like parts or pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本發明提供一種能提高連接可靠性之半導體裝置及半導體裝置之製造方法。 本實施方式之半導體裝置具備：第1基板，其具有第1面；樹脂層，其設在上述第1面上，且在上述第1基板之相反側具有第2面；及導線，其設置成貫通上述樹脂層而從上述第2面突出；上述導線包含寬幅部，該寬幅部設在從上述第2面突出之上述導線之端部且寬度大於貫通上述樹脂層之上述導線之寬度；上述寬幅部以與上述第2面相接之方式配置。

Description

半導體裝置及半導體裝置之製造方法
本實施方式係關於一種半導體裝置及半導體裝置之製造方法。
半導體封裝中，有時採用積層有複數個封裝之PoP(Package on Package，堆疊封裝)構造。PoP構造中，封裝彼此例如利用焊料而連接。例如，當連接面積不充分時，封裝間之連接部可能會斷裂。
本發明提供一種能提高連接可靠性之半導體裝置及半導體裝置之製造方法。
本實施方式之半導體裝置具備：第1基板，其具有第1面；樹脂層，其設在上述第1面上，且在上述第1基板之相反側具有第2面；及導線，其貫通上述樹脂層而從上述第2面突出；上述導線包含寬幅部，該寬幅部設在從上述第2面突出之上述導線之端部且寬度大於貫通上述樹脂層之上述導線之寬度；上述寬幅部以與上述第2面相接之方式配置。
以下，參照圖式說明本發明之實施方式。本實施方式並不限制本發明。以下之實施方式中，佈線基板之上下方向表示半導體晶片之設置面朝上時的相對方向，有時與基於重力加速度之上下方向不同。圖式係示意性或概念性之圖，各部分之比率等未必與實際相同。說明書及圖式中，對於與上文中針對已提及之圖式所描述之要素相同的要素標註相同符號，並適當省略詳細說明。 (第1實施方式)
圖1係表示第1實施方式之半導體裝置1之結構之一例的剖視圖。半導體裝置1具有例如複數個封裝積層而成的構造。半導體裝置1具備積層之封裝10、20。
繼而，對於封裝10之結構進行說明。
封裝10具備佈線基板11、半導體晶片12、導線13、樹脂層14及導線15。
佈線基板11例如為印刷基板等基板。佈線基板11具有面F11a(第1面)、面F11b、焊墊P11a～P11c、通孔111及佈線層(未圖示)。
面F11b係與面F11a相反側之面。焊墊P11a設在面F11a上，且與導線13連接。焊墊P11b設在面F11a上，且與導線15連接。焊墊P11c設在面F11b上。通孔111以貫通佈線基板11之方式從佈線基板11之面F11a到達面F11b，電性連接焊墊P11b與焊墊P11c。
焊墊P11a～P11c及通孔111之材料採用導電性材料。
半導體晶片12例如為NAND型閃存的記憶體晶片、控制記憶體晶片之控制晶片、或是任意的搭載有LSI(Large Scale Integration，大規模積體電路)之半導體晶片。半導體晶片12之上表面上具有焊墊P12。焊墊P12之材料採用導電性材料。
而且，半導體晶片12設在面F11a上。半導體晶片12例如被樹脂層14覆蓋。半導體晶片12例如經由焊墊P12、導線13、焊墊P11a、佈線基板11內之佈線(未圖示)、及焊墊P11b而與導線15電性連接。而且，半導體晶片12亦可積層2層以上。
導線13例如為環狀導線。導線13電性連接焊墊P12與焊墊P11a。導線13之材料採用例如Au等導電性金屬。
樹脂層14設在佈線基板11之面F11a上。樹脂層14在佈線基板11之相反側具有面F14(第2面)。樹脂層14例如為介電密封材等密封材。
樹脂層14採用例如酚類樹脂、聚醯亞胺類樹脂、聚醯胺類樹脂、丙烯酸類樹脂、環氧類樹脂、PBO(p-phenylene benzobisoxazole，聚對苯撐苯并二噁唑)類樹脂、矽酮類樹脂、苯并環丁烯類樹脂等樹脂、或其等之混合材料、複合材料等有機絕緣材料。
導線15以貫通樹脂層14之方式設置。導線15例如以從焊墊P11b貫通樹脂層14而從面F14突出之方式設置。導線15例如為以沿大致垂直於面F11a之方向延伸之方式設置的柱狀電極。導線15電性連接封裝10之佈線基板11與封裝20之佈線基板21。導線15之材料採用例如Au等導電性材料。而且，關於與佈線基板21連接之導線15之上端部的細節，將參照圖2而於下文進行說明。
繼而，對封裝20之結構進行說明。
封裝20以與樹脂層14之面F14相向之方式設置在封裝10上。封裝20具備佈線基板21、半導體晶片22、導線23及樹脂層24。
佈線基板21例如為印刷基板等基板。佈線基板21具有面F21a、面F21b、焊墊P21a～P21c、通孔211及佈線層(未圖示)。
面F21b係位於面F21a相反側之面。焊墊P21a～P21c及通孔211之結構與例如封裝10中之焊墊P11a～P11c及通孔111之對應結構大致相同。
佈線基板21以與樹脂層14之面F14相向之方式設置。而且，在導線15之上端部與佈線基板21之焊墊P21c之間設有焊料17。而且，還可在導線15與焊料17之連接部形成合金層。
半導體晶片22例如與封裝10中之半導體晶片12之對應結構大致相同。半導體晶片22之上表面上具有焊墊P22。焊墊P22之材料採用導電性材料。而且，半導體晶片22亦可積層2層以上。
導線23例如與封裝10中之導線13之對應結構大致相同。
樹脂層24例如與封裝10中之樹脂層14之對應結構大致相同。
繼而，將對導線15之上端部之結構進行說明。
圖2係表示第1實施方式之導線15之端部之結構之一例的剖視圖。圖2係圖1所示之虛線框D的放大圖。而且，圖2中，示出6根導線15。
導線15包含貫通部151及寬幅部152。
貫通部151係貫通樹脂層14之導線15的一部分。亦即，貫通部151之周圍被樹脂層14覆蓋。
寬幅部152設在從樹脂層14之面F14突出之導線15之端部。寬幅部152之寬度大於貫通部151之寬度。寬幅部152之寬度係指與面F11a(面F14)大致平行的方向上之寬度。寬幅部152以與面F14相接之方式配置。因此，被樹脂層14包圍之貫通部151之寬度大致固定，導線15之寬度在從樹脂層14之面F14伸出之位置開始變大。
寬幅部152之形狀例如為大致球狀，但並不限於此，亦可為其他形狀。
複數個寬幅部152與圖1所示之設置成和面F14相向之佈線基板21電性連接。如上所述，寬幅部152例如利用焊料17而與佈線基板21之焊墊P21c連接。藉由設置寬幅部152，能增大寬幅部152與焊料17之接觸面積、亦即導線15與焊料17之連接面積。藉此，能提高連接可靠性。
圖2所示之示例中，不論面F14上之任意位置如何，複數個寬幅部152之尺寸(大小)均大致相同。亦即，複數個寬幅部152之大小的偏差小。
繼而，針對半導體裝置1之製造方法進行說明。
圖3A～圖3F係表示第1實施方式之半導體裝置1之製造方法之一例的剖視圖。而且，以下，主要將對封裝10之製造方法進行說明。
首先，如圖3A所示，準備佈線基板11。在佈線基板11形成有焊墊P11a～P11c及通孔111。
繼而，如圖3B所示，在佈線基板11之面F11a上設置半導體晶片12(晶片安裝)。
繼而，如圖3C所示，形成導線13。導線13以電性連接半導體晶片12之焊墊P12與佈線基板11之焊墊P11a之方式形成。
繼而，如圖3D所示，在佈線基板11之面F11a的上方形成導線15。導線15例如以從焊墊P11b沿大致垂直於面F11a的方向延伸之方式形成。
繼而，如圖3E所示，形成樹脂層14。更詳細而言，以導線15之端部露出之方式在面F11a上形成樹脂層14，該樹脂層14在佈線基板11之相反側具有面F14。樹脂層14以覆蓋導線15之上端部以外的部分及半導體晶片12之方式形成。例如，在用於形成樹脂層14的模具內配置可供導線15之上端部貫通的膜，藉此，使導線15之上端部從樹脂層14露出。
繼而，如圖3F所示，在導線15的前端(上端部)形成寬幅部152。更詳細而言，在從面F14露出之導線15之端部形成寬幅部152，該寬幅部152之寬度大於貫通樹脂層14之導線15(貫通部151)之寬度。寬幅部152例如藉由利用雷射使導線15之端部熔融而形成。已熔融之導線15之上端部因表面張力而呈大致球狀。之後，使已熔融之導線15冷卻，形成大致球狀的寬幅部152。
而且，導線15之端部之熔融方式並不限於雷射，亦可採用放電等方式。而且，寬幅部152的形成方法亦可為熔融以外的方法。
而且，為了在形成樹脂層14後形成寬幅部152，而使寬幅部152的下端部與面F14相接。其原因在於，導線15之端部熔融到面F14之位置。藉此，熔融之導線15之端部之量取決於面F14之位置。結果，能以複數個寬幅部152之大小的偏差減小之方式形成寬幅部152。
在圖3F所示之步驟中，完成封裝10。之後，在封裝10上設置封裝20，藉此，完成圖1所示之半導體裝置1。寬幅部152例如利用焊料17而與封裝20內之佈線基板21之焊墊P21c連接。
而且，在圖3F所示之步驟之前，亦可例如利用銑床來研磨導線15之上端部，以使導線15之高度一致。藉此，不論位於面F14上的什麼位置，都能使寬幅部152之大小大致相同。亦即，能減小寬幅部152之大小的偏差。
如以上所述，根據第1實施方式，導線15包含寬幅部152。寬幅部152設在從面F14突出之導線15之端部，且寬度大於貫通樹脂層14之導線15(貫通部151)之寬度。藉此，能增大導線15與焊料17之連接面積。結果，能提高連接可靠性。
而且，第1實施方式中，如圖2所示，寬幅部152以與樹脂層14之面F14相接之方式配置。藉此，當連接導線15與佈線基板21時，寬幅部152能更適當地支持佈線基板21(封裝20)。
而且，寬幅部152與貫通部151由相同材料一體構成。亦即，在寬幅部152與貫通部151之間不存在連接部。藉此，對於容易發生應力集中之面F14，能提高強度。結果，能夠提高連接可靠性。
作為比較例，將對於未設寬幅部152之情形進行說明。當未設寬幅部152時，導線15與焊料17之連接面積取決於導線15(貫通部151)之寬度。該情形時，可能無法獲得充分之連接面積，從而容易發生斷裂等情況。而且，在作為導線15與焊料17之連接部之面F14上形成有合金層。由於面F14上容易發生應力集中，故而容易因合金層之剪切而發生斷裂，而且，容易降低物理抗衝擊性。
對此，第1實施方式中，藉由設置寬幅部152，能增大導線15與焊料17之連接面積。藉此，能抑制導線15與焊料17之連接部的斷裂。而且，在作為容易發生應力集中之部位之面F14上，存在從貫通部151到寬幅部152之材料都相同之導線15，而不存在導線15與焊料17之連接部(合金層)。藉此，能緩和剪切力，而且能提高抗衝擊性。
而且，第1實施方式中，如圖3E及圖3F所示，在形成樹脂層14之後形成寬幅部152。藉此，形成寬幅部152時之熱能容易地經過樹脂層14而散發。結果，能減少對佈線基板11及半導體晶片12等元件之熱損傷。
而且，因利用熔融形成有寬幅部152，故而能抑制導線15之高度之偏差，減小半導體裝置1之封裝厚度(高度)。即便以高度相同之方式形成複數個導線15，導線15之實際高度有時亦會存在偏差。從面F14突出之導線15因熔融而高度降低，在寬度方向變大。因此，寬幅部152之高度之偏差小於熔融前之導線15之高度之偏差。藉此，能減小半導體裝置1之封裝厚度(高度)。
而且，半導體裝置1所具備之封裝並不限於積層2層，亦可積層3層以上。
而且，封裝20亦可為單個佈線基板。該情形時，單個佈線基板上並不安裝PoP(Package on Package)構造，而是安裝封裝10。 (第2實施方式)
圖4係表示第2實施方式之導線15之端部之結構之一例的剖視圖。第2實施方式與第1實施方式之不同之處在於，寬幅部152之大小會根據面F14上之位置而有所不同。
封裝10具備各自包含寬幅部152之複數個導線15。複數個寬幅部152根據面F14上之位置而具有不同之大小。
此處，圖1所示之佈線基板21有時會產生翹曲。例如，當圖1所示之佈線基板21下凸翹曲時，外周部之寬幅部152與佈線基板21之焊墊P21c之間可能會產生連接不良。
因此，複數個寬幅部152根據佈線基板21之翹曲而具有不同之高度。寬幅部152之高度係與面F11a(面F14)大致垂直的方向上之高度。藉此，能更適當地連接導線15與佈線基板21。圖4所示之示例中，寬幅部152從面F14之中心部向外周部變高。而且，複數個寬幅部152之高度並不限於圖4所示之示例。
第2實施方式之半導體裝置1之其他結構與第1實施方式之半導體裝置1之對應結構相同，因此省略其詳細說明。
圖5係表示第2實施方式之導線15之端部之形成方法之一例的剖視圖。圖5表示圖3E所示之步驟的放大剖視圖。
形成導線13之後(參照圖3C)，以使從面F14露出之導線15之高度不同之方式，形成根據面F11a上之位置而具有不同高度之複數個導線15。複數個導線15形成為變化高度，以對應圖1所示之佈線基板21之翹曲。圖5所示之示例中，導線15形成為從面F14之中心部向外周部變高。
繼而，以與圖3E所示之步驟同樣之方式形成樹脂層14。在圖5所示之示例中，導線15形成為從面F14之中心部向外周部變高。
繼而，在複數個導線15各自之端部形成根據面F14上之位置而具有不同大小的寬幅部152。寬幅部152係由導線15之突出部分熔融而形成。因此，寬幅部152之大小取決於圖5中從面F14突出之導線15之高度。
如此，在形成樹脂層14後形成寬幅部152，故而藉由調整形成之導線15之高度，能更便於調整寬幅部152之大小(高度)。
如第2實施方式所述，寬幅部152之大小亦可根據面F14上之位置而有所不同。第2實施方式之半導體裝置1能獲得與第1實施方式相同的效果。 (第3實施方式)
圖6係表示第3實施方式之導線15之端部之結構之一例的剖視圖。第3實施方式與第1實施方式之不同之處在於，寬幅部152之大小根據面F14上之位置而有所不同。
複數個寬幅部152根據面F14中之導線15間之間隔而具有不同之寬度。
面F14具有區域R1及區域R2。關於面F14中之導線15之密度，區域R2中之密度高於區域R1中之密度。圖6所示之示例中，區域R1係面F14之中心部之區域，區域R2例如為面F14之外周部之區域。而且，區域R1、R2之位置並不限於圖6所示之示例。
區域R1中鄰接之導線15間之距離為距離L1。區域R2中鄰接之導線15間之距離係距離L2。距離L2比距離L1短。
此處，當區域R2中寬幅部152之寬度過大時，鄰接之寬幅部152會彼此接觸，從而可能發生短路。
因此，區域R2中寬幅部152之寬度小於區域R1中寬幅部152之寬度。藉此，能抑制密度較高的區域R2內之寬幅部152彼此接觸而發生短路的情況。
而且，區域R2中，寬幅部152之數量比較多，故而即便寬幅部152之寬度小，寬幅部152亦能支持佈線基板21(封裝20)。另一方面，區域R1中，寬幅部152之寬度比較大，故而即便寬幅部152之數量少，寬幅部152亦能支持佈線基板21(封裝20)。藉此，根據導線15之配置能獲得更適當之連接面積，從而能提高良率。
第3實施方式之半導體裝置1之其他結構與第1實施方式之半導體裝置1之對應結構相同，因此省略其詳細說明。
圖7係表示第3實施方式之導線15之端部之形成方法之一例的剖視圖。圖7表示圖3E所示之步驟的放大剖視圖。
而且，第3實施方式之導線15之端部之形成方法與第2實施方式之導線15之端部之形成方法大致相同，僅導線15之高度及配置不同。
複數個導線15根據密度、或導線15間之距離而形成不同高度。圖7所示之示例中，導線15在區域R1中形成得比較高，在區域R2中形成得比較低。圖6所示之示例中，寬幅部152在區域R1中寬度比較大，在區域R2中寬度比較小。
從而，在形成樹脂層14後形成寬幅部152，故而藉由調整形成之導線15之高度，能更便於調整寬幅部152之大小(寬度)。
如第3實施方式所述，寬幅部152之大小亦可根據面F14上之位置而有所不同。第3實施方式之半導體裝置1能獲得與第1實施方式相同的效果。
已對本發明之若干實施方式進行了說明，但該等實施方式僅作為示例提出，並非用於限定發明之範圍。該等實施方式可以其他各種形態實施，且可在不脫離發明宗旨之範圍內進行多種省略、置換、變更。該等實施方式及其變形皆屬於發明之範圍及宗旨內，亦屬於專利申請範圍所記載之發明及與其等價之範圍內。 [相關申請]
本申請享有以日本專利申請2022-025975號(申請日：2022年2月22日)為基礎申請之優先權。本申請藉由參照該基礎申請而包含基礎申請之全部內容。
1:半導體裝置 10:封裝 11:佈線基板 12:半導體晶片 13:導線 14:樹脂層 15:導線 17:焊料 20:封裝 21:佈線基板 22:半導體晶片 23:導線 24:樹脂層 111:通孔 151:貫通部 152:寬幅部 211:通孔 D:虛線框 F11a:面 F11b:面 F14:面 F21a:面 F21b:面 L1,L2:距離 P11a～P11c:焊墊 P12:焊墊 P21a～P21c:焊墊 P22:焊墊 R1:區域 R2:區域
圖1係表示第1實施方式之半導體裝置之結構之一例的剖視圖。 圖2係表示第1實施方式之導線之端部之結構之一例的剖視圖。 圖3A係表示第1實施方式之半導體裝置之製造方法之一例的剖視圖。 圖3B係繼圖3A之後表示半導體裝置之製造方法之一例的剖視圖。 圖3C係繼圖3B之後表示半導體裝置之製造方法之一例的剖視圖。 圖3D係繼圖3C之後表示半導體裝置之製造方法之一例的剖視圖。 圖3E係繼圖3D之後表示半導體裝置之製造方法之一例的剖視圖。 圖3F係繼圖3E之後表示半導體裝置之製造方法之一例的剖視圖。 圖4係表示第2實施方式之導線之端部之結構之一例的剖視圖。 圖5係表示第2實施方式之導線之端部之形成方法之一例的剖視圖。 圖6係表示第3實施方式之導線之端部之結構之一例的剖視圖。 圖7係表示第3實施方式之導線之端部之形成方法之一例的剖視圖。
1:半導體裝置
10:封裝
11:佈線基板
12:半導體晶片
13:導線
14:樹脂層
15:導線
17:焊料
20:封裝
21:佈線基板
22:半導體晶片
23:導線
24:樹脂層
111:通孔
211:通孔
D:虛線框
F11a:面
F11b:面
F14:面
F21a:面
F21b:面
P11a~P11c:焊墊
P12:焊墊
P21a~P21c:焊墊
P22:焊墊

Claims (9)

  1. 一種半導體裝置，其具備：第1基板，其具有第1面；樹脂層，其設在上述第1面上，且在上述第1基板之相反側具有第2面；及導線，其貫通上述樹脂層而從上述第2面突出；上述導線包含寬幅部，該寬幅部設在從上述第2面突出之上述導線之端部且寬度大於貫通上述樹脂層之上述導線之寬度；上述寬幅部以與上述第2面相接之方式配置；其中上述半導體裝置係具備分別包含上述寬幅部之複數個上述導線，複數個上述寬幅部根據上述第2面上之位置而具有不同的直徑，複數個上述寬幅部與設置成和上述第2面相向之第2基板電性連接，複數個上述寬幅部根據上述第2基板之翹曲而具有不同之高度。
  2. 如請求項1之半導體裝置，其中上述導線沿大致垂直於上述第1面之方向延伸。
  3. 如請求項1之半導體裝置，其中複數個上述寬幅部根據上述第2面上之上述導線間之間隔而具有不同之寬度。
  4. 如請求項3之半導體裝置，其中 上述第2面具有第1區域、及上述第2面中上述導線之密度高於上述第1區域的第2區域，上述第2區域中上述寬幅部之寬度小於上述第1區域中上述寬幅部之寬度。
  5. 如請求項1之半導體裝置，其中上述寬幅部與貫通上述樹脂層之上述導線由相同材料一體構成。
  6. 如請求項1之半導體裝置，其中上述第1基板還具有設在上述第1面上之焊墊，上述導線係以從上述焊墊貫通上述樹脂層而從上述第2面突出之方式設置。
  7. 如請求項1之半導體裝置，其還具備設在上述第1面上且被上述樹脂層覆蓋之半導體晶片，上述半導體晶片與上述導線電性連接。
  8. 一種半導體裝置之製造方法，其具備：在具有第1面之第1基板之上述第1面的上方形成導線，以上述導線之端部露出之方式，在上述第1面上形成樹脂層，該樹脂層在上述第1基板之相反側具有第2面，在從上述第2面露出之上述導線之端部，形成寬度大於貫通上述樹脂層之上述導線之寬度的寬幅部， 以使從上述第2面露出之上述導線之高度不同之方式，形成根據上述第1面上之位置而具有不同高度之複數個上述導線，在複數個上述導線各自之端部，形成根據上述第2面上之位置而具有不同大小的上述寬幅部。
  9. 如請求項8之半導體裝置之製造方法，其還具備藉由使上述導線之端部熔融，而在從上述第2面露出之上述導線之端部形成上述寬幅部。
TW111128377A 2022-02-22 2022-07-28 半導體裝置及半導體裝置之製造方法 TWI833306B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2022025975A JP2023122330A (ja) 2022-02-22 2022-02-22 半導体装置およびその製造方法
JP2022-025975 2022-02-22

Publications (2)

Publication Number Publication Date
TW202335113A TW202335113A (zh) 2023-09-01
TWI833306B true TWI833306B (zh) 2024-02-21

Family

ID=87574535

Family Applications (1)

Application Number Title Priority Date Filing Date
TW111128377A TWI833306B (zh) 2022-02-22 2022-07-28 半導體裝置及半導體裝置之製造方法

Country Status (4)

Country Link
US (1) US20230268281A1 (zh)
JP (1) JP2023122330A (zh)
CN (1) CN116682798A (zh)
TW (1) TWI833306B (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8404520B1 (en) * 2011-10-17 2013-03-26 Invensas Corporation Package-on-package assembly with wire bond vias
US9209110B2 (en) * 2014-05-07 2015-12-08 Qualcomm Incorporated Integrated device comprising wires as vias in an encapsulation layer
TW201705386A (zh) * 2015-07-29 2017-02-01 力成科技股份有限公司 以封膠體取代基板核心之多晶片封裝構造
TW201739022A (zh) * 2015-12-25 2017-11-01 英特爾公司 導線貫穿模具連接之設備及方法
TW202002189A (zh) * 2018-06-27 2020-01-01 力成科技股份有限公司 封裝結構及其製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8404520B1 (en) * 2011-10-17 2013-03-26 Invensas Corporation Package-on-package assembly with wire bond vias
US9209110B2 (en) * 2014-05-07 2015-12-08 Qualcomm Incorporated Integrated device comprising wires as vias in an encapsulation layer
TW201705386A (zh) * 2015-07-29 2017-02-01 力成科技股份有限公司 以封膠體取代基板核心之多晶片封裝構造
TW201739022A (zh) * 2015-12-25 2017-11-01 英特爾公司 導線貫穿模具連接之設備及方法
TW202002189A (zh) * 2018-06-27 2020-01-01 力成科技股份有限公司 封裝結構及其製造方法

Also Published As

Publication number Publication date
US20230268281A1 (en) 2023-08-24
JP2023122330A (ja) 2023-09-01
CN116682798A (zh) 2023-09-01
TW202335113A (zh) 2023-09-01

Similar Documents

Publication Publication Date Title
US8659151B2 (en) Semiconductor device and manufacturing method thereof
JP5341337B2 (ja) 半導体装置及びその製造方法
US11437326B2 (en) Semiconductor package
US20170358557A1 (en) Package-on-package structure and manufacturing method thereof
US8507805B2 (en) Wiring board for semiconductor devices, semiconductor device, electronic device, and motherboard
USRE45932E1 (en) Semiconductor device and method of manufacturing the same
JP5501562B2 (ja) 半導体装置
JP5372346B2 (ja) 半導体装置及びその製造方法
KR20140012677A (ko) 반도체 장치
JP2010010269A (ja) 半導体装置、半導体装置製造用中間体およびそれらの製造方法
KR102573760B1 (ko) 반도체 패키지
TWI833306B (zh) 半導體裝置及半導體裝置之製造方法
JP2014192171A (ja) 半導体装置及びその製造方法
US6812567B2 (en) Semiconductor package and package stack made thereof
JP2004128290A (ja) 半導体装置
JP2010272734A (ja) 半導体装置及びその製造方法
JP2009283835A (ja) 半導体装置及びその製造方法
KR102540829B1 (ko) 반도체 패키지, 반도체 패키지 제조방법 및 재배선 구조체 제조방법
US9117741B2 (en) Semiconductor device
JP2011061055A (ja) 半導体装置の製造方法
JP4917979B2 (ja) 半導体装置及びその製造方法
KR101123797B1 (ko) 적층 반도체 패키지
US20230317590A1 (en) Semiconductor package
TW202335215A (zh) 半導體裝置及半導體裝置的製造方法
JP2005057099A (ja) 半導体装置およびその製造方法