TW201633467A - 用於積體電路封裝體之有機－無機混合結構 - Google Patents

用於積體電路封裝體之有機－無機混合結構 Download PDF

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Publication number
TW201633467A
TW201633467A TW104138580A TW104138580A TW201633467A TW 201633467 A TW201633467 A TW 201633467A TW 104138580 A TW104138580 A TW 104138580A TW 104138580 A TW104138580 A TW 104138580A TW 201633467 A TW201633467 A TW 201633467A
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Taiwan
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die
package
sash
integrated circuit
perforations
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TW104138580A
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TWI616988B (zh
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黃普洛里
亨利 蘇
啓楷 鐘
萊恩 王
王瓊斯
謝丹尼爾
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英特爾公司
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Abstract

本發明說明一種用於積體電路封裝體之有機-無機混合結構。在一個舉例中，一積體電路封裝體包括：一陶瓷框架、一積體電路晶粒及一再分配層。該陶瓷框架具有一頂側及一底側，該頂側具有一框格，該框格具有一底板及複數個在該底板中的導電穿孔。該積體電路晶粒被附著至該底板並位於該等導電穿孔之上。該再分配層位於底側並連接至該等導電穿孔。

Description

用於積體電路封裝體之有機-無機混合結構 發明領域
本說明是有關於一種積體電路封裝體，尤其是在一陶瓷框架中之一晶粒的封裝體。
發明背景
隨著計算裝置越做越小且帶有越來越多的接線，IC(積體電路)晶粒封裝體便發展成包括超過一個的晶粒於一單一封裝體中。因為晶粒一般遠小於一封裝體，所以額外的晶粒並不會顯著地增加該封裝體的尺寸。藉由結合複數個晶粒於一單一的封裝體中，相應地使該裝置只需要較少的封裝體而使該裝置變得更小並減少該等晶粒之間的距離。在不同封裝體的兩個晶粒之間的該較長連接路徑可能會減少該等晶粒之間的該資料通訊速度。這些較長的連接會有較多的電抗及較多的阻抗，而更容易接受到雜訊與干擾。所有的這些特性會限制能夠在一特定時間間隔被傳遞經該資料的資料量。
一封裝體內的晶粒係藉由堆疊該等晶粒且將一個晶粒的前側附著到其他晶粒的背側而被連接。穿過該晶 粒背側的通孔能允許該等晶粒直接連接。一封裝體內的該等晶粒也可利用一中介件而連接。有各種不同的中介件配置，但其中大部分是將該等晶粒附著到該中介件，且該中介件用於在該等晶粒之間傳遞訊號，且或許也可將該等訊號傳遞至一封裝基板。
依據本發明之一實施例，係特地提出一種積體電路封裝體，包含：一陶瓷框架，具有一頂側及一底側，該頂側具有一框格，該框格具有一底板及在該底板的複數個導電穿孔；一積體電路晶粒，其附著至位於該等導電穿孔之上的該底板；及一再分配層，位於該底側並連接至該等導電穿孔。
2‧‧‧系統主機板
4‧‧‧處理器
6‧‧‧通訊封裝體(通訊晶片)
8‧‧‧揮發性記憶體(動態隨機存取記憶體)
9‧‧‧非揮發性記憶體(唯讀記憶體)
10‧‧‧大容量儲存裝置(大容量記憶體)
12‧‧‧圖形處理器(圖形中央處理器)
14‧‧‧晶片組
16‧‧‧天線
18‧‧‧顯示器(觸控螢幕顯示器)
20‧‧‧觸控螢幕控制器
22‧‧‧電池
24‧‧‧功率放大器
26‧‧‧全球定位系統裝置
28‧‧‧羅盤
30‧‧‧喇叭
32‧‧‧照像機
34‧‧‧麥克風
36‧‧‧音頻晶片
100‧‧‧計算裝置
101、201‧‧‧封裝體
102、204、324‧‧‧陶瓷框架
104、216、218、220、222、224、338‧‧‧框格
106、108、110、346、348、352‧‧‧晶粒
112、126、132、204、330、332、336‧‧‧穿孔
114、350、354‧‧‧填充材
115‧‧‧底板
116、208、320‧‧‧再分配層
118‧‧‧路由層
120、314、316‧‧‧通孔
124‧‧‧側壁
130、302‧‧‧底蓋
134、322‧‧‧墊
138‧‧‧主機板
212、234‧‧‧被動裝置
214‧‧‧中央處理器晶粒
232‧‧‧晶片組晶粒
236‧‧‧記憶體晶粒
302、304、324、326‧‧‧板坯
308‧‧‧銅層
310‧‧‧圖案化的銅層
312‧‧‧ABF層
318‧‧‧水平銅層
340、342‧‧‧焊球(凸塊)
本發明的實施例是用以舉例說明，而不是作為限制用，且在附圖的圖示中，類似的標號指的是相似的元件。
圖1是一實施例之使用一陶瓷框架的一堆疊晶粒封裝體的剖面側視圖。
圖2是一實施例之使用一陶瓷框架的一第二堆疊晶粒封裝體的局部透明之立體視圖。
圖3-16是一實施例之製造一陶瓷框架的製程階段之剖面側視圖。
圖17-18是一實施例之利用圖15的該陶瓷框架組裝一封裝體的製程階段之剖面側視圖。
圖19是一實施例的一將一封裝體與一陶瓷框架 合併的計算裝置之方塊圖。
較佳實施例之詳細說明
如在此所述，一陶瓷框架可允許許多IC(積體電路)晶粒被封裝在較小的空間中。該等晶粒以至少二層堆疊入框架的框格中。複數個框格可被用於：允許十個或以上的IC晶粒安裝在框架中以創造一單一的封裝體。該形成有框格的陶瓷框架不需考慮任何對一矽中介件的需求，並提供用於晶粒之間I/O(輸入/輸出)訊號之大量的高速資料頻寬。
圖1是具有將三個IC晶粒106、108、110一起封裝進一陶瓷框架102之一封裝體101的一個舉例的剖面側視圖。該陶瓷框架具有將尺寸形成可保持該等所欲之晶粒的四個外部側壁124。在一個舉例中，該等壁為大約100-400μm高。一框格104形成於這四個側壁內且從該等側壁的頂部起算大約為50-300μm深。該框格是圍繞該封裝體的中心而形成，且大到足以容納一個或多個晶粒並排在該框格的一平垣的底面上。該框格的該等側壁會厚到足以容納從該等側壁的頂部延伸至該框架的底部的鑽孔126。有許多這樣的穿孔而使其足以因應其中一個晶粒的該等I/O需求。
該框格的底板115具有從該框格的底板鑽設到貫穿該陶瓷框架的底部的一陣列的穿孔112。這些穿孔會被充填或鍍上導電材料。在一些實施例中，該等穿孔會以純錫或以錫/銅合金電鍍。該等穿孔會與該等I\O墊或該等晶粒的 焊盤對準，以使附著至該框格104的底板115的該二晶粒106、108容易地焊接定位在該等穿孔上。該等晶粒可附著在由該等穿孔內部之該電鍍的純錫或錫/銅合金所形成的凸塊上。
藉由充填該等穿孔且接著使該陶瓷框架在低溫下前進通過一回焊爐，該電鍍的金屬就會在該爐的加熱下於穿孔中向上及向下膨脹，以在各端形成純錫或錫/銅合金的凸塊。利用一第二次回焊爐製程，這些凸塊允許該等晶粒直接附著至該電鍍材料。這項技術可避免要分開進行表面加工製程及微焊球附著製程的情形。然而，各種不同的其他技術可被利用來使這些孔可導電並提供焊接凸塊以附著晶粒及被動裝置。
在將該等晶粒附著到該框格之該板後，一填充材114可被用來隔離與保護該等焊接連接件。
在一框格深度足以在三側上完全地將最初的二個晶粒106、108封閉的情形下，該框架的該等側壁126會向上延伸到該框格中之該二個晶粒的該等頂部之上。依據特定的實施方式，在框格中可有多於或少於二個的晶粒。二個晶粒是作為舉例而顯示。這些側壁可以該封裝體只包含該二個晶粒的狀態原樣留下。
如所示地，一第三之較大的晶粒110可用來覆蓋該框格的頂部。此較大的晶粒可以是更大的、或是藉以將其附著到一較大之基板或其他較大的結構而將其做成具有一較大的形狀因子。該較大的晶粒是從一個側壁至另一側 壁延伸穿越該框格。在此方式下，該較大的晶粒會密封該框格以保護該框格內部的該等二個晶粒及該等焊接連接件。該較大的晶粒可用金屬層或介電層、樹脂包覆成型(overmold)或以任意的各種其他方式來密封。該頂部晶粒110可被用於密封該框格，或是使該頂部晶粒於一側或多側上小於該框格開口。在該晶粒的該等邊緣之間的該間隙及該相對應之側壁可用於允許在框格層中進行空氣循環，或是以另外的材料將其密封。
該頂部晶粒110是在該等側壁的該等穿孔126上方附著至該等側壁。可將這些穿孔以導電材料鍍上或充填，並且以無電鍍鎳之類的導電材料覆蓋。該等穿孔是被配置且排列成與該頂部晶粒的連接墊或焊盤接觸。可相應地將該頂部晶粒焊接定位於該框格的該頂部之上，而利用該等穿孔連接至外部構件。
在該框格104之底板115中的該等穿孔112及在該等側壁中的該等穿孔126全部都是貫穿到該框架的該底面而被鑽穿。所有的晶粒連接件在之後會延伸穿過至此一表面。一再分配層116是形成在該陶瓷框架的該底面上，以將該等晶粒互相連接並與外部構件形成連接。在該圖示之例中，該框格中的其中一個晶粒106是一CPU(中央處理器)，而另一個晶粒108是一晶片組。這些晶粒通常是透過一高速匯流排而耦合在一起。可透過該再分配層116形成此匯流排的該等電連接。該頂部晶粒110為記憶體及功能IC，例如SDRAM(靜態動態隨機存取記憶體)或DRAM(動態隨機存 取記憶體)。根據該系統架構，可將該記憶體透過該再分配層直接連接到該CPU或晶片組。
該再分配層可用任意的各種不同方式來形成。在一些實施例中，一BBUL(內建非凹凸層)是以複數層的水平路由118及在各路由層之間的介電質而形成。該等路由層是利用行經介該電質至該等路由層的通孔120而被連接。或者，可將矽、樹脂、預浸材或其他類型的基板形成具有一個或多個路由層，以將該等穿孔112、126互連且連至外部連接件。
該再分配層是藉一陶瓷底蓋130而完成。可使用與該陶瓷框架相同的材料或是不同的材料來製造該底蓋。該底蓋具有各用以供再分配層通過以連接到外部之鑽設的穿孔132。這些穿孔是以純錫或錫/銅合金充填或電鍍。可將該等穿孔用與上述對於該陶瓷框架中之該等穿孔相同的方式進行處理。在該等穿孔上側具有連接至該再分配層中的一相對應的連接點之一蓋或墊。在下側，各穿孔各具有一以例如錫/銅形成的焊球、焊盤或墊134。這些可以利用如上述之該電鍍物的膨脹來形成，但本發明並不受限於此。
可在該陶瓷底蓋的該底部提供一C4(控制塌陷晶片連接件)或BGA(球柵陣列)。根據例如深盲雷射鑽孔之雷射鑽孔與電鍍錫或錫/銅技術的準確度，凸塊尺寸可降至30-50μm等級。該底部焊球可允許將該封裝體焊接至一主機板138、一插槽、或是其他將封裝體連接至外部裝置的基 板。根據該特定的實施方式，這些裝置可包括電源、使用者介面構件、資料I/O介面構件、天線、及其他類型的構件。
圖1的例子，是將一工作站或一電腦之一主要的部分封裝在一單一的陶瓷框架中。記憶體晶粒110可包括RAM，以將該封裝體只連接至外部的大容量儲存器、使用者介面及圖形處理器。
圖2是根據一具有複數個框格216、218、220、222、224之陶瓷框架204形成的一較大的封裝體201之局部透明之立體視圖。利用較多的框格，可將較多的晶粒封裝在該相同的框架204中。將一再分配層208附著到或形成於該框架的底部，且將一陶瓷底蓋206附著到該再分配層的底部。該再分配層會涵蓋該框架的整個底面延伸而位於該等複數個框格之間。這樣做，不僅如圖1在相同框格中的晶粒之間，連在不同框格中的晶粒之間皆可允許形成連接。這些連接是在不跑出該封裝體201之外的情形下形成，因此該等連接會更短且更可靠。
該等框格可被製作成不同尺寸且具有不同的穿孔配置，以容納不同尺寸及型式的晶粒。在圖示之範例中，有五個不同的框格。該第一框格216具有一CPU晶粒214及耦合至該晶粒或是耦合於該等晶粒與其他外部連接件之間的被動裝置212。可將該等被動裝置用於不同的用途。該等被動裝置可被用於例如電源調節或高速資料傳訊調節。一記憶體晶粒214被安裝在該框格上以密封該框格並對該CPU提供高速記憶體。
第二框格218具有一晶片組晶粒232、被動裝置234、及一在該框格與該晶片組之上的記憶體晶粒236。因此，該晶片組可如圖1所示地與該CPU位於相同框格中，或是如所示地在一分隔的框格中。該等框格之特定配置及用途可被調整以配合一特定封裝體之該I/O、冷卻、及其他設計配置。
該等第三框格220、第四框格222及第五框格224包含一個或更多的額外的晶粒及被動裝置，且也都是以一記憶體或其他功能IC晶粒所覆蓋。該特定的晶粒之選擇可取決於該封裝體選擇的預定用途。對於電腦系統封裝體，該等額外的晶粒可包括下列類型的晶粒：額外的CPU、圖形處理器、共處理器、網路介面、無線電通訊基頻或RF模組、音頻模組、影像處理模組、記憶體模組、任何其他類型之晶粒。
所有這些IC晶粒可同時封裝，以增加組裝過程的穩定性。該等晶粒可全部直接置於該等穿孔之上，而無需在基板表面上形成阻焊。藉此可避免更多的校準及可能在一阻焊塗覆過程中產生之FM/污斑之課題。
該完整的封裝體可用各種不同的方式來組裝。在一些實施例中，在形成該等穿孔及該等框格之後，所有的該等穿孔112、126會以電鍍的純錫或錫/銅合金充填。在晶粒附著之前，該封裝體會在低溫下進行簡易的回焊爐製程，以使該等穿孔內之該已鍍上的金屬垂直向上與向下膨脹而形成純錫或錫/銅合金凸塊。在該等焊接凸塊已藉由膨脹而 形成之後，會將該底層IC晶粒及被動裝置放置於該框格內之該等穿孔112的頂部且充填填充材。接著，頂層IC晶粒放置於該等側壁穿孔126的頂部。最後，該整個封裝體通過一第二簡易回焊爐製程以完成組裝。具有穿孔及框格的該陶瓷框架可讓在兩層中的所有的IC晶粒及被動裝置同時且以通過一次回焊爐的方式被組裝好。相較於許多其他晶粒堆疊封裝，此作法較為快速，並且讓晶粒承受較少的熱應力。
對於該框架及該底蓋，可使用各種不同的陶瓷材料。其包括氧化鋁、氮化鋁、鋯增韌氧化鋁、及其他材料。這些陶瓷具有相較於一習用的有機基板或例如FR-4之樹脂更加接近於矽晶粒的一CTE(熱膨脹係數)。其結果為，可以將當結合異質材料時所導致的翹曲間題大幅降低。這些陶瓷也具有遠高於有機樹脂及其他的一般基板的熱傳導性。此可允許將該陶瓷使用於高密度2.5D或3D之IC封裝體的散熱上。來自該等晶粒的熱能可透過該等焊球或墊並經由該等通孔且接著進入該陶瓷而被抽離。該變熱的陶瓷能透過其外表面散熱。藉由將均熱片、散熱鰭片、熱輻射器、或冷卻器裝設至該封裝體的一個或多個外表面，可增加散熱。該等側壁提供可藉由額外的熱輻射器而加大的顯著的熱輻射表面。
圖3-16顯示可被用於建構如上所述之一陶瓷框架、再分配層及底蓋的一序列的操作。在圖3中，第一及第二陶瓷板胚302、304是利用一可剝離膠而結合在一起。此可允許在頂部與底部上對二個封裝體同步地執行某些製程。 然而，相同的方法只能以一次只作用在一側的形式被使用。圖3是僅一部分的陶瓷板坯的剖面圖，其在各側上只有形成一個框格。一大得多的陶瓷板坯可被使用以同時形成複數個框格。因此，二個板坯302、304在該頁面上皆是延伸至該左、右兩邊，並且如所示地也在該剖面視圖之前後延伸。
該陶瓷板坯由頂部至底部可為100至400μm厚，如此，該二個板坯會如所示地總共為200至700μm高。可採用特定的尺寸以配合許多不同大小的晶粒及最終的封裝體形式。該可剝離膠使兩個陶瓷芯材附著在一起，並且可為一用於例如PCB/FPC(印刷電路板/可撓性印刷電路板)製造之類型。
在圖4中，該二面板皆覆蓋上一銅層308。此可用許多不同的方式來完成。在一些實施例中，鉈/銅係濺鍍於該表面以於表面形成種子層，然後將銅電鍍於該被濺鍍的表面上。市面上的氧化鋁陶瓷芯材具有類似於一般銅跡線(Cu trace)之大約0.5μm的Ra(平均表面粗糙度)。因此，在ABF(味之素積層膜(Ajinomoto Build-up Film))層及該陶瓷芯材之間的結合是極佳的。
在圖5中，該銅層308進行圖案化以形成在該等板坯的頂部及底部上之一圖案化的銅層310。光刻技術、雷射加工或其他技術可利用來對該銅進行圖案化。在圖6中，一ABF層312被施加於該圖案化的銅上。該ABF將各個圖案化的銅區域與其他的銅區域隔離。在圖7中，該ABF是利用雷射鑽孔或任何其他所欲之技術來進行圖案化。此可在各個 銅焊盤上的該ABF中創造出通孔314。在圖8中，一第二層的銅形成是在該ABF及該等通孔上。該銅層包括以該等所鑽設的通孔為基礎之充填的通孔316以及一圖案化的水平銅層318。當將該圖案顯現為在各個通孔上的一焊盤時，此層可包括將不同的通孔相互連接以建立該層之一再分配層的圖案化的跡線。
在圖9中，複數個銅路由及ABF隔離層已被形成而在該頂部及底部板坯302、304上皆完成一再分配層320。該等再分配層的該等通孔316可用一墊322蓋住，以對預定形成於該再分配層之上的結構提供連接。
在圖10中，一第二陶瓷板坯324、326是被施加在該等頂部及底部的再分配層之上。這些第二陶瓷板坯可與該等最初的兩個板坯302、304相同，或是可將其特別塑形與建構作為該封裝體的該頂部陶瓷框架使用。
在圖11中，該可剝離膠被鬆脫以分離該頂部及底部的封裝體。藉此可允許使用將成為該封裝體的底蓋的該內側陶瓷板坯302、304。在圖12中，是將該底蓋拋光以減少其厚度，例如從300μm減少至100μm。該厚度的減少會縮小該封裝體的尺寸並縮減從該封裝體到要將該封裝體安裝至其上的主機板、插槽或其他基板之連接長度。該底蓋的最後厚度可被調整成適合於與不同的實施方式配合。
在圖13中，該等穿孔330、332是形成在該組合件之該陶瓷框架324及該底蓋302兩者上。深盲通孔的雷射鑽孔可執行在厚度超過300μm的陶瓷芯材上，以產生具有 30-50μm半徑的孔。該等穿孔可從一側進行鑽孔，並且控制成不會使該再分配層320損壞。
在圖14中，該等穿孔係被鍍敷、充填及覆蓋，以使其可作為該等晶粒與其他晶粒及外部構件之間的導電連接器來使用。該等孔予可用各種不同的方式充填或鍍敷。在一實施例中，無電式鍍鎳處理被施加，随後再進行無電式鍍銅。在此之後接著進行純錫或錫/銅合金深盲通孔電鍍。該等鍍敷的參數可被以下事項控制：槽浴循環、空氣攪拌作用、金屬濃度等。鍚因為其本身的高原子重量而很適合用於充填上。然而，也可配合其他製程參數使用其他材料。錫也可提供對於一焊接點的一良好表面。藉由使用少量的無電鍍銅，將在回流後使對該充填孔之該連接主要為錫。
在圖15中，該等框格338被形成於該陶瓷框架中。如上所述，陶瓷板坯可形成具有複數個框格之一封裝體或複數個各自具有複數個框格的封裝體之基礎。結果可形成一個或多個框格。可藉由蝕刻、機械加工或使用其他技術來形成該等框格。在一些實施例中，是藉由雷射開槽技術來形成該等框格。可將一雷射鑽孔機使用於製出具有不同尺寸及深度的不同框格，以配合使不同IC晶粒一起在一個框架或不同框架中的安裝。在製造各個框格而進行雷射開槽期間，可將形成在該等穿孔336中的該等錫柱或錫/銅柱部分鑽掉。
使用所述之製程複數個面板可被0同時處理以製造出複數個各自具有複數個框格的封裝體。該所得到的封 裝體可將超過10個的IC晶粒一起收容在一個陶瓷框架中，而使一個陶瓷框架在功能及價值方面幾乎等同於5至10個現有的封裝體。該陶瓷可將電絕緣性和高熱傳導性一起提供給所有的該等穿孔、墊、被動裝置及其他構件，以將熱自該等晶粒抽離。
圖15顯示準備用於晶粒附著之完整但中空的封裝體。可以用各種不同的方式將該等晶粒安裝至該封裝體。習用的材料及製程可使用以利用回流焊接來安裝該等晶粒。
圖16-18是利用圖15的該陶瓷框架及再分配層與底蓋組裝一封裝體之剖面側視圖。在圖16中，圖15之該中空的封裝體是在該陶瓷框架324之頂部及該底蓋302底部之該等穿孔的末端上接收焊球340、342可藉由將該結構在低溫下通過一簡單的回焊爐製程以讓該鍍敷之金屬膨脹形成該等凸塊340、342，而如上所述地形成該等焊接凸塊或焊球。此外，也可以使用任意的各種其他技術來施作該等凸塊或球。
在圖17中，填充材350係施加於該框格338的底板，並且將一個或多個晶粒346、348放置於適當的焊球之上。該等晶粒被對準使得在該等晶粒上的墊與該等焊球對準，然後將該封裝體放置於一回焊爐中以使該等晶粒附著到該框格的底板。
在圖18中，是利用焊球340及一填充材354同樣地使該頂部晶粒352附著到該封裝體的該等側壁的該等頂部。 再次將該封裝體放置於該回焊爐中以將該頂部晶粒焊接至該封裝體。該封裝體接著即藉著使所有的晶粒均附著上而完成，並且準備就緒而可安裝到一主機板、一插槽或任何其他所欲之平台。
圖19是根據本發明的一個實施方式的一計算裝置100的方塊圖。該計算裝置100容納一系統主機板2。該主機板2可包括許多構件，且包括但不限於一處理器4及一晶片組。該處理器4在實體上與電氣上耦合至該主機板2。
根據其應用，計算裝置100可包括其他實體未必耦合至該主機板2而電氣上耦合至該主機板2之構件。這些其他構件包括但不限於，通訊晶片6、揮發性記憶體(如DRAM)8、非揮發性記憶體(如ROM)9、快閃記憶體(圖未示)、一圖形處理器12、一數位訊號處理器(圖未示)、一加密處理器(圖未示)、一晶片組14、一天線16、一顯示器18(例如觸控螢幕顯示器)、一觸控螢幕控制器20、一電池22、一音訊解碼器(圖未示)、一視訊解碼器(圖未示)、一功率放大器24、一全球定位系統(GPS)裝置26、一羅盤28、一加速器(圖未示)、一迴轉儀(圖未示)、一喇叭30、一相機32、及一大容量儲存裝置(例如硬式磁碟機)10、光碟(CD)(圖未示)、數位通用磁碟(DVD)(圖未示)等等。可將該等構件連接至該系統主機板2、裝設至該系統主機板、或與任何的其他構件結合。
該通訊封裝體6能夠進行無線及/或有線通訊，以進行往來該計算裝置100之資料的傳輸。該用語“無線”及 其衍生詞可被用於描述電路、裝置、系統、方法、技術、通訊頻道等，其可藉由透過非實體媒體(non-solid medium)之經調變的電磁輻射之使用來進行資料通訊。該用語並未隱含該相關裝置不會包括任何導線之意，雖然在一些實施例中其可能會不包括。該通訊封裝體6可執行任何無線或有線的標準或協定，包括但不限於其Wi-Fi(IEEE 802.11系列)、WiMAX(IEEE 802.16系列)、IEEE 802.20、長期演進(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、藍芽、乙太網路衍生技術、以及任何其他被指定為3G、4G、5G及其之後的無線及有線的協定。該計算裝置100可包括複數個通訊封裝體6。例如，一第一通訊封裝體6可用於較短距的無線通訊，例如Wi-Fi及藍芽，且一第二通訊封裝體6可用於較長距的無線通訊，例如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO、及其他無線通訊。
可如在此所述地將任何一個或多個晶片或處理器封裝，或利用如所述之一共同的陶瓷框架將若干個該等晶片結合為一單一的封裝體。
在不同的實施方式中，該計算裝置100可為一伺服器、一工作站、一膝上型電腦、一隨身型易網機(netbook)、一筆記型電腦、一超筆電(ultrabook)、一智慧型手機、一數位平板、一個人數位助理(PDA)、一超級移動PC、一行動電話、一印表機、一掃描器、一監視器、一機上盒、一娛樂控制單元、一數位相機、一可攜式音樂播放器、或一數 位視訊記錄器。在進一步的實施方式中，該計算裝置100可為任何其他的電子裝置，例如可用以處理資料之一筆、一錢包、一手錶、或一用具。
可將實施例作為利用一主機板、一特定應用積體電路(ASIC)、及/或一現場可程式閘陣列(FPGA)而互連的一個或多個記憶體晶片、控制器、CPUs(中央處理器)、微晶片或積體電路之一部分來實行。
對"一實施例"、"一個實施例"、"舉例實施例"、"各種實施例"等之引用表示如此描述之本發明之該(等)實施例可包括特定的形態、結構、或特徵，但不是每個實施例都必須包括該特定的形態、結構、或特徵。再者，一些實施例可包括對其他實施例所說明之該等形態中的一些、全部、或不包括。
在以下之說明及申請專利範圍中，可使用該用語”耦合的”與其衍生詞。”耦合的”是用來表示兩個或更多的元件彼此相配合或交互作用，但它們未必具有中介之實體的、或電氣的構件在它們之間。
除非另有說明，如在申請專利範圍中所使用地，使用該順序形容詞“第一”、“第二”、“第三”等用以描述共通的元件，僅表示所引用的是相似元件之不同實例，並非是想要表示如此描述之該等元件必定是所給定的順序，亦非是在時間上、空間上、或任何其他形式上之排序。
該等圖式及前面的說明列舉出實施例的例子。本領域之技術人員理應察知的是，可將一個或多個所述元件 結合成一個單一的功能元件。或是，可將某些元件分成多個功能元件。可將其中一個實施例之元件加到另一個實施例。例如，可改變在此所述之製程的順序，而不限於在此所述之方式。再者，任何流程圖之動作並不需要依所示之順序執行；而且也不是所有的動作都必須被執行。還有，可將不是依存於其他動作來進行的那些動作，與其他動作同時執行。該等實施例之範圍不應因這些特定的舉例而受限。不論說明書中是否有明確地說明，像是在結構、尺寸及材料之使用上的差異之類的各種變化，都是可能的。該等實施例之範圍至少與以下的申請專利範圍所述者相同。
下述舉例涉及進一步之實施例。不同實施例之各種形態可與將某些形態包含在內而將其他形態排除之方式作各種不同的結合，以因應各種不同的應用。有些實施例是有關於一積體電路封裝體，其包括：一陶瓷框架，具有一頂側及一底側，該頂側具有一框格，該框格具有一底板及複數個在該底板中的導電穿孔；一積體電路晶粒，其附著至位於該等導電穿孔之上的該底板；及一再分配層，位於該底側並連接至該等導電穿孔。
在進一步的實施例中，該框格是以側壁而定義，該陶瓷框架具有在該等側壁中從頂側延伸到底側的複數個第二導電穿孔，且該封裝體進一步包含附著到在該頂側上之該等側壁並且在該框格上方延伸以覆蓋該框格的一第二積體電路晶粒，該第二晶粒連接至複數個第二導電穿孔。
在進一步的實施例中，一部分的該等第一導電穿 孔是透過該再分配層耦合至一部分的該等第二導電穿孔，以將該第一晶粒連接至該第二晶粒。
進一步的實施例包含附著到該再分配層的一陶瓷底蓋，藉此使該再分配層位於該陶瓷框架底側及該底蓋之間。
在進一步的實施例中，該底蓋具有複數個第三導電穿孔以將該再分配層連接至外部構件。
在進一步的實施例中，該等穿孔以鍚充填。
在進一步的實施例中，該等穿孔被覆有錫/銅合金，且其中該晶粒是藉由回焊來附著。
進一步的實施例包含附著至在該等導電穿孔一部分之上的該底板的一第二積體電路晶粒，且其中該再分配層是透過該等穿孔而連接該等第一及第二晶粒。
在進一步的實施例中，該陶瓷框架是由氧化鋁形成。
進一步的實施例包含附著至該底板並與該晶粒耦合的被動裝置。
某些實施例是有關於一方法，該方法包括下列步驟：在一陶瓷板坯上形成一再分配層，該再分配層具有路由層及在該等路由層之間的通孔；將一陶瓷底蓋附著在該再分配層之上；薄化該底蓋；鑽設穿過該板坯及該底蓋之穿孔，而使該等穿孔可連接到該再分配層的通孔；將該等穿孔以一導電材料鍍敷；在該板坯中形成一框格，該框格具有側壁及一在該等側壁之間的底板；及將一晶粒附著至 該底板，而使該晶粒可電氣耦合至已鍍敷之該等穿孔。
在進一步的實施例中，形成一再分配層之步驟包含將銅沈積層及在該等銅沈積層之間的味之素積層膜圖案化。
在進一步的實施例中，在該板坯中形成一框格之步驟包含對該板坯進行雷射開槽。
在進一步的實施例中，將鍍敷該等穿孔之步驟包含以鍚電鍍該等穿孔。
在進一步的實施例中，附著一晶粒之步驟包含：對已鍍敷之該等穿孔施加一低溫回焊，以在該框格中的該等穿孔之上形成焊球；將填充材施加至底板上；將一晶粒放置於該框格中的該等焊球之上；及利用一回焊爐來使該晶粒附著。
在進一步的實施例中，鑽設穿孔之步驟包括在該等側壁中鑽設穿孔，該方法進一步包含附著一晶粒到該框格之上以覆蓋該框格。
進一步的實施例包括使被動裝置附著至該底板且將該等被動裝置連接至該晶粒。
某些實施例是有關於一計算裝置，其包括：一系統主機板；連接至該系統主機板的一通訊封裝體；及連接至該系統主機板的一積體電路封裝體，該積體電路封裝體具有：一陶瓷框架，具有一頂側及一底側，該頂側具有一框格，該框格具有一底板及在該底板的複數個導電穿孔；一積體電路晶粒，附著至位於該等導電穿孔之上的該底板； 及一再分配層，位於該底側上並連接至該等導電穿孔。
在進一步的實施例中，該積體電路封裝體具有帶有各自的底板及導電穿孔之複數個額外的框格，各個額外的框格具有一額外的積體電路晶粒，且其中該再配層會在該等額外的框格之間延伸並相互連接該等額外的積體電路晶粒。
在進一步的實施例中，該積體電路封裝體的該等額外的框格具有不同的大小且各進一步被額外的積體電路晶粒所覆蓋。
101‧‧‧封裝體
102‧‧‧陶瓷框架
104‧‧‧框格
106、108、110‧‧‧晶粒
112、126、132‧‧‧穿孔
114‧‧‧填充材
115‧‧‧底板
116‧‧‧再分配層
118‧‧‧路由層
120‧‧‧通孔
124‧‧‧側壁
130‧‧‧底蓋
134‧‧‧墊
138‧‧‧主機板

Claims (20)

  1. 一種積體電路封裝體，包含：一陶瓷框架，具有一頂側及一底側，該頂側具有一框格，該框格具有一底板及在該底板的複數個導電穿孔；一積體電路晶粒，其附著至位於該等導電穿孔之上的該底板；及一再分配層，位於該底側並連接至該等導電穿孔。
  2. 如請求項1之封裝體，其中，該框格是由側壁而定義，該陶瓷框架具有在該等側壁中從該頂側延伸到該底側的複數個第二導電穿孔，且該封裝體進一步包含附著到在該頂側上之該等側壁並且在該框格上方延伸以覆蓋該框格的一第二積體電路晶粒，該第二晶粒連接至複數個第二導電穿孔。
  3. 如請求項2之封裝體，其中，一部分的該等第一導電穿孔是透過該再分配層耦合至一部分的該等第二導電穿孔，以將第一晶粒連接至第二晶粒。
  4. 如請求項1之封裝體，其還包含附著到該再分配層的一陶瓷底蓋，藉此使該再分配層位於該陶瓷框架底側及該底蓋之間。
  5. 如請求項1之封裝體，其中，該底蓋具有複數個第三導電穿孔以將該再分配層連接至外部構件。
  6. 如請求項1之封裝體，其中，該等穿孔以鍚充填。
  7. 如請求項1之封裝體，其中，該等穿孔被覆有錫/銅合金，且其中該晶粒是藉由回焊來附著。
  8. 如請求項1之封裝體，其還包含附著至在該等導電穿孔一部分之上的該底板的一第二積體電路晶粒，且其中該再分配層是透過該等穿孔而連接該等第一及第二晶粒。
  9. 如請求項1之封裝體，其中該陶瓷框架是由氧化鋁形成。
  10. 如請求項1之封裝體，其還包含附著至該底板並與該晶粒耦合的被動裝置。
  11. 一種方法，包含下列步驟：在一陶瓷板坯上形成一再分配層，該再分配層具有路由層及在該等路由層之間的通孔；將一陶瓷底蓋附著在該再分配層之上；薄化該底蓋；鑽設穿過該板坯及該底蓋之穿孔，而使該等穿孔可連接到該再分配層的通孔；將該等穿孔以一導電材料鍍敷；在該板坯中形成一框格，該框格具有側壁及在該等側壁之間的一底板；及將一晶粒附著至該底板，而使該晶粒可電氣耦合至已鍍敷之該等穿孔。
  12. 如請求項11之方法，其中形成一再分配層之步驟包含將銅沈積層及在該等銅沈積層之間的味之素積層膜圖案 化。
  13. 如請求項11之方法，其中在該板坯中形成一框格之步驟包含對該板坯進行雷射開槽。
  14. 如請求項11之方法，其中鍍敷該等穿孔之步驟包含以鍚電鍍該等穿孔。
  15. 如請求項14之方法，其中附著一晶粒之步驟包含：對已鍍敷之該等穿孔施加一低溫回焊，以在該框格中的該等穿孔之上形成焊球；將填充材施加至該底板；將一晶粒放置於該框格中的該等焊球之上；及利用一回焊爐來附著該晶粒。
  16. 如請求項11之方法，其中鑽設穿孔之步驟包含在該等側壁中鑽設穿孔，且該方法還包含使一晶粒附著到該框格之上以覆蓋該框格。
  17. 如請求項11之方法，其還包含使被動裝置附著至該底板且將該等被動裝置連接至該晶粒。
  18. 一種計算裝置，包含：一系統主機板；一通訊封裝體，其連接至該系統主機板板；及一積體電路封裝體，連接至該系統主機板，該積體電路封裝體具有一陶瓷框架、一積體電路晶粒及一再分配層，該陶瓷框架具有一頂側及一底側，該頂側具有一框格，該框格具有一底板及複數個在該底板中的導電穿孔，該積體電路晶粒是被附著至位於該等導電穿孔之上 的該底板，且該再分配層位於該底側並連接至該等導電穿孔。
  19. 如請求項18之計算裝置，其中，該積體電路封裝體具有帶有各自的底板及導電穿孔之複數個額外的框格，各個額外的框格具有一額外的積體電路晶粒，且其中該再分配層會在該等額外的框格之間延伸並相互連接該等額外的積體電路晶粒。
  20. 如請求項19之計算裝置，其中，該積體電路封裝體的該等額外的框格具有不同的大小且各進一步被額外的一積體電路晶粒所覆蓋。
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Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2947692B1 (en) * 2013-12-20 2020-09-23 Analog Devices, Inc. Integrated device die and package with stress reduction features
US10287161B2 (en) 2015-07-23 2019-05-14 Analog Devices, Inc. Stress isolation features for stacked dies
US10453786B2 (en) * 2016-01-19 2019-10-22 General Electric Company Power electronics package and method of manufacturing thereof
TWI655892B (zh) * 2016-05-31 2019-04-01 日商Ｊｘ金屬股份有限公司 附散熱用金屬材之結構物、印刷電路板及電子機器、散熱用金屬材
TWI659828B (zh) * 2016-07-27 2019-05-21 日商Ｊｘ金屬股份有限公司 附散熱用金屬材之結構物、印刷電路板、電子機器及散熱用金屬材
US10861803B1 (en) * 2017-03-17 2020-12-08 Scientific Components Corporation Low cost millimeter wave integrated LTCC package and method of manufacturing
US10630296B2 (en) * 2017-09-12 2020-04-21 iCometrue Company Ltd. Logic drive with brain-like elasticity and integrality based on standard commodity FPGA IC chips using non-volatile memory cells
FR3079068B1 (fr) * 2018-03-13 2023-05-26 St Microelectronics Grenoble 2 Dispositifs electroniques et procedes de fabrication
US11127716B2 (en) 2018-04-12 2021-09-21 Analog Devices International Unlimited Company Mounting structures for integrated device packages
US10734358B2 (en) * 2018-06-14 2020-08-04 Intel Corporation Multi-packaging for single-socketing
US11387187B2 (en) * 2018-06-28 2022-07-12 Intel Corporation Embedded very high density (VHD) layer
US10522450B1 (en) * 2018-10-15 2019-12-31 Intel Corporation Pillar based socket
CN111446553B (zh) * 2019-01-17 2024-04-02 富泰华工业（深圳）有限公司 天线结构及具有所述天线结构的无线通信装置
US11342256B2 (en) 2019-01-24 2022-05-24 Applied Materials, Inc. Method of fine redistribution interconnect formation for advanced packaging applications
IT201900006740A1 (it) * 2019-05-10 2020-11-10 Applied Materials Inc Procedimenti di strutturazione di substrati
IT201900006736A1 (it) 2019-05-10 2020-11-10 Applied Materials Inc Procedimenti di fabbricazione di package
US11931855B2 (en) 2019-06-17 2024-03-19 Applied Materials, Inc. Planarization methods for packaging substrates
US11862546B2 (en) 2019-11-27 2024-01-02 Applied Materials, Inc. Package core assembly and fabrication methods
US11257790B2 (en) 2020-03-10 2022-02-22 Applied Materials, Inc. High connectivity device stacking
US11454884B2 (en) 2020-04-15 2022-09-27 Applied Materials, Inc. Fluoropolymer stamp fabrication method
US11400545B2 (en) 2020-05-11 2022-08-02 Applied Materials, Inc. Laser ablation for package fabrication
US11664340B2 (en) 2020-07-13 2023-05-30 Analog Devices, Inc. Negative fillet for mounting an integrated device die to a carrier
US11232951B1 (en) 2020-07-14 2022-01-25 Applied Materials, Inc. Method and apparatus for laser drilling blind vias
US11676832B2 (en) 2020-07-24 2023-06-13 Applied Materials, Inc. Laser ablation system for package fabrication
US11521937B2 (en) 2020-11-16 2022-12-06 Applied Materials, Inc. Package structures with built-in EMI shielding
US11404318B2 (en) 2020-11-20 2022-08-02 Applied Materials, Inc. Methods of forming through-silicon vias in substrates for advanced packaging
US11705365B2 (en) 2021-05-18 2023-07-18 Applied Materials, Inc. Methods of micro-via formation for advanced packaging
CN115332225A (zh) * 2022-10-14 2022-11-11 北京华封集芯电子有限公司 无机中介层结构及无机中介层结构的制作方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6906407B2 (en) * 2002-07-09 2005-06-14 Lucent Technologies Inc. Field programmable gate array assembly
JP4520355B2 (ja) * 2005-04-19 2010-08-04 パナソニック株式会社 半導体モジュール
US8193034B2 (en) * 2006-11-10 2012-06-05 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure using stud bumps
US20080116564A1 (en) * 2006-11-21 2008-05-22 Advanced Chip Engineering Technology Inc. Wafer level package with die receiving cavity and method of the same
DE102006062473A1 (de) * 2006-12-28 2008-07-03 Qimonda Ag Halbleiterbauelement mit auf einem Substrat montiertem Chip
US8592992B2 (en) 2011-12-14 2013-11-26 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure with conductive micro via array for 3-D Fo-WLCSP
US8362607B2 (en) * 2009-06-03 2013-01-29 Honeywell International Inc. Integrated circuit package including a thermally and electrically conductive package lid
US8643164B2 (en) * 2009-06-11 2014-02-04 Broadcom Corporation Package-on-package technology for fan-out wafer-level packaging
US8937381B1 (en) * 2009-12-03 2015-01-20 Amkor Technology, Inc. Thin stackable package and method
US8466544B2 (en) * 2011-02-25 2013-06-18 Stats Chippac, Ltd. Semiconductor device and method of forming interposer and opposing build-up interconnect structure with connecting conductive TMV for electrical interconnect of Fo-WLCSP
US8848380B2 (en) * 2011-06-30 2014-09-30 Intel Corporation Bumpless build-up layer package warpage reduction
TWI473218B (zh) 2012-07-26 2015-02-11 Unimicron Technology Corp 穿孔中介板及其製法與封裝基板及其製法
US9368438B2 (en) 2012-12-28 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package (PoP) bonding structures
JP6230794B2 (ja) * 2013-01-31 2017-11-15 新光電気工業株式会社 電子部品内蔵基板及びその製造方法
KR102127772B1 (ko) * 2013-05-16 2020-06-29 삼성전자주식회사 방열 판을 갖는 반도체 패키지 및 그 형성 방법
KR102076044B1 (ko) * 2013-05-16 2020-02-11 삼성전자주식회사 반도체 패키지 장치
US8980691B2 (en) * 2013-06-28 2015-03-17 Stats Chippac, Ltd. Semiconductor device and method of forming low profile 3D fan-out package
KR102198858B1 (ko) * 2014-07-24 2021-01-05 삼성전자 주식회사 인터포저 기판을 갖는 반도체 패키지 적층 구조체

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