TW201730992A - 具有與嵌入於微電子基板中之微電子橋連接的多個微電子裝置之微電子結構 - Google Patents

具有與嵌入於微電子基板中之微電子橋連接的多個微電子裝置之微電子結構 Download PDF

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TW201730992A
TW201730992A TW105134420A TW105134420A TW201730992A TW 201730992 A TW201730992 A TW 201730992A TW 105134420 A TW105134420 A TW 105134420A TW 105134420 A TW105134420 A TW 105134420A TW 201730992 A TW201730992 A TW 201730992A
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Prior art keywords
microelectronic
microelectronic device
substrate
bridge
density interconnect
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TW105134420A
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English (en)
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TWI726926B (zh
Inventor
艾利克 李
提摩西 高斯林
富田佳宏
蕭娜 里夫
安蘭 艾登
馬克 薩塔斯
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英特爾公司
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Abstract

一種微電子結構包括：微電子基板，該微電子基板具有第一表面及自該微電子基板第一表面延伸至該基板中之空腔；第一微電子裝置及第二微電子裝置，該等裝置附接至該微電子基板第一表面；以及微電子橋，該微電子橋設置於該微電子基板空腔內且附接至該第一微電子裝置及該第二微電子裝置。在一個實施例中，該微電子裝置可包括：重構晶圓，該重構晶圓由該第一微電子裝置及該第二微電子裝置形成。在另一實施例中，助熔劑材料可在該第一微電子裝置與該微電子橋之間及在該第二微電子裝置與該微電子橋之間延伸。

Description

具有與嵌入於微電子基板中之微電子橋連接的多個微電子裝置之微電子結構
本說明書之實施例總體上係關於微電子封裝製造之領域，並且更具體而言，係關於包括嵌入於基板中以用於微電子裝置之間的電信號連接之橋的微電子結構，且係關於製造該微電子結構之方法。
微電子工業不斷力求生產用於在各種電子產品中使用之較快及較小的微電子封裝。作為此努力之一部分，已開發出含有多個裝置之微電子封裝，如微電子晶粒。此等多個微電子裝置封裝在此項技術中稱為多裝置封裝或多晶片封裝(MCP)，且提供以低成本增加架構可撓性之可能性，但必須如此以使得提供適當的微電子裝置至微電子裝置互連密度。如熟習此項技術者將理解，互連密度是重要因素，因為數量不足的微電子裝置連接將限制用於受影響微電子裝置介面之頻寬容量，且因此將降低微電子 裝置之間的通訊效率及容量。
依據本發明之一實施例，係特地提出一種形成一微電子結構之方法，該方法包含：形成一第一微電子裝置及一第二微電子裝置，其中該第一微電子裝置及該第二微電子裝置中之每一者在其一主動表面上包括多個高密度互連結構及多個較低密度互連結構；將一微電子橋附接至該第一微電子裝置之該等多個高密度互連結構及該第二微電子裝置之該等多個高密度互連結構；形成一微電子基板，該微電子基板具有界定於其中之一空腔，該空腔自該微電子基板之一第一表面延伸，其中該空腔包括至少一個側壁及一底表面；以及將該第一微電子裝置之該等多個較低密度互連結構及該第二微電子裝置之該等多個較低密度互連結構電氣附接至該微電子基板之該第一表面，其中該微電子橋延伸至該微電子基板空腔中。
1101‧‧‧第一微電子裝置/微電子裝置
1102‧‧‧第二微電子裝置/微電子裝置
112‧‧‧主動表面
114‧‧‧後表面
116、146‧‧‧側面
118‧‧‧包封劑材料
120‧‧‧重構晶圓
122‧‧‧高密度互連結構
124‧‧‧較低密度互連結構
132、202‧‧‧載體
134‧‧‧黏附層
140‧‧‧微電子橋
142‧‧‧第一表面
144‧‧‧第二表面
148、168‧‧‧傳導路線
152‧‧‧互連結構/微電子橋互連結構
154、176‧‧‧焊接材料
160‧‧‧微電子基板
162‧‧‧第一表面/微電子基板第一表面
164‧‧‧焊墊/基板焊墊/微電子基板焊墊
170‧‧‧空腔/微電子基板空腔
172‧‧‧底表面
174‧‧‧側壁
178‧‧‧底部填充材料
180‧‧‧微電子結構
182‧‧‧黏附材料
204‧‧‧助熔劑材料
212‧‧‧信號路由層
214‧‧‧主動組件
216‧‧‧介電材料
222‧‧‧焊接球
224‧‧‧引線黏結劑
300‧‧‧製程
302、304、306、308‧‧‧方框
400‧‧‧計算裝置
402‧‧‧板
404‧‧‧處理器
406A、406B‧‧‧通訊晶片
408‧‧‧依電性記憶體
410‧‧‧非依電性記憶體
412‧‧‧快閃記憶體
414‧‧‧圖形處理器或CPU
416‧‧‧晶片組
P1、P2‧‧‧間距/間隔
T‧‧‧厚度
在本說明書之總結部分中特別指出且清楚主張了本揭示案之標的。本揭示案之前述及其他特徵將自以下結合隨附圖式進行之描述及所附申請專利範圍而變得更充分明顯。應理解，隨附圖式僅描繪根據本揭示案之若干實施例，且因此不被認為限制其範疇。將經由隨附圖式之使用，以附加特性及細節來描述本揭示案，以使得本揭示案之優點可更容易地確定，該等圖式中：圖1至圖10例示根據本說明書之實施例的用於製造包 括與橋電氣連接之至少兩個微電子裝置的微電子結構之方法的橫截面視圖，其中該橋駐留於微電子基板中之空腔內，該等微電子裝置電氣附接至該微電子基板。
圖11至圖16例示根據本說明書之實施例的用於製造包括與橋電氣連接之至少兩個微電子裝置的微電子結構之另一方法的橫截面視圖，其中該橋駐留於微電子基板中之空腔內，該等微電子裝置電氣附接至該微電子基板。
圖17為根據本說明書之實施例的製造微電子結構之製程的流程圖。
圖18例示根據本說明書之一個實行方案的計算裝置。
在以下詳細描述中，對以例示方式展示可實踐所主張標的之特定實施例的隨附圖式進行參考。足夠詳細地描述此等實施例，以使熟習此項技術者能夠實踐標的。應理解，各種實施例雖然不同，但不一定互斥。例如，可在不脫離所主張標的之精神及範疇的情況下，在其他實施例內實行本文中結合一個實施例所描述之特定特徵、結構或特性。本說明書內對「一個實施例」或「一實施例」之提及意味結合該實施例描述之特定特徵、結構或特性係納入涵蓋於本說明書內之至少一個實行方案中。因此，片語「一個實施例」或「在一實施例中」之使用不一定指代同一實施例。另外，應理解，可在不脫離所主張標的之精神及範疇的情況下，修改每一所揭示之實施例內的個別元件之位置或佈置。因此，以下詳細描述不應視為限制意義， 且標的之範疇以及授權所附申請專利範圍之等效物的全範圍僅由所附申請專利範圍界定、適當地解釋。在圖式中，貫穿若干視圖，相似數字指代相同或類似的元件或功能，並且其中所描繪之元件不一定彼此成比例，而可將個別元件放大或縮小，以便在本說明書之情境中更容易地理解該等元件。
如本文中所使用之「在...上方」、「至」、「在...之間」及「在...上」等詞可指代一個層相對於其他層之相對位置。「在另一層上方」或「在另一層上」或黏結「至」另一層的一個層可與另一個層直接接觸或可具有一或多個介入層。「在層之間」的一個層可與該等層直接接觸或可具有一或多個介入層。
本說明書之實施例包括製造包含形成第一微電子裝置及第二微電子裝置之微電子結構，其中第一微電子裝置及第二微電子裝置中之每一者在其主動表面上包括多個高密度互連結構及多個較低密度互連結構，將微電子橋附接至第一微電子裝置之多個高密度互連結構及第二微電子裝置之多個高密度互連結構，形成具有空腔之微電子基板，該空腔自該微電子基板之第一表面延伸至該微電子基板中，以及將第一微電子裝置之多個較低密度互連結構及第二微電子裝置之多個較低密度互連結構電氣附接至微電子基板之第一表面，其中微電子橋延伸至微電子基板空腔中。
本說明書之實施例可實現微電子封裝內之 結構的密度縮放，該密度縮放可藉由使用嵌入於微電子基板中的微電子橋來表示對現有技術時代之重大改良。此等微電子橋支援自第一微電子裝置至第二微電子裝置之密集微電子裝置至微電子裝置互連。因此，所得微電子封裝可顯著小於僅與微電子基板內之傳導路線互連的微電子封裝。
圖1至圖11例示根據本說明書之一個實施例的製造微電子結構之方法。如圖1中所示，可形成展示為第一微電子裝置1101及第二微電子裝置1102之多個微電子裝置，其中每一微電子裝置1101、1102可包括主動表面112、相反的後表面114、以及至少一個側面116，該側面在微電子裝置主動表面112與微電子裝置後表面114之間延伸。每一微電子裝置1101、1102可在微電子裝置主動表面112上包括諸如凸塊或支柱之多個高密度互連結構122、以及諸如凸塊或支柱之多個較低密度互連結構124。應理解，高密度互連結構122及較低密度互連結構124可與第一微電子裝置1101及第二微電子裝置1102內之積體電路系統(未展示)電氣通訊。第一微電子裝置1101及第二微電子裝置1102可為諸如微電子晶粒之任何適當微電子裝置，包括但不限於：微處理器、晶片組、圖形裝置、無線裝置、記憶體裝置、特定應用積體電路裝置等。
如為本說明書定義，「較低密度互連結構」中之「較低密度」一詞相對於「高密度互連結構」中之「高密度」一詞之處在於較低密度互連結構124具有比高密度 互連結構122之間的間距/間隔P2更大的較低密度互連結構124之間的間距/間隔P1，且反之亦然。
如圖2中所示，第一微電子裝置1101及第二微電子裝置1102可於載體132上被對準。在一個實施例中，第一微電子裝置1101及第二微電子裝置1102可利用其面向載體132之主動表面112對準，且利用黏附層134緊固於適當位置中，該黏附層設置在載體132與第一微電子裝置1101及第二微電子裝置1102之主動表面112之間。在一實施例中，第一微電子裝置1101及第二微電子裝置1102可經對準以使得第一微電子裝置1101之多個高密度互連結構122直接相鄰於第二微電子裝置1102之高密度互連結構122。如熟習此項技術者將理解，可以預定間隔及取向利用精確拾取及放置設備來保證合適對準。
如圖3中所示，包封劑材料118可沉積於第一微電子裝置1101及第二微電子裝置1102上方，以使得包封劑材料118接觸第一微電子裝置1101及第二微電子裝置1102之後表面114及側面116。在一個實施例中，具有低熱膨脹係數的晶圓級壓縮模製材料可用來沉積包封劑材料118。包封劑材料118可為任何適當材料，包括但不限於具有或具有適當填料之聚合物材料。
如圖4中所示，包封劑材料118可經固化或部分地固化，且結構可藉由移除包封劑材料118的相鄰於第一微電子裝置1101及第二微電子裝置1102之後表面114的部分來薄化，以暴露其後表面114。此移除使得包封劑材 料118接觸第一微電子裝置1101及第二微電子裝置1102之側面116，從而形成被稱為重構晶圓120之結構。應理解，第一微電子裝置1101及第二微電子裝置1102之部分可在移除包封劑材料118之部分期間或之後移除，以減小重構晶圓120之厚度T。在一個實施例中，可在移除載體132(見圖4)及黏附層134(見圖4)之前執行包封劑材料118之部分的移除及第一微電子裝置1101及第二微電子裝置1102之部分的移除。在另一實施例中，可在移除載體132(見圖4)及黏附層134(見圖4)之後執行包封劑材料118之部分的移除及第一微電子裝置1101及第二微電子裝置1102之部分的移除，其中第一微電子裝置1101及第二微電子裝置1102可在移除包封劑材料118之部分及移除第一微電子裝置1101及第二微電子裝置1102之部分之前附接至後研磨帶(未展示)。包封劑材料118之部分的移除及第一微電子裝置1101及第二微電子裝置1102之部分的移除可藉由此項技術中已知的任何技術達成，包括但不限於機械研磨、蝕刻、化學機械平面化等。如熟習此項技術者將理解，材料移除可改良熱效能且可平面化重構晶圓120。
如圖5中所示，可形成微電子橋140，該微電子橋包含第一表面142、相反的第二表面144、以及至少一個側面146，該側面在第一表面142與第二表面144之間延伸。微電子橋140在微電子橋第一表面142上可包括諸如凸塊或支柱之多個互連結構152。如所例示，微電子橋140可包括形成於其中之多個傳導路線148，以連接相應微電 子橋互連結構152。如進一步例示，焊接材料154可藉由此項技術中已知的任何適當製程塗覆於互連結構154上，諸如使用電鍍技術形成細小但均勻的間距。
如圖6中所示，微電子橋140可附接至第一微電子裝置1101之高密度互連結構122及第二微電子裝置1102之高密度互連結構122，以便在其間形成電氣連接。在一個實施例中，微電子橋140之多個互連結構152處於第一微電子裝置1101及第二微電子裝置1102之多個高密度互連結構122的鏡像組態中，且利用焊接材料154藉由熱壓焊接附接至該等多個高密度互連結構122。在另一實施例中，當利用低熱膨脹係數的包封劑材料118時，不管微電子橋互連結構152之高密度/小間距如何，可利用傳統晶片附接模組製程來附接微電子橋140，因此微電子橋140與重構晶圓120之間的熱膨脹失配極小。用於形成微電子橋140之製程及材料在此項技術中熟知，並且為簡潔及簡明起見，本文中將不再描述或例示。
如圖7中所示，可形成微電子基板160，該微電子基板其中具有空腔170，該空腔自微電子基板160之第一表面162延伸至微電子基板160中，其中微電子基板空腔170由至少一個側壁174及底表面172界定。微電子基板160可進一步包括多個焊墊164，該等焊墊形成於微電子基板第一表面162中或微電子基板第一表面162上。微電子基板空腔170可由此項技術中已知的任何已知技術形成，包括但不限於，雷射剝蝕、控制深度路由、蝕刻等。
微電子基板160可為任何適當微電子基板，包括但不限於，內插器、母板等。此外，微電子基板160可包含多個介電層(未展示)，該等介電層具有多個傳導路線148，該等傳導路線由形成於介電層(未展示)上之傳導跡線(未展示)形成，該等傳導跡線與穿過介電層(未展示)形成之傳導通孔(未展示)連接。用於形成微電子基板160之製程及材料在此項技術中熟知，並且為簡潔及簡明起見，本文中將不再描述或例示。
如圖8中所示，圖6之結構可附接至微電子基板160，其中第一微電子裝置1101之多個較低密度互連結構124及第二微電子裝置1102之多個較低密度互連結構124可電氣附接至多個基板焊墊164，該等基板焊墊形成於微電子基板第一表面162中或微電子基板第一表面162上，其中微電子橋140延伸至微電子基板空腔170中。在一個實施例中，第一微電子裝置1101之多個較低密度互連結構124及第二微電子裝置1102之多個較低密度互連結構124處於多個微電子基板焊墊164之鏡像組態中，且利用焊接材料176藉由熱壓焊接附接至該等多個微電子基板焊墊164。在一個實施例中，焊接材料176可利用如此項技術中已知的微球處理塗覆至多個基板焊墊164。
如圖9中所示，底部填充材料178可設置在第一微電子裝置1101之主動表面112與微電子基板第一表面162之間、第二微電子裝置1102之主動表面112與微電子基板第一表面162之間，以及微電子基板空腔170內，以便形 成微電子結構180。在一個實施例中，如圖9中所例示，底部填充材料178可設置在微電子橋140之第二表面144與空腔170之底表面172之間。在另一實施例中，如圖10中所例示，諸如快速固化環氧樹脂的黏附材料182可在附接第一微電子裝置1101及第二微電子裝置1102之前設置在空腔170之底表面174上，以確保材料設置在微電子橋140之第二表面144與空腔170之底表面172之間。在一實施例中，毛細管底部填充製程可用來設置底部填充材料178。在另一實施例中，由於將要填充的空間之複雜性，高壓輔助的固化製程可用來設置底部填充材料178，如熟習此項技術者將理解。還應注意，底部填充材料178為填充空間之單個材料，如所描述。
圖11至圖16例示根據本說明書之另一實施例的製造微電子結構之方法。如圖11中所示，如所示且關於圖1所論述之第一微電子裝置1101及第二微電子裝置1102可於諸如熱壓焊接底座之載體202中被對準。在一個實施例中，第一微電子裝置1101及第二微電子裝置1102可利用其鄰接載體202之後表面114對準。在一實施例中，第一微電子裝置1101及第二微電子裝置1102可經對準以使得第一微電子裝置1101之多個高密度互連結構122直接相鄰於第二微電子裝置1102之高密度互連結構122。如熟習此項技術者將理解，可以預定間隔及取向利用精確拾取及放置設備來保證合適對準。
如圖12中所示，諸如環氧樹脂助熔劑材料之 助熔劑材料204可分配至第一微電子裝置1101之高密度互連結構122上，且可分配至第一微電子裝置1102之高密度互連結構122上。如圖13中所示，如關於圖5所論述之微電子橋140可附接至第一微電子裝置1101之高密度互連結構122及第二微電子裝置1102之高密度互連結構122，以便在其間形成電氣連接，其中助熔劑材料204在第一微電子裝置1101與微電子橋140之間延伸，且在第二微電子裝置1102與微電子橋140之間延伸。在一個實施例中，微電子橋140之多個互連結構152處於第一微電子裝置1101及第二微電子裝置1102之多個高密度互連結構122的鏡像組態中，且利用焊接材料154藉由熱壓焊接附接至該等多個高密度互連結構122。
如圖14中所示，圖13之結構可自載體202(見圖13)移除，且可附接至微電子基板160，如關於圖7所論述，其中第一微電子裝置1101之多個較低密度互連結構124及第二微電子裝置1102之多個較低密度互連結構124可電氣附接至多個基板焊墊164，該等多個基板焊墊形成於微電子基板第一表面162中或微電子基板第一表面162上，其中微電子橋140延伸至微電子基板空腔170中。在一個實施例中，第一微電子裝置1101之多個較低密度互連結構124及第二微電子裝置1102之多個較低密度互連結構124處於多個微電子基板焊墊164之鏡像組態中，且利用焊接材料176藉由熱壓焊接附接至該等多個微電子基板焊墊164。
如圖15中所示，底部填充材料178可設置在第一微電子裝置1101之主動表面112與微電子基板第一表面162之間、第二微電子裝置1102之主動表面112與微電子基板第一表面162之間，以及微電子基板空腔170內，以便形成微電子結構180。
在如圖6至圖10及圖13至圖15中所例示之一些實施例中，微電子橋140可為無源結構，在該無源結構中，其不具有除在第一微電子裝置1101與第二微電子裝置1102之間提供傳導路線148以外的功能。在其他實施例中，如圖16中所示，微電子橋140可包含至少一個主動組件214，該主動組件除橋接功能之外還具有其自身的功能，並且因此可為嵌入於微電子橋140中之微電子裝置、電阻器、電容器等。在一個實施例中，如圖16中所例示，微電子橋140可具有信號路由層212，該信號路由層具有利用焊接球222及/或引線黏結劑224電氣附接至信號路由層212之至少一個主動組件214，其中主動組件214可包封於介電材料216內。
應注意，本說明書之製程實施例在將微電子橋140與微電子基板160合併之前，將微電子橋140附接至第一微電子裝置1101及第二微電子裝置1102。與其中在附接第一微電子裝置1101及第二微電子裝置1102之前將微電子橋140嵌入於微電子基板160中之製程相比，此類製程可具有優點。例如，若微電子橋140嵌入於微電子基板160中，則將需要第一微電子裝置1101及第二微電子裝置1102 同時附接至混合間距的互連，此將使得一個步驟製程對於產生晶片附接製程所需要之均勻凸塊高度不再是可行選擇。如熟習此項技術者將理解，可能需要晶粒上焊接製程或多步驟石印及電鍍製程。然而，由於處理邊緣化，尤其對較大微電子結構而言，混合間距組態及嚴格的凸塊高度均勻性需求使得晶粒上焊接製程極難發展。
應理解，雖然關於圖1至圖16之實施例的詳細描述針對兩個微電子裝置1101及1102、一個微電子橋140、以及微電子基板160中之一個空腔170，但本說明書之標的並不如此受限，因為可使用任何數目之微電子裝置、微電子橋、以及微電子基板空腔。在一個實施例中，三個微電子裝置可附接至三角橋。在另一實施例中，六個微電子裝置可附接至六角橋。在進一步實施例中，多於一個微電子橋可設置在單個微電子基板空腔中。在更進一步實施例中，多個空腔可形成於單個微電子基板中。
圖17為根據本說明書之實施例的製造微電子結構之製程300的流程圖。如方框302中所闡述，可形成第一微電子裝置及第二微電子裝置，其中第一微電子裝置及第二微電子裝置中之每一者在其主動表面上包括多個高密度互連結構及多個較低密度互連結構。微電子橋可附接至第一微電子裝置之多個高密度互連結構及第二微電子裝置之多個高密度互連結構，如方框304中所闡述。如方框306中所闡述，可形成微電子基板，該微電子基板具有界定於其中之空腔，該空腔自微電子基板之第一表面延伸， 其中該空腔包括至少一個側壁及底表面。第一微電子裝置之多個較低密度互連結構及第二微電子裝置之多個較低密度互連結構可電氣附接至微電子基板之第一表面，其中微電子橋延伸至微電子基板空腔中，如方框308中所闡述。
圖18例示根據本說明書之一個實行方案的計算裝置400。計算裝置400容納板402。板可包括數個微電子組件，包括但不限於處理器404、至少一個通訊晶片406A、406B、依電性記憶體408(例如，DRAM)、非依電性記憶體410(例如，ROM)、快閃記憶體412、圖形處理器或CPU 414、數位信號處理器(未展示)、密碼處理器(未展示)、晶片組416、天線、顯示器(觸控螢幕顯示器)、觸控螢幕控制器、蓄電池、音訊編解碼器(未展示)、視訊編解碼器(未展示)、功率放大器(AMP)、全球定位系統(GPS)裝置、羅盤、加速計(未展示)、回轉儀(未展示)、揚聲器(未展示)、相機，及大容量儲存裝置(未展示)(諸如，硬碟片驅動機、光碟片(CD)、數位通用碟片(DVD)，等等)。微電子組件中之任一者可實體地且電氣地耦接至板402。在一些實行方案中，微電子組件中之至少一者可為處理器404之一部分。
通訊晶片406A、406B啟用用於資料至計算裝置400及自該計算裝置400之傳送的無線通訊。「無線」一詞及其派生詞可用來描述可經由非固體媒體藉由調變電磁輻射之使用來通訊資料的電路、裝置、系統、方法、技術、通訊通道等。該術語並非暗示相關聯裝置不含有任何 引線，但是在一些實施例中該等相關聯裝置可不含有任何引線。通訊晶片306可實施數個無線標準或協定中之任一者，包括但不限於Wi-Fi(IEEE 802.11系列)、WiMAX(IEEE 802.16系列)、IEEE 802.20、長期演進(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、藍牙、其衍生物，以及命名為3G、4G、5G及更高之任何其他無線協定。計算裝置400可包括多個通訊晶片406A、406B。例如，第一通訊晶片406A可專用於較短範圍之無線通訊，諸如Wi-Fi及藍牙，且第二通訊晶片406B可專用於較長範圍之無線通訊，諸如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO，及其他。
「處理器」一詞可指代處理來自暫存器及/或記憶體之電子資料，以將該電子資料轉換成可儲存於暫存器及/或記憶體中之其他電子資料的任何裝置或裝置之部分。
計算裝置400內之微電子組件中之任一者可包括彼此連接的微電子裝置，該等微電子裝置具有嵌入於根據上述實行方案形成之微電子基板中的微電子橋。
在各種實行方案中，計算裝置400可為膝上型電腦、隨身型易網機、筆記型電腦、超極致筆電(ultrabook)、智慧型電話、平板電腦、個人數位助理(PDA)、超行動PC、行動電話、桌上型電腦、伺服器、印表機、掃描器、監視器、機上盒(set-top box)、娛樂控制 單元、數位相機、可攜式音樂播放器或數位視訊記錄器。在其他實行方案中，計算裝置400可為處理資料之任何其他電子裝置。
應理解，本說明書之標的不一定限於圖1至圖18中所例示之特定應用。標的可應用於其他微電子裝置及組裝應用，以及任何適當的電子應用，如熟習此項技術者將理解的。
以下實例係關於其他實施例。實例中之細節可在一或多個實施例中之任何處使用。
在實例1中，形成微電子結構之方法可包含：形成第一微電子裝置及第二微電子裝置，其中第一微電子裝置及第二微電子裝置中之每一者在其主動表面上包括多個高密度互連結構及多個較低密度互連結構；將微電子橋附接至第一微電子裝置之多個高密度互連結構及第二微電子裝置之多個高密度互連結構；形成微電子基板，該微電子基板具有界定於其中之空腔，該空腔自微電子基板之第一表面延伸，其中該空腔包括至少一個側壁及底表面；以及將第一微電子裝置之多個較低密度互連結構及第二微電子裝置之多個較低密度互連結構電氣附接至微電子基板之第一表面，其中微電子橋延伸至微電子基板空腔中。
在實例2中，實例1之標的可任擇地包括：微電子橋電氣連接第一微電子裝置及第二微電子裝置。
在實例3中，實例1之標的可任擇地包括：微電子橋包括其中之多個傳導路線。
在實例4中，實例1之標的可任擇地包括：微電子橋包括嵌入於其中之至少一個微電子裝置。
在實例5中，實例1之標的可任擇地包括：將底部填充材料設置在第一微電子裝置主動表面與微電子基板第一表面之間、第二微電子裝置主動表面與微電子基板第一表面之間，以及微電子基板空腔內。
在實例6中，實例1至5中任一者之標的可任擇地包括：在附接微電子橋之前，由第一微電子裝置及第二微電子裝置形成重構晶圓。
在實例7中，實例6之標的可任擇地包括：形成重構晶圓包含將包封劑材料設置在第一微電子裝置之至少一個側面與第二微電子裝置之至少一個側面之間。
在實例8中，實例7之標的可任擇地包括：利用，將載體上的第一微電子裝置及第二微電子裝置與面向載體的第一微電子裝置及第二裝置中之各者的主動表面對準；並且其中設置包封劑材料包含將包封劑材料設置於第一微電子裝置之後表面及第二微電子裝置之後表面上方。
在實例9中，實例8之標的可任擇地包括：將第一微電子裝置及第二微電子裝置對準於載體上進一步包含將第一微電子裝置及第二微電子裝置黏附至具有黏附層之載體。
在實例10中，實例8之標的可任擇地包括：移除包封劑材料之一部分以暴露第一微電子裝置之後表面 及第二微電子裝置之後表面。
在實例11中，實例10之標的可任擇地包括：移除第一微電子裝置及第二微電子裝置之一部分。
在實例12中，實例1至5中任一者之標的可任擇地包括：將微電子橋附接至第一微電子裝置之多個高密度互連結構及第二微電子裝置之多個高密度互連結構包含將第一微電子裝置及第二微電子裝置中之每一者的後表面對準於載體上，以及附接微電子橋。
在實例13中，實例12之標的可任擇地包括：將助熔劑材料設置於第一微電子裝置之多個高密度互連表面上及第二微電子裝置之多個高密度互連表面上；以及經由該助熔劑材料附接微電子橋。
在實例14中，微電子結構可包含：形成第一微電子裝置及第二微電子裝置，其中第一微電子裝置及第二微電子裝置中之每一者在其主動表面上包括多個高密度互連結構及多個較低密度互連結構；微電子橋，該微電子橋附接至第一微電子裝置之多個高密度互連結構及第二微電子裝置之多個高密度互連結構；微電子基板，該微電子基板具有界定於其中之空腔，該空腔自微電子基板之第一表面延伸，其中該空腔包括至少一個側壁及底表面，其中第一微電子裝置之多個較低密度互連結構及第二微電子裝置之多個較低密度互連結構電氣附接至微電子基板之第一表面，並且其中微電子橋延伸至微電子基板空腔中；以及底部填充材料，該底部填充材料處於第一微電子裝置主 動表面與微電子基板第一表面之間、第二微電子裝置主動表面與微電子基板第一表面之間，以及微電子基板空腔內。
在實例15中，實例14之標的可任擇地包括：微電子橋電氣連接第一微電子裝置及第二微電子裝置。
在實例16中，實例14之標的可任擇地包括：微電子橋包括其中之多個傳導路線。
在實例17中，實例14之標的可任擇地包括：微電子橋包括嵌入於其中之至少一個微電子裝置。
在實例18中，實例14至17中任一者之標的可任擇地包括重構晶圓，該重構晶圓由第一微電子裝置及第二微電子裝置形成。
在實例19中，實例18之標的可任擇地包括：重構晶圓包括包封劑材料，該包封劑材料處於第一微電子裝置之至少一個側面與第二微電子裝置之至少一個側面之間。
在實例20中，實例14之標的可任擇地包括助熔劑材料，該助熔劑材料設置於第一微電子裝置與微電子橋之間，以及第二微電子裝置與微電子橋之間。
在實例21中，計算裝置可包含板及微電子結構，該微電子結構附接至該板，其中微電子結構包含第一微電子裝置及第二微電子裝置，其中第一微電子裝置及第二微電子裝置中之每一者在其主動表面上包括多個高密度互連結構及多個較低密度互連結構；微電子橋，該微電子橋附接至第一微電子裝置之多個高密度互連結構及第二 微電子裝置之多個高密度互連結構；微電子基板，該微電子基板具有界定於其中之空腔，該空腔自微電子基板之第一表面延伸，其中該空腔包括至少一個側壁及底表面，其中第一微電子裝置之多個較低密度互連結構及第二微電子裝置之多個較低密度互連結構電氣附接至微電子基板之第一表面，並且其中微電子橋延伸至微電子基板空腔中；以及底部填充材料，該底部填充材料處於第一微電子裝置主動表面與微電子基板第一表面之間、第二微電子裝置主動表面與微電子基板第一表面之間，以及微電子基板空腔內。
在實例22中，實例21之標的可任擇地包括：微電子橋電氣連接第一微電子裝置及第二微電子裝置。
在實例23中，實例21之標的可任擇地包括：微電子橋包括其中之多個傳導路線。
在實例24中，實例21之標的可任擇地包括：微電子橋包括嵌入於其中之至少一個微電子裝置。
在實例25中，實例21至24中任一者之標的可任擇地包括重構晶圓，該重構晶圓由第一微電子裝置及第二微電子裝置形成。
在實例26中，實例25之標的可任擇地包括：重構晶圓包括包封劑材料，該包封劑材料處於第一微電子裝置之至少一個側面與第二微電子裝置之至少一個側面之間。
在實例27中，實例21之標的可任擇地包括助熔劑材料，該助熔劑材料設置於第一微電子裝置與微電 子橋之間，以及第二微電子裝置與微電子橋之間。
因此已詳細描述了本說明書之實施例，應理解，由所附申請專利範圍定義之本說明書不受以上描述中所闡述之特定細節限制，因為在不脫離其精神或範疇的情況下，許多其明顯的變體係可能的。
1101‧‧‧第一微電子裝置/微電子裝置
1102‧‧‧第二微電子裝置/微電子裝置
112‧‧‧主動表面
114‧‧‧後表面
116‧‧‧側面
122‧‧‧高密度互連結構
124‧‧‧較低密度互連結構
P1、P2‧‧‧間距/間隔

Claims (25)

  1. 一種形成一微電子結構之方法，其包含：形成一第一微電子裝置及一第二微電子裝置，其中該第一微電子裝置及該第二微電子裝置中之各者在其一主動表面上包括多個高密度互連結構及多個較低密度互連結構；將一微電子橋附接至該第一微電子裝置之該等多個高密度互連結構及該第二微電子裝置之該等多個高密度互連結構；形成一微電子基板，其具有界定於其中之一空腔，該空腔自該微電子基板之一第一表面延伸，其中該空腔包括至少一個側壁及一底表面；以及將該第一微電子裝置之該等多個較低密度互連結構及該第二微電子裝置之該等多個較低密度互連結構電氣附接至該微電子基板之該第一表面，其中該微電子橋延伸至該微電子基板空腔中。
  2. 如請求項1之方法，其中該微電子橋電氣連接該第一微電子裝置及該第二微電子裝置。
  3. 如請求項1之方法，其中該微電子橋包括其中之多個傳導路線。
  4. 如請求項1之方法，其中該微電子橋包括被嵌入於其中之至少一個微電子裝置。
  5. 如請求項1之方法，其進一步包括：將一底部填充材料設置在該第一微電子裝置主動表面與該微電子基板第一表面之間、在該第二微電子裝置主動表面與該微電子基板第一表面之間，以及在該微電子基板空腔內。
  6. 如請求項1之方法，其進一步包含：在附接該微電子橋之前，由該第一微電子裝置及該第二微電子裝置所形成一重構晶圓。
  7. 如請求項6之方法，其中形成該重構晶圓包含：將一包封劑材料設置在該第一微電子裝置之至少一側與該第二微電子裝置之 至少一側之間。
  8. 如請求項7之方法，其進一步包括：利用，將一載體上的該第一微電子裝置及該第二微電子裝置與面向該載體的該第一微電子裝置及該第二裝置中之各者的該主動表面對準；並且其中設置該包封劑材料包含：將該包封劑材料設置於該第一微電子裝置之一後表面及該第二微電子裝置之一後表面上方。
  9. 如請求項8之方法，其中將該載體上的該第一微電子裝置及該第二微電子裝置對準進一步包含：利用一黏附層將該第一微電子裝置及該第二微電子裝置黏附至該載體。
  10. 如請求項8之方法，其進一步包含：移除該包封劑材料之一部分以暴露該第一微電子裝置之該後表面及該第二微電子裝置之該後表面。
  11. 如請求項10之方法，其進一步包含移除該第一微電子裝置及該第二微電子裝置之一部分。
  12. 如請求項1之方法，其中將該微電子橋附接至該第一微電子裝置之該等多個高密度互連結構及該第二微電子裝置之該等多個高密度互連結構包含：將該載體上的該第一微電子裝置及該第二微電子裝置中之各者的一後表面對準，以及附接該微電子橋。
  13. 如請求項12之方法，其進一步包含：將一助熔劑材料設置於該第一微電子裝置之該等多個高密度互連表面上及該第二微電子裝置之該等多個高密度互連表面上；以及透過該助熔劑材料附接該微電子橋。
  14. 一種微電子結構，其包含：一第一微電子裝置及一第二微電子裝置，其中該第一微電子裝置及該第二微電子裝置中之各者在其一主動表面上包括多個高密度互連結構及多個較低密度互連結構；一微電子橋，其被附接至該第一微電子裝置之該等多個高密度互連結構及該第二微電子裝置之該等多個高密度互連結構； 一微電子基板，其具有界定於其中之一空腔，該空腔自該微電子基板之一第一表面延伸，其中該空腔包括至少一個側壁及一底表面，其中該第一微電子裝置之該等多個較低密度互連結構及該第二微電子裝置之該等多個較低密度互連結構係電氣附接至該微電子基板之該第一表面，並且其中該微電子橋延伸至該微電子基板空腔中；以及一底部填充材料，其在該第一微電子裝置主動表面與該微電子基板第一表面之間、在該第二微電子裝置主動表面與該微電子基板第一表面之間，以及在該微電子基板空腔內。
  15. 如請求項14之微電子結構，其中該微電子橋電氣連接該第一微電子裝置及該第二微電子裝置。
  16. 如請求項14之微電子結構，其中該微電子橋包括其中之多個傳導路線。
  17. 如請求項14之微電子結構，其中該微電子橋包括被嵌入於其中之至少一個微電子裝置。
  18. 如請求項14之微電子結構，其進一步包含一重構晶圓，該重構晶圓由該第一微電子裝置及該第二微電子裝置所形成。
  19. 如請求項18之微電子結構，其中該重構晶圓包括一包封劑材料，該包封劑材料在該第一微電子裝置之至少一側與該第二微電子裝置之至少一側之間。
  20. 如請求項14之微電子結構，其進一步包含一助熔劑材料，該助熔劑材料被設置在該第一微電子裝置與該微電子橋之間，以及在該第二微電子裝置上與該微電子橋之間。
  21. 一種計算裝置，其包含：一板；一微電子結構，其被附接至該板，其中該微電子結構包含：一第一微電子裝置及一第二微電子裝置，其中該第一微電子裝置及該第二微電子裝置中之各者在其一主動表面上包括多個高密度互連結構及多個較低密度互連結構； 一微電子橋，其被附接至該第一微電子裝置之該等多個高密度互連結構及該第二微電子裝置之該等多個高密度互連結構；一微電子基板，其具有界定於其中之一空腔，該空腔自該微電子基板之一第一表面延伸，其中該空腔包括至少一個側壁及一底表面，其中該第一微電子裝置之該等多個較低密度互連結構及該第二微電子裝置之該等多個較低密度互連結構係電氣附接至該微電子基板之該第一表面，並且其中該微電子橋延伸至該微電子基板空腔中；以及一底部填充材料，其在該第一微電子裝置主動表面與該微電子基板第一表面之間、在該第二微電子裝置主動表面與該微電子基板第一表面之間，以及在該微電子基板空腔內。
  22. 如請求項21之計算裝置，其中該微電子橋電氣連接該第一微電子裝置及該第二微電子裝置。
  23. 如請求項21之計算裝置，其進一步包含一重構晶圓，該重構晶圓由該第一微電子裝置及該第二微電子裝置所形成。
  24. 如請求項23之計算裝置，其中該重構晶圓包括一包封劑材料，該包封劑材料在該第一微電子裝置之至少一側與該第二微電子裝置之至少一側之間。
  25. 如請求項21之計算裝置，其進一步包含一助熔劑材料，該助熔劑材料被設置在該第一微電子裝置與該微電子橋之間，以及在該第二微電子裝置上與該微電子橋之間。
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