TW201622024A - 安裝晶片的方法與安裝晶片的裝置 - Google Patents

安裝晶片的方法與安裝晶片的裝置 Download PDF

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TW201622024A
TW201622024A TW104139911A TW104139911A TW201622024A TW 201622024 A TW201622024 A TW 201622024A TW 104139911 A TW104139911 A TW 104139911A TW 104139911 A TW104139911 A TW 104139911A TW 201622024 A TW201622024 A TW 201622024A
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wafer
front side
mounting
solder beads
solder
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TWI682469B (zh
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瓦金斯 賽巴斯提安 休勒
拉夫 萊賢巴哈
漢斯 彼德 貝爾
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羅伯特博斯奇股份有限公司
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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Abstract

一種安裝晶片的方法，包括以下步驟：提供一個具有一前側(V)及一後側(R)的載體基材(1)；將第一多數個組的第一種銲錫珠(L1)(L2),(L3)(L4)到該前側(V)上；將第二多數個組的晶片(C1)(C2)用倒裝晶片方法施加到該前側(V)上，其中各有一組第一種銲錫珠(L1)(L2),(L3)(L4)設在一相關晶片的周圍；將一種下填料(UF)施到該前側(V)上以將該晶片(C1)(C2)至少部分地下填，其中該下填料(UF)局部沈積到該第一銲錫珠(L1)(L2),(L3)(L4)上；做一道電漿清潔步驟，以將該下填料從該第一種銲錫珠(L1)(L2),(L3)(L4)至少部分地除去，其中該晶片(C1)(C2)至少保持部分下填充；且將該晶片(C1)(C2)與該各組的第一種銲錫珠(L1)(L2),(L3)(L4)及該載體基材(1)的一相關區域(1a)(1b)的複合物切分，此外關於一種一種安裝晶片的裝置，具有一載體基材(1)的一區域(1a)(1b)，其具有一前側(Va)(Vb)及一後側(Ra)(Rb)， 一晶片(C1)(C2)，其用導裝晶片方法設到該前側(Va)(Vb)，一組第一銲錫珠(L1)(L2),(L3)(L4)，設在晶片(C1)(C2)周圍，及一下充填部(UF)，充填到該前側(V)，它將該晶片(C1)(C2)至少部分地下充填，其中該下填充部(UF’)有一用電漿蝕刻的表面(DF)。

Description

安裝晶片的方法與安裝晶片的裝置
本發明關於一種安裝晶片的方法及一種安裝晶片的裝置。
一般安裝晶片的裝置(其中個別晶片用倒裝晶片方法裝到一載體基材上)一般設計成使個別的晶片在軟銲上去後利用一種下充填料(Unterfüllung)(例如一種環氧樹脂)作下充填以造成較高的程序強固性(rubustness)，其背景為一種鋸子切分程序，其中要避免鋸屑跑到晶片和載體基材之間。
如果除了所裝晶片外還要在載體基材斗設銲錫珠(Lötkugelchen,英：solder bead)則它們要距晶片一段一定的超碼最小距離(典型者大於200微米)，俾使下充填料不會污染銲錫珠，這點對隨後的軟銲程序會造成可靠性的問題。
DE 10 2005 051330 A1發表了一種電路載體用的可表面安裝的半導體晶片的製造方法，其中準備一種具有設成行與列的半導體晶片位置的半導體晶圓，它具有金屬接觸面，其經由表面受保護的導線路與半導體位置的半導體元件構造呈作用連接，將一導電的晶核層施到半導體晶圓表面，將晶核層用絕緣的護層蓋住而留著接觸面區域露出，並選擇性地將 外接點插座析出該露出而可自由抵達的接觸面區域，然後在一電漿化灰(Veraschung,英：ashing)步驟將使層化灰燼除去，隨後將晶核層作電漿蝕刻。
US 2004/0223696 A1發表了將從側邊相鄰的晶片跑出來的下填充料用微球粒噴砂程序除去。
本發明提供一種申請專利範圍第1項的安裝方法和申請專利範圍第11項的安裝晶片的裝置。
本發明的構想在於銲鍚珠受下填充料的污染處在隨後的清潔程序除去。
清潔程序係用一道短短的電漿化灰步驟，它將下填充部上側的一薄層除去，但下填充部的母質(Matrix)不破壞，因此下填充部留在晶片下方或在晶片邊緣區域，因此其作鋸切保護的功能不喪失。
本發明因此可減少晶片和載體基材上的銲鍚珠間的距離減少，而不須忍受可靠性的問題的代價，這點可使相關產品的包封尺寸〔脚印(footprint)〕更小。
本發明標的之進一步有利特點見於申請專利範圍附屬項。
依一較佳實施例，第一組銲錫珠裝到在前側形成的各半導體區域上，這點提高穩定性。
依另一較佳實施例，晶片裝以第二組的多數銲錫珠。
依又一實施例，該下填料用一供應程序施加，這點可達成較快的程序步驟，特別有利的是使用一道噴料供應程序，這點可使一定量的料很準確地供應。
依再一有利實施例，用於除去下填料的電漿清潔步造成化灰，這點用於使之無殘餘物留下。
依另一較佳實施例，第一組銲錫珠在前側突伸超出晶片一預定距離，這點對進一步安裝有利。
依又一較佳實施例，用於除去下填料的電裝清潔步驟利用一個受質溶儀控制的終點檢出而在一定的程序停住。
依再一較佳實施例，切分的晶片配合各第一組銲錫珠及載體基材的相關區域軟銲到一電路基材上。
依另一較佳實施例，切分作業用一道鋸切程序達成。
以下利用圖式中示意圖示的圖所示之實施例詳細說明。
(1)‧‧‧載體基材
(100)‧‧‧電路基材
C1‧‧‧晶片
C2‧‧‧晶片
d2‧‧‧距離用圖號
L1‧‧‧第一銲錫珠
L2‧‧‧第一銲錫珠
L3‧‧‧第一銲錫珠
L4‧‧‧第一銲錫珠
P1‧‧‧附著區域
P2‧‧‧附著區域
P3‧‧‧附著區域
P4‧‧‧附著區域
PS1‧‧‧附著面
PS2‧‧‧附著面
PS3‧‧‧附著面
PS4‧‧‧附著面
R‧‧‧後側
Ra‧‧‧後側
Rb‧‧‧後側
S1‧‧‧第二銲錫珠
S2‧‧‧第二銲錫珠
S3‧‧‧第二銲錫珠
S4‧‧‧第二銲錫珠
SP‧‧‧縫隙
UF’‧‧‧下填充料
V‧‧‧前側
Va‧‧‧前側
Vb‧‧‧前側
圖1a~1e係為本發明的晶片安裝程序的一實施例中先後相隨的程序階段。
在圖式中相同圖號表示相同或功能相同的元件。
圖1a中，圖號(1)表示一載體基材(例如一晶圓基材)它具有一前側V及一後側R。
第一多數組的第一銲錫珠(L1)(L2)及(L3)(L4)設到前側的相關附著區域(P1)(P2)(P3)(P4)。
此外，參考圖1b，有一第二多數的晶片(C1),(C2)用倒裝晶片法設到前側(V)上，其中各有一組第一銲鍚珠(L1)(L2)或(L3)(L4)設在一相關 晶片的周圍，稍後，這些銲錫珠(L1)(L2)或(L3)(L4)用於安裝到一電路基材上的安裝作業。
為此，晶片(C1)(C2)各經另一組之較小的第二銲錫珠(S1)(S2)或(S3)(S4)軟銲到載體基材(1)的相關附著面(PS1)(PS2)或(PS3)(PS4)。
在圖1a所示的程序狀態，銲錫珠(L1)(L2)(L3)(L4)突伸超出所安裝的晶片(C1)(C2)，典型的超出距離d1為50~80微米，且舉例而言，高度為200~250微米，銲錫珠(L1)(L2)(L3)(L4)和各相關晶片(C1)或(T2)間的距離用圖號d2表示，典型值為50~100微米。
依圖1b在一隨後的程序步驟，將下填料(例如一種環氧樹脂)作下充填利用定量供量下充填到前側(V)上或利用類似的方法，俾使安裝的晶片(C1)(C2)至少部分地或完全地下充填，在此下充填料(UF)也沈積在晶片(C1)(C2)之背向載體基材的那一側上以及沈積在銲錫珠(L1)(L2)(L3)(L4)上。
此外請看圖1c，在隨後作一道電漿蝕刻程序PE，其中將下填料UF從第一銲錫珠(L1)(L2)(L3)(L4)及從晶片(C1)(C2)除去，其中晶片(C1)(C2)至少部分地保持下充填，因此在背蝕刻的狀態，下填充料(UF’)往往在隨後的切分程序及安裝程序造成保護作用。
在電漿化灰步驟，下填料(UF)的表面(DF)略受損，但其母質保持安然無痣。
隨後依圖1d作鋸切晶片(C1)(C2)的切分程序(SV)，配合各組之第一銲錫珠(L1)(L2)或(L3)(L4)及載體基材(100)的一相關區域(1a)(1b)作切分，因此，切分的晶片(C1)(C2)具有各一前側(Va)(Vb)及各一後側(Ra)(Rb)， 它們可個別用於作進一步安裝。
如圖1e所示，進一步的安裝，舉例而言，係軟銲到一電路基材軟銲到一電路基材(100)的半區域(P10)(P20)上，在圖1e的程序狀態，在晶片(C1)經由銲錫珠(L1)(L2)安裝到電路基材(100)上後，在背向載體基材區域的那一側和電路基材間留一縫隙(SP)。
雖然本發明只利用較佳實施例說明，但這並不限制其範圍，而係可用各種方式變更。
特別是所述材料和幾何形狀只是舉例，且可任意變更。
(1)‧‧‧載體基材
C1‧‧‧晶片
C2‧‧‧晶片
L1‧‧‧第一銲錫珠
L2‧‧‧第一銲錫珠
L3‧‧‧第一銲錫珠
L4‧‧‧第一銲錫珠
d2‧‧‧距離用圖號
P1‧‧‧附著區域
P2‧‧‧附著區域
P3‧‧‧附著區域
P4‧‧‧附著區域
R‧‧‧後側
S1‧‧‧第二銲錫珠
S2‧‧‧第二銲錫珠
S3‧‧‧第二銲錫珠
S4‧‧‧第二銲錫珠
PS1‧‧‧附著面
PS2‧‧‧附著面
PS3‧‧‧附著面
PS4‧‧‧附著面
UF’‧‧‧下填充料

Claims (12)

  1. 一種安裝晶片的方法，包括以下步驟：提供一個具有一前側(V)及一後側(R)的載體基材(1)；將第一多數個組的第一種銲錫珠(L1)(L2),(L3)(L4)到該前側(V)上；將第二多數個組的晶片(C1)(C2)用倒裝晶片方法施加到該前側(V)上，其中各有一組第一種銲錫珠(L1)(L2),(L3)(L4)設在一相關晶片的周圍；將一種下填料(UF)施到該前側(V)上以將該晶片(C1)(C2)至少部分地下填，其中該下填料(UF)局部沈積到該第一銲錫珠(L1)(L2),(L3)(L4)上；做一道電漿清潔步驟，以將該下填料從該第一種銲錫珠(L1)(L2),(L3)(L4)至少部分地除去，其中該晶片(C1)(C2)至少保持部分下填充；且將該晶片(C1)(C2)與該各組的第一種銲錫珠(L1)(L2),(L3)(L4)及該載體基材(1)的一相關區域(1a)(1b)的複合物切分。
  2. 如申請專利範圍第1項之安裝晶片的方法，其中：該第一種銲錫珠(L1)(L2),(L3)(L4)施在各個在該前側上(V)形成的附著區域(P1)~(P4)上。
  3. 如申請專利範圍第1或第2項之安裝晶片的方法，其中：該晶片(C1)(C2)用一第二多數個組的第二種銲錫珠(S1)(S2),(S3)(S4)施加。
  4. 如申請專利範圍第1或第2項之安裝晶片的方法，其中：將該下填料(UF)用一道供給程序施加。
  5. 如申請專利範圍第1或第2項之安裝晶片的方法，其中：將該下填料(UF)一道噴料供給程序施加。
  6. 如申請專利範圍第1或第2項之安裝晶片的方法，其中：該用於除去下填料的電漿清潔步驟造成化灰(Veraschung)。
  7. 如申請專利範圍第1或第2項之安裝晶片的方法，其中：該第一種銲錫珠(L1)(L2),(L3)(L4)在該前側(V)上突伸超出該晶片(C1)(C2)一段預定距離(d1)。
  8. 如申請專利範圍第1或第2項之安裝晶片的方法，其中：該用於除去下填料(UF))的電漿清潔步驟藉著用質溶儀控制檢出終點而在一定程度停止。
  9. 如申請專利範圍第1或第2項之安裝晶片的方法，其中：該切分出的晶片(C1),(C2)連同該各組第一種銲錫珠(L1)(L2),(L3)(L4)及該載體基材(1)的相關區域(1)銲到一電路基材(100)上。
  10. 如申請專利範圍第1或第2項之安裝晶片的方法，其中：該切分作業用一道鋸切程序達成。
  11. 一種安裝晶片的裝置，具有一載體基材(1)的一區域(1a)(1b)，其具有一前側(Va)(Vb)及一後側(Ra)(Rb)，一晶片(C1)(C2)，其用導裝晶片方法設到該前側(Va)(Vb)，一組第一銲錫珠(L1)(L2),(L3)(L4)，設在晶片(C1)(C2)周圍，及一下充填部(UF)，充填到該前側(V)，它將該晶片(C1)(C2)至少部分地下充填，其中該下填充部(UF’)有一用電漿蝕刻的表面(DF)。
  12. 如申請專利範圍第11項之安裝晶片的裝置，其中： 該第一組銲鍚珠(L1)(L2),(L3)(L4)軟銲到一電路基材(100)上。
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