KR20160065749A - 칩 실장 방법 및 칩 실장체 - Google Patents
칩 실장 방법 및 칩 실장체 Download PDFInfo
- Publication number
- KR20160065749A KR20160065749A KR1020150166626A KR20150166626A KR20160065749A KR 20160065749 A KR20160065749 A KR 20160065749A KR 1020150166626 A KR1020150166626 A KR 1020150166626A KR 20150166626 A KR20150166626 A KR 20150166626A KR 20160065749 A KR20160065749 A KR 20160065749A
- Authority
- KR
- South Korea
- Prior art keywords
- chip
- solder balls
- filler
- providing
- carrier substrate
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 36
- 229910000679 solder Inorganic materials 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000000945 filler Substances 0.000 claims description 22
- 238000004140 cleaning Methods 0.000 claims description 7
- 238000004380 ashing Methods 0.000 claims description 6
- 238000001514 detection method Methods 0.000 claims description 2
- 238000001020 plasma etching Methods 0.000 claims description 2
- 239000013049 sediment Substances 0.000 abstract 1
- 239000011805 ball Substances 0.000 description 19
- 239000004065 semiconductor Substances 0.000 description 6
- 239000010410 layer Substances 0.000 description 5
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 235000012431 wafers Nutrition 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000011806 microball Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000005488 sandblasting Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
- H01L21/02046—Dry cleaning only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
- H01L23/295—Organic, e.g. plastic containing a filler
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/80009—Pre-treatment of the bonding area
- H01L2224/8001—Cleaning the bonding area, e.g. oxide removal step, desmearing
- H01L2224/80013—Plasma cleaning
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83104—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus by applying pressure, e.g. by injection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83909—Post-treatment of the layer connector or bonding area
- H01L2224/8391—Cleaning, e.g. oxide removal step, desmearing
- H01L2224/83911—Chemical cleaning, e.g. etching, flux
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0302—Properties and characteristics in general
- H05K2201/0305—Solder used for other purposes than connections between PCB or components, e.g. for filling vias or for programmable patterns
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10954—Other details of electrical connections
- H05K2201/10977—Encapsulated connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Die Bonding (AREA)
Abstract
본 발명은 칩 실장 방법에 관한 것이다. 상기 방법은, 전방 면(V) 및 후방 면(R)을 구비한 캐리어 기판(1)을 제공하는 단계와, 제1 솔더 볼(L1, L2; L3, L4)의 제1 복수의 그룹을 전방 면(V) 상에 제공하는 단계와, 플립 칩 방법으로 제2 복수의 칩(C1; C2)을 전방 면(V) 상에 제공하는 단계로서, 이때 제1 솔더 볼(L1, L2; L3, L4)의 각각 하나의 그룹은, 하나의 해당 칩의 주변에 배치되는 단계와, 칩(C1; C2)을 적어도 부분적으로 충진하기 위해, 전방 면(V) 상에 충진제(UF)를 제공하는 단계로서, 이때 충진제(UF)는 영역에 따라 제1 솔더 볼(L1, L2; L3, L4) 상에 침전되는 단계와, 제1 솔더 볼(L1, L2; L3, L4)로부터 충진제(UF)를 적어도 부분적으로 제거하기 위한 플라즈마 세정 단계를 실행하는 단계로서, 이때 칩(C1; C2)은 적어도 부분적으로 충진 상태로 유지되는 단계와, 제1 솔더 볼(L1, L2; L3, L4)의 각각의 그룹 및 캐리어 기판(1)의 상응하는 영역(1a; 1b)과 결합되어 칩(C1; C2)을 개별화하는 단계를 포함한다.
Description
본 발명은 칩 실장 방법 및 칩 실장체에 관한 것이다.
개별 칩이 플립 칩 방법으로 캐리어 기판 상에 제공되는 칩 실장체는 통상, 향상된 공정 견고성을 달성하기 위해, 납땜 후에 개별 칩이 충진제, 예를 들어 에폭시로 충진되는(underfilling) 방식으로 형성된다. 그 배경에는 칩과 캐리어 기판 사이에 쏘잉(sawing) 잔여물이 도달하는 것이 방지되어야 하는 쏘잉 분리 공정이 있다.
제공된 칩 이외에 솔더 볼이 캐리어 기판 상에 제공되어야 할 경우, 주목해야 할 점은, 이러한 솔더 볼이 칩에 대해 (통상 200㎛보다 큰) 특정 최소 간격을 포함함으로써, 충진제가 솔더 볼을 오염시킬 수 없는데, 이는 후속적인 납땜 공정에 있어서 신뢰성 문제를 나타낼 수도 있다는 것이다.
DE 10 2005 051 330 A1에는 회로 기판용으로 표면 실장 가능한 반도체 칩 제조 방법이 공지되어 있으며, 반도체 웨이퍼는 행과 열로 배치된 반도체 칩 위치에 의해 제공되며, 반도체 칩 위치는, 표면 보호된 전도 경로를 통해 반도체 칩 위치의 반도체 소자 구조와 작용 연결되는 금속 접촉면을 포함한다. 전도성 시드층이 반도체 웨이퍼의 표면 측에 제공되며, 시드층이 접촉면 영역의 노출 하에 절연 보호층에 의해 덮이고, 시드층 상의 외부 접촉 소켓은 자유로이 접근 가능한 접촉면 영역 내로 선택적으로 분리된다. 이어서, 보호층은 플라즈마 애싱 단계에서 이어지는 시드층의 플라즈마 에칭 하에 제거된다.
US 2004/0223696 A1에는 마이크로 볼들을 이용하는 샌드 블래스트 방법으로, 실장된 칩 옆의 측면에서 나오는 충진제를 제거하는 것이 공지되어 있다.
본 발명은 청구항 제1항에 따른 칩 실장 방법 및 청구항 제11항에 따른 칩 실장체를 제공한다.
본 발명은 충진제를 통한 솔더 볼 상의 오염을 후속되는 세정 공정에서 제거하는 사상에 기초한다.
세정 공정으로서, 충진제의 상부 면의 박막층을 제거하나, 충진제의 매트릭스를 파괴하지 않는 짧은 플라즈마 애싱 단계가 제안된다. 이로써, 충진제는 칩의 하부에 또는 칩의 주변 영역에 유지됨으로써, 쏘잉 보호부로서의 기능을 잃지 않는다.
따라서, 본 발명은 신뢰성 문제를 고려할 필요 없이, 캐리어 기판 상에서 칩과 솔더 볼 사이의 간격을 감소시키는 것을 가능케 한다. 이는, 관련 제품의 더 작은 포장크기(footprint)을 가능케 한다.
바람직한 개선예는 종속 청구항의 대상이다.
바람직한 실시예에 따르면, 제1 솔더 볼은 전방 면에 형성된 각각의 접착 영역 상에 제공된다. 이는 안정성을 증가시킨다.
바람직한 다른 실시예에 따르면, 칩에는 제2 솔더 볼의 제2 복수의 그룹이 제공된다.
바람직한 다른 실시예에 따르면, 디스펜싱 공정에서 충진제의 제공이 수행된다. 이는 비교적 빠른 공정 단계를 가능케 한다. 특히 바람직한 것은 제트 디스펜싱 공정의 이용이다. 이는 규정된 양의 매우 정확한 주입을 가능케 한다.
바람직한 다른 실시예에 따르면, 충진제의 제거를 위한 플라즈마 세정 단계는 애싱을 유도한다. 이는 잔여물이 남지 않는 것을 보장한다.
바람직한 다른 실시예에 따르면, 제1 솔더 볼이 전방 면에서 사전 결정된 간격만큼 칩을 돌출한다. 이는 추가의 실장을 위해 바람직하다.
바람직한 다른 실시예에 따르면, 충진제의 제거를 위한 플라즈마 세정 단계는 분광계를 통해 제어된 종단점(endpoint) 검출에 의해 규정되어 종료된다.
바람직한 다른 실시예에 따르면, 개별화된 칩은 제1 솔더 볼의 각각의 그룹 및 캐리어 기판의 상응하는 영역과 결합되어 회로 기판 상에 납땜된다.
바람직한 다른 실시예에 따르면, 쏘잉 단계에서 개별화가 수행된다.
이하, 본 발명은 도면의 개략적인 도시를 참조하여 기재되는 실시예에서 상세히 설명된다.
도 1a 내지 도 1e는 본 발명에 따른 칩 실장 방법의 실시예의 연속되는 공정 단계의 횡단면도를 도시한다.
도면에서 동일한 도면 부호는 동일하거나 기능이 같은 소자를 나타낸다.
도 1a에서 도면 부호 1은 전방 면(V) 및 후방 면(R)을 갖는 캐리어 기판, 예를 들어 웨이퍼 기판을 나타낸다.
전방 면에서 상응하는 접착 영역(P1, P2, P3, P4) 상에는 제1 솔더 볼(L1, L2 및 L3, L4)의 제1 복수의 그룹이 제공된다.
또한, 도 1b를 참조하면, 플립 칩 방법으로 제2 복수의 칩(C1, C2)이 전방 면(V) 상에 제공되며, 제1 솔더 볼(L1, L2 또는 L3, L4)의 각각 하나의 그룹이 하나의 해당 칩의 주변에 배치된다. 이후에, 솔더 볼(L1, L2 또는 L3, L4)은 회로 기판 상에 실장하기 위해 사용된다.
칩(C1, C2)은 각각 더 작은 제2 그룹의 솔더 볼(S1, S2 또는 S3, S4)을 통해 캐리어 기판(1)의 상응하는 접착 면(PS1, PS2 또는 PS3, PS4) 상에 납땜된다.
도 1a에 따른 공정 상태에서, 솔더 볼(L1, L2, L3, L4)은 실장된 칩(C1, C2)을 통상 50 내지 80㎛ 간격(d1)만큼 돌출하고, 예를 들어 200 내지 250㎛ 높이를 포함한다. 솔더 볼(L1, L2, L3, L4)과 각각의 배치된 칩(C1 또는 T2) 사이의 간격은 도면 부호 d2로 표시되며 통상 50 내지 100㎛를 갖는다.
후속 공정 단계에서, 도 1b에 따르면, 실장된 칩(C1, C2)을 적어도 부분적으로 또는 완전히 충진시키기 위해, 충진제(UF), 예를 들어 에폭시가 전방 측(V)에서 디스펜싱 방법 또는 유사한 방법을 통해 제공된다. 이 경우에, 충진제(UF)는 캐리어 기판(1)으로부터 먼 칩(C1, C2)의 면 상에 그리고 솔더 볼(L1, L2, L3, L4) 상에 침전된다.
또한, 도 1c를 참조하면, 상기 공정에 바로 이어서, 제1 솔더 볼(L1, L2, L3, L4) 및 칩(C1, C2)으로부터 충진제(UF)가 제거되는 플라즈마 애싱 단계(PE)가 수행되며, 칩(C1, C2)이 적어도 부분적으로 충진 상태로 유지됨으로써, 충진제(UF')가 에칭 백 상태로 후속 개별화 공정 및 실장 공정에서 여전히 보호부를 형성한다.
플라즈마 애싱 단계에서, 충진제(UF)의 표면(OF)은 약간 손상되나 매트릭스는 보존된다.
이어서, 도 1d에 따르면, 칩(C1, C2)의 쏘잉 개별화 공정(SV)은 제1 솔더 볼(L1, L2 또는 L3, L4)의 각각의 그룹 및 캐리어 기판(1)의 상응하는 영역(1a, 1b)과 결합되어 수행된다. 이로써, 각각의 전방 면(Va, Vb) 및 각각의 후방 면(Ra, Rb)을 갖는 개별화된 칩(C1, C2)이 형성되며, 이는 후속되는 실장을 위해 개별적으로 사용될 수 있다.
도 1e에 도시된 바와 같이, 후속되는 실장은, 예를 들어 회로 기판(100)의 접착 영역(P10, P20) 상에서 회로 기판에 대한 납땜 과정이다. 도 1e에 따른 공정 상태에서, 회로 기판(100) 상의 솔더 볼(L1, L2)을 통해 칩(C1)을 실장한 후에, 캐리어 기판 영역(1a)으로부터 먼 면과 회로 기판 사이의 간극(SP)이 남는다.
본 발명은 바람직한 실시예를 참조로 전체적으로 설명되었음에도 불구하고, 발명이 상기 실시예로 한정되는 것이 아니라, 다양한 유형 및 방식으로 변형될 수 있다.
특히 기재된 재료 및 기하학적 형상은 예시적인 것으로 보아야 하며 임의로 변경될 수 있다.
Claims (12)
- 칩 실장 방법으로서,
전방 면(V) 및 후방 면(R)을 구비한 캐리어 기판(1)을 제공하는 단계와,
제1 솔더 볼(L1, L2; L3, L4)의 제1 복수의 그룹을 전방 면(V) 상에 제공하는 단계와,
플립 칩 방법으로 전방 면(V) 상에 제2 복수의 칩(C1; C2)을 제공하는 단계로서, 이때 제1 솔더 볼(L1, L2; L3, L4)의 각각 하나의 그룹이, 하나의 해당 칩의 주변에 배치되는 단계와,
칩(C1; C2)을 적어도 부분적으로 충진하기(underfilling) 위해, 전방 면(V) 상에 충진제(UF)를 제공하는 단계로서, 이때 충진제(UF)는 영역에 따라 제1 솔더 볼(L1, L2; L3, L4) 상에 침전되는 단계와,
제1 솔더 볼(L1, L2; L3, L4)로부터 충진제(UF)를 적어도 부분적으로 제거하기 위한 플라즈마 세정 단계를 실행하는 단계로서, 이때 칩(C1; C2)은 적어도 부분적으로 충진 상태로 유지되는 단계와,
제1 솔더 볼(L1, L2; L3, L4)의 각각의 그룹 및 캐리어 기판(1)의 상응하는 영역(1a; 1b)과 결합되어 칩(C1; C2)을 개별화하는 단계를 포함하는 칩 실장 방법. - 제1항에 있어서, 제1 솔더 볼(L1, L2; L3, L4)은 전방 면(V) 상에 각각 형성된 접착 영역(P1 내지 P4) 상에 제공되는 칩 실장 방법.
- 제1항 또는 제2항에 있어서, 칩(C1; C2)은 제2 솔더 볼(S1, S2; S3, S4)의 제2 복수의 그룹과 함께 제공되는 칩 실장 방법.
- 제1항 또는 제2항에 있어서, 충진제(UF)의 제공은 디스펜싱 공정에서 수행되는 칩 실장 방법.
- 제1항 또는 제2항에 있어서, 충진제(UF)의 제공은 제트-디스펜싱 공정에서 수행되는 칩 실장 방법.
- 제1항 또는 제2항에 있어서, 충진제(UF)의 제거를 위한 플라즈마 세정 단계는 애싱(ashing)을 유도하는 칩 실장 방법.
- 제1항 또는 제2항에 있어서, 제1 솔더 볼(L1, L2; L3, L4)은 전방 면(V) 상에서 사전 결정된 간격(d1)만큼 칩(C1; C2)을 돌출하는 칩 실장 방법.
- 제1항 또는 제2항에 있어서, 충진제(UF)의 제거를 위한 플라즈마 세정 단계가 분광계를 통해 제어된 종단점 검출에 의해 규정되어 정지되는 칩 실장 방법.
- 제1항 또는 제2항에 있어서, 개별화된 칩(C1; C2)은 제1 솔더 볼(L1, L2; L3, L4)의 각각의 그룹 및 캐리어 기판(1)의 상응하는 영역(1a; 1b)과 결합되어 회로 기판(100) 상에 납땜되는 칩 실장 방법.
- 제1항 또는 제2항에 있어서, 개별화는 쏘잉(sawing) 공정에서 수행되는 칩 실장 방법.
- 칩 실장체로서,
전방 면(Va; Vb) 및 후방 면(Ra; Rb)을 구비한 캐리어 기판(1)의 영역(1a; 1b)과,
플립 칩 방법으로 전방 면(Va; Vb) 상에 제공된 칩(C1; C2)과,
칩(C1; C2)의 주변에 배치된 제1 솔더 볼(L1, L2; L3, L4)의 그룹과,
칩(C1; C2)을 적어도 부분적으로 충진하는, 전방 면(V) 상의 충진제(UF)를 포함하며,
상기 충진제(UF')는 플라즈마 에칭 표면(OF)을 포함하는 칩 실장체. - 제11항에 있어서, 제1 솔더 볼(L1, L2; L3, L4)의 그룹이 회로 기판(100) 상에 납땜되는 칩 실장체.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102014224548.6A DE102014224548A1 (de) | 2014-12-01 | 2014-12-01 | Chipmontageverfahren und Chipmontageanordnung |
DE102014224548.6 | 2014-12-01 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20160065749A true KR20160065749A (ko) | 2016-06-09 |
KR102447203B1 KR102447203B1 (ko) | 2022-09-26 |
Family
ID=55967828
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020150166626A KR102447203B1 (ko) | 2014-12-01 | 2015-11-26 | 칩 실장 방법 및 칩 실장체 |
Country Status (3)
Country | Link |
---|---|
KR (1) | KR102447203B1 (ko) |
DE (1) | DE102014224548A1 (ko) |
TW (1) | TWI682469B (ko) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102017202023B4 (de) * | 2017-02-09 | 2020-09-03 | Robert Bosch Gmbh | Mikromechanische Sensorvorrichtung mit integrierter Gehäusedichtung, mikromechanische Sensoranordnung und entspechendes Herstellungsverfahren |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007066935A (ja) * | 2005-08-29 | 2007-03-15 | Matsushita Electric Ind Co Ltd | プラズマ処理装置 |
KR20080031644A (ko) * | 2006-10-04 | 2008-04-10 | 신꼬오덴기 고교 가부시키가이샤 | 반도체 디바이스 및 반도체 디바이스의 제조 방법 |
KR20100033932A (ko) * | 2008-09-22 | 2010-03-31 | 쿄세라 에스엘시 테크놀로지 가부시키가이샤 | 배선 기판 및 그 제조 방법 |
JP2010267895A (ja) * | 2009-05-18 | 2010-11-25 | Panasonic Corp | 部品内蔵配線基板の製造方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6753958B2 (en) | 2001-03-22 | 2004-06-22 | Metrophotonics Inc. | Resolution enhanced optical spectrometer having a fixed number of photodetector elements |
DE102005051330B4 (de) | 2005-10-25 | 2015-04-02 | Infineon Technologies Ag | Verfahren zum Herstellen und Reinigen von oberflächenmontierbaren Außenkontaktsockeln |
US9202714B2 (en) * | 2012-04-24 | 2015-12-01 | Micron Technology, Inc. | Methods for forming semiconductor device packages |
US9161712B2 (en) * | 2013-03-26 | 2015-10-20 | Google Inc. | Systems and methods for encapsulating electronics in a mountable device |
-
2014
- 2014-12-01 DE DE102014224548.6A patent/DE102014224548A1/de active Pending
-
2015
- 2015-11-26 KR KR1020150166626A patent/KR102447203B1/ko active IP Right Grant
- 2015-11-30 TW TW104139911A patent/TWI682469B/zh active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007066935A (ja) * | 2005-08-29 | 2007-03-15 | Matsushita Electric Ind Co Ltd | プラズマ処理装置 |
KR20080031644A (ko) * | 2006-10-04 | 2008-04-10 | 신꼬오덴기 고교 가부시키가이샤 | 반도체 디바이스 및 반도체 디바이스의 제조 방법 |
KR20100033932A (ko) * | 2008-09-22 | 2010-03-31 | 쿄세라 에스엘시 테크놀로지 가부시키가이샤 | 배선 기판 및 그 제조 방법 |
JP2010267895A (ja) * | 2009-05-18 | 2010-11-25 | Panasonic Corp | 部品内蔵配線基板の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
KR102447203B1 (ko) | 2022-09-26 |
DE102014224548A1 (de) | 2016-06-02 |
TW201622024A (zh) | 2016-06-16 |
TWI682469B (zh) | 2020-01-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI664668B (zh) | 用於單一化半導體晶圓之方法 | |
TWI659512B (zh) | 半導體裝置以及囊封半導體晶粒的方法 | |
CN105374783B (zh) | 半导体边界保护密封剂 | |
US7833881B2 (en) | Methods for fabricating semiconductor components and packaged semiconductor components | |
US7394152B2 (en) | Wafer level chip size packaged chip device with an N-shape junction inside and method of fabricating the same | |
US9337097B2 (en) | Chip package and method for forming the same | |
US8922013B2 (en) | Through via package | |
US9177919B2 (en) | Chip package and method for forming the same | |
JP6180567B2 (ja) | 応力解放式画像センサパッケージ構造及び方法 | |
US8093102B2 (en) | Process of forming an electronic device including a plurality of singulated die | |
KR101494814B1 (ko) | 팬 아웃 반도체 패키지 및 그 제조 방법 | |
US10643856B2 (en) | Method for fabricating laterally insulated integrated circuit chips | |
TWI503937B (zh) | 晶片封裝體及其形成方法 | |
TW201618245A (zh) | 電子封裝件及其製法 | |
KR102447203B1 (ko) | 칩 실장 방법 및 칩 실장체 | |
KR100927778B1 (ko) | 반도체 패키지 제조 방법 | |
US20160141217A1 (en) | Electronic package and fabrication method thereof | |
US8853859B2 (en) | Passivation for wafer level—chip-scale package devices | |
US20130113084A1 (en) | Semiconductor substrate with molded support layer | |
KR20160108942A (ko) | 반도체 패키지 구조 및 제조 방법 | |
KR20090074500A (ko) | 웨이퍼 레벨 패키지의 제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
AMND | Amendment | ||
E601 | Decision to refuse application | ||
X091 | Application refused [patent] | ||
AMND | Amendment | ||
X701 | Decision to grant (after re-examination) | ||
GRNT | Written decision to grant |