KR20160065749A - 칩 실장 방법 및 칩 실장체 - Google Patents

칩 실장 방법 및 칩 실장체 Download PDF

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KR20160065749A
KR20160065749A KR1020150166626A KR20150166626A KR20160065749A KR 20160065749 A KR20160065749 A KR 20160065749A KR 1020150166626 A KR1020150166626 A KR 1020150166626A KR 20150166626 A KR20150166626 A KR 20150166626A KR 20160065749 A KR20160065749 A KR 20160065749A
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South Korea
Prior art keywords
chip
solder balls
filler
providing
carrier substrate
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KR1020150166626A
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English (en)
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KR102447203B1 (ko
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세바스티안 슐러-바트킨스
랄프 라이혠바흐
한스-페터 배어
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로베르트 보쉬 게엠베하
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Publication of KR20160065749A publication Critical patent/KR20160065749A/ko
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

본 발명은 칩 실장 방법에 관한 것이다. 상기 방법은, 전방 면(V) 및 후방 면(R)을 구비한 캐리어 기판(1)을 제공하는 단계와, 제1 솔더 볼(L1, L2; L3, L4)의 제1 복수의 그룹을 전방 면(V) 상에 제공하는 단계와, 플립 칩 방법으로 제2 복수의 칩(C1; C2)을 전방 면(V) 상에 제공하는 단계로서, 이때 제1 솔더 볼(L1, L2; L3, L4)의 각각 하나의 그룹은, 하나의 해당 칩의 주변에 배치되는 단계와, 칩(C1; C2)을 적어도 부분적으로 충진하기 위해, 전방 면(V) 상에 충진제(UF)를 제공하는 단계로서, 이때 충진제(UF)는 영역에 따라 제1 솔더 볼(L1, L2; L3, L4) 상에 침전되는 단계와, 제1 솔더 볼(L1, L2; L3, L4)로부터 충진제(UF)를 적어도 부분적으로 제거하기 위한 플라즈마 세정 단계를 실행하는 단계로서, 이때 칩(C1; C2)은 적어도 부분적으로 충진 상태로 유지되는 단계와, 제1 솔더 볼(L1, L2; L3, L4)의 각각의 그룹 및 캐리어 기판(1)의 상응하는 영역(1a; 1b)과 결합되어 칩(C1; C2)을 개별화하는 단계를 포함한다.

Description

칩 실장 방법 및 칩 실장체{CHIP MOUNTING METHOD AND CHIP MOUNTING ASSEMBLY}
본 발명은 칩 실장 방법 및 칩 실장체에 관한 것이다.
개별 칩이 플립 칩 방법으로 캐리어 기판 상에 제공되는 칩 실장체는 통상, 향상된 공정 견고성을 달성하기 위해, 납땜 후에 개별 칩이 충진제, 예를 들어 에폭시로 충진되는(underfilling) 방식으로 형성된다. 그 배경에는 칩과 캐리어 기판 사이에 쏘잉(sawing) 잔여물이 도달하는 것이 방지되어야 하는 쏘잉 분리 공정이 있다.
제공된 칩 이외에 솔더 볼이 캐리어 기판 상에 제공되어야 할 경우, 주목해야 할 점은, 이러한 솔더 볼이 칩에 대해 (통상 200㎛보다 큰) 특정 최소 간격을 포함함으로써, 충진제가 솔더 볼을 오염시킬 수 없는데, 이는 후속적인 납땜 공정에 있어서 신뢰성 문제를 나타낼 수도 있다는 것이다.
DE 10 2005 051 330 A1에는 회로 기판용으로 표면 실장 가능한 반도체 칩 제조 방법이 공지되어 있으며, 반도체 웨이퍼는 행과 열로 배치된 반도체 칩 위치에 의해 제공되며, 반도체 칩 위치는, 표면 보호된 전도 경로를 통해 반도체 칩 위치의 반도체 소자 구조와 작용 연결되는 금속 접촉면을 포함한다. 전도성 시드층이 반도체 웨이퍼의 표면 측에 제공되며, 시드층이 접촉면 영역의 노출 하에 절연 보호층에 의해 덮이고, 시드층 상의 외부 접촉 소켓은 자유로이 접근 가능한 접촉면 영역 내로 선택적으로 분리된다. 이어서, 보호층은 플라즈마 애싱 단계에서 이어지는 시드층의 플라즈마 에칭 하에 제거된다.
US 2004/0223696 A1에는 마이크로 볼들을 이용하는 샌드 블래스트 방법으로, 실장된 칩 옆의 측면에서 나오는 충진제를 제거하는 것이 공지되어 있다.
본 발명은 청구항 제1항에 따른 칩 실장 방법 및 청구항 제11항에 따른 칩 실장체를 제공한다.
본 발명은 충진제를 통한 솔더 볼 상의 오염을 후속되는 세정 공정에서 제거하는 사상에 기초한다.
세정 공정으로서, 충진제의 상부 면의 박막층을 제거하나, 충진제의 매트릭스를 파괴하지 않는 짧은 플라즈마 애싱 단계가 제안된다. 이로써, 충진제는 칩의 하부에 또는 칩의 주변 영역에 유지됨으로써, 쏘잉 보호부로서의 기능을 잃지 않는다.
따라서, 본 발명은 신뢰성 문제를 고려할 필요 없이, 캐리어 기판 상에서 칩과 솔더 볼 사이의 간격을 감소시키는 것을 가능케 한다. 이는, 관련 제품의 더 작은 포장크기(footprint)을 가능케 한다.
바람직한 개선예는 종속 청구항의 대상이다.
바람직한 실시예에 따르면, 제1 솔더 볼은 전방 면에 형성된 각각의 접착 영역 상에 제공된다. 이는 안정성을 증가시킨다.
바람직한 다른 실시예에 따르면, 칩에는 제2 솔더 볼의 제2 복수의 그룹이 제공된다.
바람직한 다른 실시예에 따르면, 디스펜싱 공정에서 충진제의 제공이 수행된다. 이는 비교적 빠른 공정 단계를 가능케 한다. 특히 바람직한 것은 제트 디스펜싱 공정의 이용이다. 이는 규정된 양의 매우 정확한 주입을 가능케 한다.
바람직한 다른 실시예에 따르면, 충진제의 제거를 위한 플라즈마 세정 단계는 애싱을 유도한다. 이는 잔여물이 남지 않는 것을 보장한다.
바람직한 다른 실시예에 따르면, 제1 솔더 볼이 전방 면에서 사전 결정된 간격만큼 칩을 돌출한다. 이는 추가의 실장을 위해 바람직하다.
바람직한 다른 실시예에 따르면, 충진제의 제거를 위한 플라즈마 세정 단계는 분광계를 통해 제어된 종단점(endpoint) 검출에 의해 규정되어 종료된다.
바람직한 다른 실시예에 따르면, 개별화된 칩은 제1 솔더 볼의 각각의 그룹 및 캐리어 기판의 상응하는 영역과 결합되어 회로 기판 상에 납땜된다.
바람직한 다른 실시예에 따르면, 쏘잉 단계에서 개별화가 수행된다.
이하, 본 발명은 도면의 개략적인 도시를 참조하여 기재되는 실시예에서 상세히 설명된다.
도 1a 내지 도 1e는 본 발명에 따른 칩 실장 방법의 실시예의 연속되는 공정 단계의 횡단면도를 도시한다.
도면에서 동일한 도면 부호는 동일하거나 기능이 같은 소자를 나타낸다.
도 1a에서 도면 부호 1은 전방 면(V) 및 후방 면(R)을 갖는 캐리어 기판, 예를 들어 웨이퍼 기판을 나타낸다.
전방 면에서 상응하는 접착 영역(P1, P2, P3, P4) 상에는 제1 솔더 볼(L1, L2 및 L3, L4)의 제1 복수의 그룹이 제공된다.
또한, 도 1b를 참조하면, 플립 칩 방법으로 제2 복수의 칩(C1, C2)이 전방 면(V) 상에 제공되며, 제1 솔더 볼(L1, L2 또는 L3, L4)의 각각 하나의 그룹이 하나의 해당 칩의 주변에 배치된다. 이후에, 솔더 볼(L1, L2 또는 L3, L4)은 회로 기판 상에 실장하기 위해 사용된다.
칩(C1, C2)은 각각 더 작은 제2 그룹의 솔더 볼(S1, S2 또는 S3, S4)을 통해 캐리어 기판(1)의 상응하는 접착 면(PS1, PS2 또는 PS3, PS4) 상에 납땜된다.
도 1a에 따른 공정 상태에서, 솔더 볼(L1, L2, L3, L4)은 실장된 칩(C1, C2)을 통상 50 내지 80㎛ 간격(d1)만큼 돌출하고, 예를 들어 200 내지 250㎛ 높이를 포함한다. 솔더 볼(L1, L2, L3, L4)과 각각의 배치된 칩(C1 또는 T2) 사이의 간격은 도면 부호 d2로 표시되며 통상 50 내지 100㎛를 갖는다.
후속 공정 단계에서, 도 1b에 따르면, 실장된 칩(C1, C2)을 적어도 부분적으로 또는 완전히 충진시키기 위해, 충진제(UF), 예를 들어 에폭시가 전방 측(V)에서 디스펜싱 방법 또는 유사한 방법을 통해 제공된다. 이 경우에, 충진제(UF)는 캐리어 기판(1)으로부터 먼 칩(C1, C2)의 면 상에 그리고 솔더 볼(L1, L2, L3, L4) 상에 침전된다.
또한, 도 1c를 참조하면, 상기 공정에 바로 이어서, 제1 솔더 볼(L1, L2, L3, L4) 및 칩(C1, C2)으로부터 충진제(UF)가 제거되는 플라즈마 애싱 단계(PE)가 수행되며, 칩(C1, C2)이 적어도 부분적으로 충진 상태로 유지됨으로써, 충진제(UF')가 에칭 백 상태로 후속 개별화 공정 및 실장 공정에서 여전히 보호부를 형성한다.
플라즈마 애싱 단계에서, 충진제(UF)의 표면(OF)은 약간 손상되나 매트릭스는 보존된다.
이어서, 도 1d에 따르면, 칩(C1, C2)의 쏘잉 개별화 공정(SV)은 제1 솔더 볼(L1, L2 또는 L3, L4)의 각각의 그룹 및 캐리어 기판(1)의 상응하는 영역(1a, 1b)과 결합되어 수행된다. 이로써, 각각의 전방 면(Va, Vb) 및 각각의 후방 면(Ra, Rb)을 갖는 개별화된 칩(C1, C2)이 형성되며, 이는 후속되는 실장을 위해 개별적으로 사용될 수 있다.
도 1e에 도시된 바와 같이, 후속되는 실장은, 예를 들어 회로 기판(100)의 접착 영역(P10, P20) 상에서 회로 기판에 대한 납땜 과정이다. 도 1e에 따른 공정 상태에서, 회로 기판(100) 상의 솔더 볼(L1, L2)을 통해 칩(C1)을 실장한 후에, 캐리어 기판 영역(1a)으로부터 먼 면과 회로 기판 사이의 간극(SP)이 남는다.
본 발명은 바람직한 실시예를 참조로 전체적으로 설명되었음에도 불구하고, 발명이 상기 실시예로 한정되는 것이 아니라, 다양한 유형 및 방식으로 변형될 수 있다.
특히 기재된 재료 및 기하학적 형상은 예시적인 것으로 보아야 하며 임의로 변경될 수 있다.

Claims (12)

  1. 칩 실장 방법으로서,
    전방 면(V) 및 후방 면(R)을 구비한 캐리어 기판(1)을 제공하는 단계와,
    제1 솔더 볼(L1, L2; L3, L4)의 제1 복수의 그룹을 전방 면(V) 상에 제공하는 단계와,
    플립 칩 방법으로 전방 면(V) 상에 제2 복수의 칩(C1; C2)을 제공하는 단계로서, 이때 제1 솔더 볼(L1, L2; L3, L4)의 각각 하나의 그룹이, 하나의 해당 칩의 주변에 배치되는 단계와,
    칩(C1; C2)을 적어도 부분적으로 충진하기(underfilling) 위해, 전방 면(V) 상에 충진제(UF)를 제공하는 단계로서, 이때 충진제(UF)는 영역에 따라 제1 솔더 볼(L1, L2; L3, L4) 상에 침전되는 단계와,
    제1 솔더 볼(L1, L2; L3, L4)로부터 충진제(UF)를 적어도 부분적으로 제거하기 위한 플라즈마 세정 단계를 실행하는 단계로서, 이때 칩(C1; C2)은 적어도 부분적으로 충진 상태로 유지되는 단계와,
    제1 솔더 볼(L1, L2; L3, L4)의 각각의 그룹 및 캐리어 기판(1)의 상응하는 영역(1a; 1b)과 결합되어 칩(C1; C2)을 개별화하는 단계를 포함하는 칩 실장 방법.
  2. 제1항에 있어서, 제1 솔더 볼(L1, L2; L3, L4)은 전방 면(V) 상에 각각 형성된 접착 영역(P1 내지 P4) 상에 제공되는 칩 실장 방법.
  3. 제1항 또는 제2항에 있어서, 칩(C1; C2)은 제2 솔더 볼(S1, S2; S3, S4)의 제2 복수의 그룹과 함께 제공되는 칩 실장 방법.
  4. 제1항 또는 제2항에 있어서, 충진제(UF)의 제공은 디스펜싱 공정에서 수행되는 칩 실장 방법.
  5. 제1항 또는 제2항에 있어서, 충진제(UF)의 제공은 제트-디스펜싱 공정에서 수행되는 칩 실장 방법.
  6. 제1항 또는 제2항에 있어서, 충진제(UF)의 제거를 위한 플라즈마 세정 단계는 애싱(ashing)을 유도하는 칩 실장 방법.
  7. 제1항 또는 제2항에 있어서, 제1 솔더 볼(L1, L2; L3, L4)은 전방 면(V) 상에서 사전 결정된 간격(d1)만큼 칩(C1; C2)을 돌출하는 칩 실장 방법.
  8. 제1항 또는 제2항에 있어서, 충진제(UF)의 제거를 위한 플라즈마 세정 단계가 분광계를 통해 제어된 종단점 검출에 의해 규정되어 정지되는 칩 실장 방법.
  9. 제1항 또는 제2항에 있어서, 개별화된 칩(C1; C2)은 제1 솔더 볼(L1, L2; L3, L4)의 각각의 그룹 및 캐리어 기판(1)의 상응하는 영역(1a; 1b)과 결합되어 회로 기판(100) 상에 납땜되는 칩 실장 방법.
  10. 제1항 또는 제2항에 있어서, 개별화는 쏘잉(sawing) 공정에서 수행되는 칩 실장 방법.
  11. 칩 실장체로서,
    전방 면(Va; Vb) 및 후방 면(Ra; Rb)을 구비한 캐리어 기판(1)의 영역(1a; 1b)과,
    플립 칩 방법으로 전방 면(Va; Vb) 상에 제공된 칩(C1; C2)과,
    칩(C1; C2)의 주변에 배치된 제1 솔더 볼(L1, L2; L3, L4)의 그룹과,
    칩(C1; C2)을 적어도 부분적으로 충진하는, 전방 면(V) 상의 충진제(UF)를 포함하며,
    상기 충진제(UF')는 플라즈마 에칭 표면(OF)을 포함하는 칩 실장체.
  12. 제11항에 있어서, 제1 솔더 볼(L1, L2; L3, L4)의 그룹이 회로 기판(100) 상에 납땜되는 칩 실장체.
KR1020150166626A 2014-12-01 2015-11-26 칩 실장 방법 및 칩 실장체 KR102447203B1 (ko)

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