TW201618300A - 碳化矽場效電晶體 - Google Patents

碳化矽場效電晶體 Download PDF

Info

Publication number
TW201618300A
TW201618300A TW103138027A TW103138027A TW201618300A TW 201618300 A TW201618300 A TW 201618300A TW 103138027 A TW103138027 A TW 103138027A TW 103138027 A TW103138027 A TW 103138027A TW 201618300 A TW201618300 A TW 201618300A
Authority
TW
Taiwan
Prior art keywords
doped
type
effect transistor
field effect
layer
Prior art date
Application number
TW103138027A
Other languages
English (en)
Other versions
TWI559534B (zh
Inventor
Chien-Chung Hung
Cheng-Tyng Yen
Hsiang-Ting Hung
Chwan-Ying Lee
Original Assignee
Hestia Power Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hestia Power Inc filed Critical Hestia Power Inc
Priority to TW103138027A priority Critical patent/TWI559534B/zh
Priority to US14/591,470 priority patent/US9685552B2/en
Publication of TW201618300A publication Critical patent/TW201618300A/zh
Application granted granted Critical
Publication of TWI559534B publication Critical patent/TWI559534B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
    • H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H01L29/086—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H01L29/0865—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Composite Materials (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

一種碳化矽場效電晶體，包含有一碳化矽基板、一n型漂移層、一p型磊晶層、一源極區域、一溝槽式閘極、至少一p型摻雜區域、一源極、一介電層以及一汲極。藉由設置該p型摻雜區域位於該n型漂移層而相鄰於該溝槽式閘極的一側邊，並令該p型摻雜區域包含一與該p型磊晶層接觸的第一摻雜區塊以及複數個從該第一摻雜區塊朝向該碳化矽基板而間隔排列的第二摻雜區塊，使該第二摻雜區塊的厚度不需超過2um，不僅避免受限於離子佈植的深度的問題，亦能有效降低該溝槽式閘極的一底部與一轉角處的電場，提高該碳化矽場效電晶體的可靠度。

Description

碳化矽場效電晶體
本發明有關一種半導體元件，尤指一種碳化矽場效電晶體。
半導體功率元件在特性上，要求在設計的耐壓 (breakdown voltage)，應具備盡量小的導通電阻、低反向漏電流、以及較快的開關速度，以減少操作時的導通損耗(conduction loss)及切換損耗(switching loss)。而碳化矽(silicon carbide，SiC)由於具有寬能隙 (bandgap Eg=3.26eV)、高臨界崩潰電場強度(2.2MV/cm)及高熱導係數(4.9W/cm-K)等特性，被認為是功率開關元件的極佳材料，使得許多相關業者，皆致力於碳化矽功率元件的研究。 例如在美國發明專利公開第US2013161736號中，即揭示一種溝槽式金氧半導體電晶體元件及其製造方法，其中該溝槽式金氧半導體電晶體元件包括一第一型基材、一第一型漂移區、一第二型深溝槽摻雜區、一第二型磊晶區、一溝槽式閘極、一閘極絕緣層、一源極區、一汲極電極以及一源極電極。該第一型漂移區中具有至少一深溝槽，且該第二型深溝槽摻雜區位於該深溝槽內。該溝槽式閘極貫穿該第二型磊晶區，且該溝槽式閘極之底部與該第二型深溝槽摻雜區之底部之間的距離為0.5～3微米。據此當該溝槽式金氧半導體電晶體元件在反向耐壓操作時，可有效分散電力線分佈，進而提高元件的可靠度。 然而，上述的該溝槽式金氧半導體電晶體元件，由於該第二型深溝槽摻雜區的摻雜深度必需受限於離子佈植的能量以及硬式遮罩層的厚度。一般而言，具有大能量而能夠一次佈植超過2um之深度的離子佈植設備並不常見，使得該溝槽式金氧半導體電晶體元件的發展以及耐壓的能力仍然有改善的空間。
本發明的主要目的，在於解決習知的一溝槽式金氧半導體電晶體元件，為了有效分散電力線以降低一閘極的一底部與一轉角處的電場，設置有一深溝槽摻雜區，但是該深溝槽摻雜區的摻雜深度卻受限於離子佈植的能量以及硬式遮罩層的厚度的問題。 為達上述目的，本發明提供一種碳化矽場效電晶體，包含有一碳化矽基板、一n型漂移層、一p型磊晶層、一源極區域、一溝槽式閘極、至少一p型摻雜區域、一源極、一介電層以及一汲極。 該n型漂移層設置於該碳化矽基板上；該p型磊晶層設置於該n型漂移層上；該源極區域形成於該p型磊晶層並遠離該n型漂移層；該溝槽式閘極貫穿該p型磊晶層而延伸至該n型漂移層；該p型摻雜區域形成於該n型漂移層而相鄰於該溝槽式閘極的一側邊；該源極覆蓋該源極區域與該溝槽式閘極；該介電層設置於該溝槽式閘極與該源極之間；而該汲極設置於該碳化矽基板而遠離該n型漂移層。 其中，該p型摻雜區域包含一與該p型磊晶層接觸的第一摻雜區塊以及複數個從該第一摻雜區塊朝向該碳化矽基板而間隔排列的第二摻雜區塊。  如此一來，本發明藉由於該n型漂移層內設置從該第一摻雜區塊朝向該碳化矽基板而間隔排列的該第二摻雜區塊，由於該第二摻雜區塊的厚度不需超過2um，不僅避免受限於離子佈植的能量以及硬式遮罩層的厚度的問題，亦能有效分散電力線以降低該溝槽式閘極的一底部與一轉角處的電場，提高該碳化矽場效電晶體的可靠度。
有關本發明的詳細說明及技術內容，現就配合圖式說明如下： 請參閱『圖1』所示，為本發明第一實施例的結構示意圖，本發明提供一種碳化矽場效電晶體，包含有一碳化矽基板10、一n型漂移層20、一p型磊晶層30、一源極區域40、一溝槽式閘極50、至少一p型摻雜區域60、一源極70、一介電層80以及一汲極90。 該碳化矽基板10在此可藉由將碳化矽結晶切割為特定之厚度而得，亦可使用市售之碳化矽基板10，亦可將碳化矽結晶生長於任一基板上而得，只要具有由碳化矽結晶而成之表面的基板，並不加以特別限制，該碳化矽基板10具有n型重摻雜，摻雜濃度為介於1E18 cm-3 至5E19 cm-3 之間，並具有一頂面11以及一相對遠離該頂面11的底面12。 該n型漂移層20設置於該碳化矽基板10上，而位於該頂面11，在此為使用磊晶技術成長而成，其摻雜材質可為氮或磷，摻雜濃度為介於1E15 cm-3 至1E19 cm-3 之間，該n型漂移層20包含有一第一磊晶層21以及複數個第二磊晶層22，該第一磊晶層21遠離該碳化矽基板10，具有一第一上表面211，該第二磊晶層22位於該第一磊晶層21與該碳化矽基板10之間而層疊，並各自具有一第二上表面221。該p型磊晶層30設置於該n型漂移層20上，而與該第一磊晶層21接觸，其摻雜材質可為鋁或硼，而摻雜濃度為介於1E16 cm-3 至1E19 cm-3 之間。 該溝槽式閘極50貫穿該p型磊晶層30而延伸至該n型漂移層20內，包含有一閘電極51以及一閘極絕緣層52，該閘電極51可使用複晶材料製成，例如為多晶矽(Poly-Silicon)，該閘極絕緣層52則設置於該閘電極51與該p型磊晶層30及該n型漂移層20之間，使該閘電極51與該p型磊晶層30及該n型漂移層20之間間隔而電性絕緣。 該源極區域40形成於該p型磊晶層30遠離該n型漂移層20的一側，包含有一第一源極區41以及一第二源極區42，該第一源極區41與該第二源極區42為相鄰設置，可採用離子佈植的方式形成，在本實施例中，該第一源極區41為n型重摻雜，該第二源極區42為p型重摻雜，該溝槽式閘極50於貫穿該p型磊晶層30時，同時穿過該第一源極區41。 該源極70覆蓋該源極區域40與該溝槽式閘極50，該汲極90設置於該碳化矽基板10遠離該n型漂移層20的一側，而位於該底面12，該源極70與該汲極90各可包含一歐姆接觸層以及一用以電連接的金屬層，該歐姆接觸層的材質例如可為鎳、鈦等可形成歐姆接觸的材質，該金屬層的材質則可為銅、鋁、金等金屬。而該介電層80設置於該溝槽式閘極50與該源極70之間，以令該源極70與該溝槽式閘極50之間電性絕緣。 至於該p型摻雜區域60，為形成於該n型漂移層20內而相鄰於該溝槽式閘極50的一側邊，重要的是，該p型摻雜區域60包含一第一摻雜區塊61以及複數個第二摻雜區塊62，該第一摻雜區塊61為對應設置於該第一磊晶層21內而與該p型磊晶層30接觸，可於該第一磊晶層21磊晶成長後，以離子佈植的方式形成，使該第一摻雜區塊61為從該第一上表面211朝下延伸分布；而該第二摻雜區塊62為從該第一摻雜區塊61朝向該碳化矽基板10而間隔排列，而各自單一對應設置於該第二磊晶層22內，可於各該第二磊晶層22磊晶成長後，以離子佈植的方式形成，使該第二摻雜區塊62各自從對應的該第二磊晶層22的該第二上表面221朝下延伸分布。 在本實施例中，該p型摻雜區域60有兩個，分別相鄰於該溝槽式閘極50相對的兩個該側邊，所形成的該第一摻雜區塊61，可具有一介於1um至4um之間的第一厚度，一介於5E17cm-3 至5E19cm-3 的第一摻雜濃度，該第二摻雜區塊62可具有一具介於0.5um至1.5um之間的第二厚度，一介於1E16cm-3 至2E18cm-3 的第二摻雜濃度，而該第二摻雜區塊62與該第一摻雜區塊61之間具有一介於0.3um至1.5um之間的第一間距，該第二摻雜區塊62彼此之間具有一介於0.3um至1.5um之間的第二間距，不過本發明並不以上述條件為限制，可依據實際使用需求調整。再者，要說明的是，該第一厚度與該第二厚度可藉由調變離子佈植的一能量調整控制，該能量一般為介於50KeV至1.5MeV之間，該第一摻雜濃度與該第二摻雜濃度可藉由調變離子佈植的一劑量調整控制，該劑量可介於1E12cm-2 至1E15cm-2 之間，至於該第一間距與該第二間距，則各別視該第一磊晶層21該第二磊晶層22厚度，扣除各所對應設置的該第一摻雜區塊61與該第二摻雜區塊62所形成的該第一厚度與該第二度厚而形成。 請參閱『圖2』所示，為本發明第二實施例的結構示意圖，在第二實施例中，與第一實施例相較，其特徵在於該p型摻雜區域60還包含一重摻雜區塊63，該重摻雜區塊63設置於該第一摻雜區塊61與該第二摻雜區塊62之間，而與該第一摻雜區塊61連接，並具有一大於該第一摻雜區塊61與該第二摻雜區塊62的重摻雜濃度，該重摻雜濃度為介於1E18 cm-3 至5E19 cm-3 之間。而為了形成該重摻雜區塊63，在第二實施例中，為在該第一磊晶層21中形成該第一摻雜區塊61之前，先形成一對應該第一摻雜區塊61的一寬度的溝槽，並於該溝槽周圍先形成一側邊間隙壁64，該側邊間隙壁64的材質可為氧化矽、氮化矽或是其他的絕緣材料，之後再以離子佈植的方式於該溝槽的底部形成該重摻雜區塊63，再於該構槽的位置形成該第一摻雜區塊61。 綜上所述，本發明藉由於該n型漂移層內設置從該第一摻雜區塊朝向該碳化矽基板而間隔排列的該第二摻雜區塊，並令該第二摻雜區塊的厚度不需超過2um，不僅避免摻雜的深度受限於離子佈植的能量以及硬式遮罩層的問題，亦能有效分散電力線以降低該溝槽式閘極的一底部與一轉角處的電場，提高該碳化矽場效電晶體的可靠度，再者，本發明還可藉由該側邊間隙壁設置該重摻雜區塊，使該碳化矽場效電晶體在導通時電流可以較容易向側向流，而降低開啟時的電阻值，因此本發明極具進步性及符合申請發明專利的要件，爰依法提出申請，祈  鈞局早日賜准專利，實感德便。 以上已將本發明做一詳細說明，惟以上所述者，僅爲本發明的一較佳實施例而已，當不能限定本發明實施的範圍。即凡依本發明申請範圍所作的均等變化與修飾等，皆應仍屬本發明的專利涵蓋範圍內。
10‧‧‧碳化矽基板
11‧‧‧頂面
12‧‧‧底面
20‧‧‧n型漂移層
21‧‧‧第一磊晶層
211‧‧‧第一上表面
22‧‧‧第二磊晶層
221‧‧‧第二上表面
30‧‧‧p型磊晶層
40‧‧‧源極區域
41‧‧‧第一源極區
42‧‧‧第二源極區
50‧‧‧溝槽式閘極
51‧‧‧閘電極
52‧‧‧閘極絕緣層
60‧‧‧p型摻雜區域
61‧‧‧第一摻雜區塊
62‧‧‧第二摻雜區塊
63‧‧‧重摻雜區塊
64‧‧‧側邊間隙壁
70‧‧‧源極
80‧‧‧介電層
90‧‧‧汲極
圖1，為本發明第一實施例的結構示意圖。 圖2，為本發明第二實施例的結構示意圖。
10‧‧‧碳化矽基板
11‧‧‧頂面
12‧‧‧底面
20‧‧‧n型漂移層
21‧‧‧第一磊晶層
211‧‧‧第一上表面
22‧‧‧第二磊晶層
221‧‧‧第二上表面
30‧‧‧p型磊晶層
40‧‧‧源極區域
41‧‧‧第一源極區
42‧‧‧第二源極區
50‧‧‧溝槽式閘極
51‧‧‧閘電極
52‧‧‧閘極絕緣層
60‧‧‧p型摻雜區域
61‧‧‧第一摻雜區塊
62‧‧‧第二摻雜區塊
70‧‧‧源極
80‧‧‧介電層
90‧‧‧汲極

Claims (14)

  1. 一種碳化矽場效電晶體，包含有： 一碳化矽基板； 一設置於該碳化矽基板上的n型漂移層； 一設置於該n型漂移層上的p型磊晶層； 一形成於該p型磊晶層並遠離該n型漂移層的源極區域； 一貫穿該p型磊晶層而延伸至該n型漂移層的溝槽式閘極； 至少一形成於該n型漂移層而相鄰於該溝槽式閘極的一側邊的p型摻雜區域； 一覆蓋該源極區域與該溝槽式閘極的源極； 一設置於該溝槽式閘極與該源極之間的介電層；以及 一設置於該碳化矽基板而遠離該n型漂移層的汲極； 其中，該p型摻雜區域包含一與該p型磊晶層接觸的第一摻雜區塊以及複數個從該第一摻雜區塊朝向該碳化矽基板而間隔排列的第二摻雜區塊。
  2. 如申請專利範圍第1項所述的碳化矽場效電晶體，其中該第一摻雜區塊具有一大於該第二摻雜區塊的厚度。
  3. 如申請專利範圍第1項所述的碳化矽場效電晶體，其中該第一摻雜區塊具有一介於1um至4um之間的第一厚度。
  4. 如申請專利範圍第1項所述的碳化矽場效電晶體，其中該第二摻雜區塊具有一介於0.5um至1.5um之間的第二厚度。
  5. 如申請專利範圍第1項所述的碳化矽場效電晶體，其中該第二摻雜區塊與該第一摻雜區塊之間具有一介於0.3um至1.5um之間的第一間距。
  6. 如申請專利範圍第1項所述的碳化矽場效電晶體，其中該第二摻雜區塊彼此之間具有一介於0.3um至1.5um之間的第二間距。
  7. 如申請專利範圍第1項所述的碳化矽場效電晶體，其中該n型漂移層包含複數個層疊的第二磊晶層以及一設置於該第二磊晶層與該p型磊晶層之間的第一磊晶層，該第一摻雜區塊形成於該第一磊晶層內，該第二摻雜區塊各自單一對應形成於該第二磊晶層內。
  8. 如申請專利範圍第7項所述的碳化矽場效電晶體，其中該第一磊晶層具有一第一上表面，該第一摻雜區塊從該第一上表面朝下延伸分布。
  9. 如申請專利範圍第7項所述的碳化矽場效電晶體，其中該第二磊晶層各自具有一第二上表面，該第二摻雜區塊各自於所對應的該第二磊晶層內從該第二上表面朝下延伸分布。
  10. 如申請專利範圍第1項所述的碳化矽場效電晶體，其中該第一摻雜區塊具有一介於5E17cm-3 至5E19cm-3 的第一摻雜濃度。
  11. 如申請專利範圍第1項所述的碳化矽場效電晶體，其中該第二摻雜區塊具有一介於1E16cm-3 至2E18cm-3 的第二摻雜濃度。
  12. 如申請專利範圍第1項所述的碳化矽場效電晶體，其中該p型摻雜區域有兩個，分別相鄰於該溝槽式閘極相對的兩個該側邊。
  13. 如申請專利範圍第1項所述的碳化矽場效電晶體，其中該p型摻雜區域還包含一設置於該第一摻雜區塊與該第二摻雜區塊之間，而與該第一摻雜區域連接的重摻雜區塊。
  14. 如申請專利範圍第1項所述的碳化矽場效電晶體，其中該溝槽式閘極包含一閘電極以及一介於該閘電極與該p型磊晶層及該n型漂移層之間的閘極絕緣層。
TW103138027A 2014-11-03 2014-11-03 Silicon carbide field effect transistor TWI559534B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW103138027A TWI559534B (zh) 2014-11-03 2014-11-03 Silicon carbide field effect transistor
US14/591,470 US9685552B2 (en) 2014-11-03 2015-01-07 Silicon carbide field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW103138027A TWI559534B (zh) 2014-11-03 2014-11-03 Silicon carbide field effect transistor

Publications (2)

Publication Number Publication Date
TW201618300A true TW201618300A (zh) 2016-05-16
TWI559534B TWI559534B (zh) 2016-11-21

Family

ID=55853584

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103138027A TWI559534B (zh) 2014-11-03 2014-11-03 Silicon carbide field effect transistor

Country Status (2)

Country Link
US (1) US9685552B2 (zh)
TW (1) TWI559534B (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017214627A1 (en) * 2016-06-10 2017-12-14 Maxpower Semiconductor, Inc. Fabrication of trench-gated wide-bandgap devices
JP6981890B2 (ja) * 2018-01-29 2021-12-17 ルネサスエレクトロニクス株式会社 半導体装置
CN109904220A (zh) * 2019-03-18 2019-06-18 电子科技大学 槽栅型碳化硅mosfet器件及制备方法
CN113808943A (zh) * 2020-06-12 2021-12-17 芯恩（青岛）集成电路有限公司 超结功率器件及其制备方法
CN115148826B (zh) * 2022-09-06 2023-01-06 深圳平创半导体有限公司 一种深沟槽碳化硅jfet结构的制作方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4830213B2 (ja) * 2001-05-08 2011-12-07 株式会社デンソー 炭化珪素半導体装置及びその製造方法
JP4604241B2 (ja) * 2004-11-18 2011-01-05 独立行政法人産業技術総合研究所 炭化ケイ素ｍｏｓ電界効果トランジスタおよびその製造方法
US7687851B2 (en) * 2005-11-23 2010-03-30 M-Mos Semiconductor Sdn. Bhd. High density trench MOSFET with reduced on-resistance
US20080197381A1 (en) * 2007-02-15 2008-08-21 Nec Electronics Corporation Semiconductor device and method for manufacturing same
JP4798119B2 (ja) * 2007-11-06 2011-10-19 株式会社デンソー 炭化珪素半導体装置およびその製造方法
JP4640439B2 (ja) * 2008-04-17 2011-03-02 株式会社デンソー 炭化珪素半導体装置
IT1401754B1 (it) * 2010-08-30 2013-08-02 St Microelectronics Srl Dispositivo elettronico integrato e relativo metodo di fabbricazione.
JP5310687B2 (ja) * 2010-09-30 2013-10-09 株式会社デンソー 接合型電界効果トランジスタを備えた半導体装置およびその製造方法
TWI470802B (zh) * 2011-12-21 2015-01-21 Ind Tech Res Inst 溝槽式金氧半導體電晶體元件及其製造方法
TWI587503B (zh) * 2012-01-11 2017-06-11 世界先進積體電路股份有限公司 半導體裝置及其製造方法

Also Published As

Publication number Publication date
US9685552B2 (en) 2017-06-20
US20160126346A1 (en) 2016-05-05
TWI559534B (zh) 2016-11-21

Similar Documents

Publication Publication Date Title
JP6320545B2 (ja) 半導体装置
JP6367760B2 (ja) 絶縁ゲート型スイッチング装置とその製造方法
US8704292B2 (en) Vertical capacitive depletion field effect transistor
WO2014196164A1 (ja) 炭化珪素半導体装置およびその製造方法
JP5790573B2 (ja) 炭化珪素半導体装置およびその製造方法
JP6099749B2 (ja) 炭化珪素半導体装置およびその製造方法
TWI559534B (zh) Silicon carbide field effect transistor
JP6740986B2 (ja) 炭化珪素半導体装置およびその製造方法
JP6214680B2 (ja) 炭化珪素半導体装置
JP2015041719A (ja) ワイドバンドギャップ絶縁ゲート型半導体装置
JP6802454B2 (ja) 半導体装置およびその製造方法
JP7432071B2 (ja) 半導体装置およびその製造方法
TWI590450B (zh) Semiconductor device
TWI470802B (zh) 溝槽式金氧半導體電晶體元件及其製造方法
TW201541639A (zh) 半導體裝置
TW201222828A (en) ACCUFET with integrated clamping circuit and manufacturing method thereof
JP2014170886A (ja) 半導体装置及びその製造方法
JP2015133447A (ja) 半導体装置
TWI805267B (zh) 溝渠式閘極電晶體元件
JP6318721B2 (ja) 半導体装置および半導体装置の製造方法
KR20200010188A (ko) 탄화규소 mosfet 단세포 구조의 제조방법
CN113113464B (zh) 一种半导体器件及其制造方法
CN105655394B (zh) 碳化硅场效晶体管
KR101776319B1 (ko) 반도체 소자
CN113140634A (zh) 一种半导体器件及其制造方法