TWI805267B - 溝渠式閘極電晶體元件 - Google Patents

溝渠式閘極電晶體元件 Download PDF

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TWI805267B
TWI805267B TW111108970A TW111108970A TWI805267B TW I805267 B TWI805267 B TW I805267B TW 111108970 A TW111108970 A TW 111108970A TW 111108970 A TW111108970 A TW 111108970A TW I805267 B TWI805267 B TW I805267B
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trench
gate
region
along
doped
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TW202337030A (zh
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李柏賢
曾婉雯
王誠駿
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力源半導體股份有限公司
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Priority to US17/891,904 priority patent/US20230290815A1/en
Priority to CN202310224487.0A priority patent/CN116741828A/zh
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Abstract

一種溝渠式閘極電晶體元件，包含一基板及形成於該基板上的電晶體。 該電晶體包括一整流區、至少一主動部，及多個超級接面。該整流區具有至少一由蕭特基二極體(Schottky diode)構成的整流結構。其中，該至少一主動部位於該整流區沿一第一方向的其中至少一側邊，該至少一主動部與該至少一整流結構沿該第一方向排列分佈，且該等超級接面結構沿一與該第一方向相交之第二方向分佈。

Description

溝渠式閘極電晶體元件
本發明是有關於一種半導體元件，特別是指一種溝渠式閘極電晶體元件。
隨著半導體功率元件朝向高功率、高頻、高耐熱及低功耗等新興應用的要求下，傳統的矽基功率元件已逐漸難以滿足此等性能需求。因此，具有寬能隙(WBG)、高電子遷移率、高導熱及低阻抗的碳化矽(SiC)於近年來備受矚目。其中，以碳化矽為材料的溝渠式閘極金氧半場效電晶體(Trench Gate Power MOSFET)，由於可藉由溝渠降低導通電阻(on-state resistance)及改善電晶體的終端邊緣特性(edge termination characteristics)，使得溝渠式閘極金氧半場效電晶體成為高頻低壓功率元件的主流。
以垂直式N型通道溝渠式金氧半場效電晶體(MOSFET)為例，為了增加該溝渠式MOFET的擊穿電壓並降低導通電阻，一般可透過增加閘極長度降低導通電阻或是增加N型漂移區的離子摻雜濃度等方式。而為了進一步提升元件的崩潰電壓及降低導通電阻，則有將用於承受跨壓的N型漂移區改成具有高濃度摻雜且摻雜載子相異P/N型柱狀摻雜區，令原本的N型漂移區形成P/N超級接面(PN super junction)以提高元件的特性，並可利用調整P/N柱狀摻雜區之間的寬度(pitch)，透過增加溝渠密度，改善通道的阻抗及達到不同的崩潰電壓。然而，因為一般的P/N超級接面與元件的通道層是以同一方向延伸分佈，因此溝渠密度會被同向並已預先規畫好的P柱所限制，因此並無法隨意調整。
因此，本發明的目的，即在於藉由電晶體的結構設計，提供一種具有多個超級接面，且該等超級接面的分佈方向與主動部的分佈方向彼此正交的溝渠式閘極電晶體元件。
於是，本發明的溝渠式閘極電晶體元件，包含一基板及形成於該基板上的電晶體。
該電晶體包括，一整流區、至少一主動部，及多個超級接面。
該整流區具有至少一由蕭特基二極體(Schottky diode)構成的整流結構。
該至少一主動部位於該整流區沿一第二方向的其中至少一側邊，且與該至少一整流結構沿該第二方向排列分佈。
該等超級接面沿一與該第二方向相交之第一方向分佈。
本發明的功效在於：藉由結構設計，讓電晶體的主動部與整流結構沿一第二方向排列，並令結構中的超級接面沿一與該第二方向相交之第一方向分佈，讓超級接面與主動部及整流結構的分佈方向彼此相交，而形成3D分佈的主動部及超級接面，而可避免習知以同方向(共平面)方向分佈的主動部及超級接面彼此相互影響的缺點，以令元件結構可具有較大的調整彈性。
在本發明被詳細描述之前，應當注意在以下的說明內容中，類似的元件是以相同的編號來表示。
配合參閱圖1~4，本發明溝渠式閘極電晶體元件的一實施例，包含一基板2、一汲極電極3、一電晶體4、一介電絕緣層5，及一導電單元6。其中，圖1是一立體圖，其省略了位於該電晶體4上方的該介電絕緣層5及該導電單元6；圖2-4為分別沿圖1的II-II、III-III、IV-IV割線位置的剖視示意圖，該等剖視圖則包含位於該電晶體4上方的該介電絕緣層5及該導電單元6。
該基板2由碳化矽構成並具有高濃度的第一型摻雜。
該汲極電極3形成於該基板2的其中一表面，且與該基板2成歐姆接觸。
該電晶體4是一由半導體材料構成的磊晶積層，該磊晶積層形成於該基板2反向該汲極電極3的表面，包括一整流區RA、多個主動部A，及多個超級接面SJ。該整流區RA具有至少一由蕭特基二極體構成的整流結構SD，該等主動部A位於該整流區RA沿一第二方向Y的相對兩側邊，其中，該等主動部A與該整流結構SD沿該第二方向Y排列分佈，且該等超級接面SJ沿一與該第二方向Y相交之第一方向X分佈。
詳細的說，該電晶體4包括形成於該基板2上，具有第一型摻雜且摻雜濃度小於該基板2的一第一摻雜區41、一位於該第一摻雜區41頂面並具有第二型摻雜的井區42、自該井區42頂面向下至與該第一摻雜區41連接的第二摻雜區43，及多條自該井區42的頂面向下延伸至該第一摻雜區41，並沿該第二方向Y延伸成長條柱狀的第三摻雜區44，且該等第三摻雜區44沿該第一方向X平行間隔排列。其中，該第一摻雜區41及該第二摻雜區43為同型摻雜且具有相同摻雜濃度；該井區42與該等第三摻雜區44為同型摻雜，且該井區312的摻雜濃度大於該等第三摻雜區44。
要說明的是，前述該第一型摻雜是第一導電型態摻雜，該第二型摻雜則為與該第一導電型態摻雜的電性相反的第二導電型態摻雜。例如，該第一型摻雜為N型摻雜，該第二型摻雜則為P型摻雜，反之則反。本發明的溝渠式閘極電晶體元件可為NMOS，亦可為PMOS，並無特別限制。於本實施例中，是以該第一型摻雜為N型摻雜，該第二型摻雜為P型摻雜為例；該基板2為N型摻雜碳化矽；該第一摻雜區41及該第三摻雜區是N型摻雜碳化矽、該井區42與該等第三摻雜區44是P型摻雜碳化矽，然實際實施時並不以此為限
前述該第二摻雜區43定義出該整流區RA；該整流區RA沿該第二方向Y的相對兩側邊分別定義出一主動區AA，且於該整流區RA及該等主動區AA的外圍定義出一外圍區PA。該整流區RA具有至少一由蕭特基二極體構成的整流結構SD，每一主動區AA具有至少一主動部A，且該等主動部A與該整流結構SD沿該第二方向Y排列分佈；該等成長條柱狀的第三摻雜區44會延伸至該第一摻雜區41，而形成多條於該第一摻雜區41交錯排列的柱狀區，且該等第三摻雜區44與該第一摻雜區41共同定義出該等沿該第一方向X分佈而與該等主動部A與該整流結構SD的排列方向彼此正交的超級接面SJ(Super Junction)。
具體的說，每一個主動部A具有一源極S、一溝渠式閘極結構TG。該源極S自該井區42頂面向下且深度小於該井區42，該源極S與該第一摻雜區41為同型摻雜且摻雜濃度大於該第一摻雜區41。該溝渠式閘極結構TG與相應的其中一源極S的側邊鄰接，具有自該主動區AA的頂面向下並沿該第一方向X延伸，深度超過該井區42且與該源極S的側邊鄰接的閘極溝渠101、一形成於該閘極溝渠101的內側表面的絕緣層102，及填置於該閘極溝渠101並覆蓋該絕緣層102的閘極電極103。其中，該絕緣層102可選自氮化物、氧化物，或氮氧化物，例如氮化矽、氧化矽或氮氧化矽，該閘極電極103可為多晶矽。
此外，該電晶體4還包括多個溝渠式接觸電極TC及多個重摻雜部HD。
該等溝渠式接觸電極TC具有一自該整流區RA頂面向下形成，深度不大於該井區42且沿該第一方向X橫跨延伸至該外圍區PA的第一溝渠201、分別自該主動區AA頂面向下形成，深度不大於該井區42且沿該第一方向X延伸並橫跨該等源極S至該外圍區PA的第二溝渠301、多條自該外圍區PA的頂面向下形成，深度不大於該井區42，沿該第一方向X橫跨延伸且與該等第一溝渠201平行的第三溝渠401，及多個分別對應填置於該第一溝渠201、該等第二溝渠301及該等第三溝渠401的導電金屬202、302、402。前述對應形成於該整流區RA的導電金屬與該第二摻雜區43為蕭特基接觸(Schottky contact)，而形成該由蕭特基二極體構成的整流結構SD；該等位於主動區AA的導電金屬302則用於供令該等源極S對外電連接。
該等重摻雜部HD為第二型摻雜(P型摻雜)，分別對應位於該閘極溝渠101、該第一溝渠201、該等第二溝渠301及該等第三溝渠401的下方並與該等溝渠的底部鄰接。
該介電絕緣層5覆蓋該電晶體4的頂面，由低介電常數的絕緣材料，例如磷矽玻璃(PSG)、硼磷矽玻璃(BPSG)等所構成。
該導電單元6設置於該介電絕緣層5上，具有多條接觸電極線61、多條閘極電極線 (圖未示)，及多個導電插塞62。
其中，該等導電插塞62貫穿該介電絕緣層5並分別與該等閘極電極101，及該等導電金屬202、302、402連接。每一條閘極電極線透過相應的導電插塞62與填置於該閘極溝渠101的該閘極電極102電連接，而令該等閘極電極線沿該第二方向Y間隔分佈；每一條接觸電極線61也會透過相應的導電插塞62分別與該等金屬插塞202、302、402連接，令該等接觸電極線61沿該第二方向Y與該等閘極電極線間隔交錯分佈，而可透過該導電單元6將該溝渠式閘極電晶體元件對外電連接。
於一些實施例中，該每一溝渠式閘極結構TG的該絕緣層102的底部具有最大厚度，且厚度不小於1000Å。利用讓該絕緣層102的底部具有最大厚度，可避免該溝渠式閘極結構TG的溝渠底部因電場集中所造成的閘極氧化層崩潰問題而可提高元件的耐壓。
由於SiC基材的氧化層品質不易控制，通常有過多缺陷 (defect)導致通道阻抗較高，而一般可藉由拉高溝渠密度以有效改善通道阻抗，但習知的P/N超級接面與元件的通道層是以同一方向延伸分佈，因此，溝渠密度的調整會受到P柱所限制，無法隨意調整。而本發明該溝渠式閘極電晶體元件利用將該電晶體4的該等主動部A與整流結構SD沿該第二方向Y排列形成，並令該電晶體4結構中的超級接面SJ沿與該第二方向Y正交之該第一方向X分佈，讓該等超級接面SJ與該等主動部A的分佈方向彼此正交，因此，該等超級接面SJ的寬度調整與該主動部A的通道寬度的調整可各自獨立不相互影響，而可避免習知以共平面方向分佈的主動部及超級接面彼此相互影響的缺點，而可以令元件結構可具有較大的調整彈性。
此外，因為本發明的超級接面SJ與該等主動部A的分佈方向彼此正交，因此，位於該等閘極溝渠101底部的重摻雜部HD與該等超級接面SJ可更易連接，而可降低該等閘極溝渠101底部的邊緣電場及閘極與汲極之間的電容(C gd) ，除此之外，利用摻雜於SiC的重摻雜部 HD 可承受更高的崩潰接面電場，保護閘極溝渠101底部的氧化層，減少溝渠底部101的尖端電場所引發閘極可靠度問題；而進一步藉由將該整流結構SD整合於該電晶體4結構中，可減少該溝渠式功率電晶體於順向導通及關閉時回覆時間(recovery)的功耗，故確實能達成本發明的目的。
茲將本案溝渠式閘極電晶體元件該實施例的製作方法說明如下。
參閱圖5，首先進行步驟A，於該具有高濃度N型摻雜的碳化矽基板2上磊晶形成一摻雜濃度低於該碳化矽基板2的N型摻雜碳化矽磊晶層，於該基板2上形成該第一摻雜區41，且該第一摻雜區41厚度約為5~100um。
接著，參閱圖6，進行步驟B，利用形成於該第一摻雜區41頂面的圖案化光罩，自該第一摻雜區41的頂面以離子佈植方式向下形成多條P型摻雜的第三摻雜區44，且該等第三摻雜區44沿該第二方向Y延伸成長條柱狀並沿該第一方向X平行間隔排列。其中，該等第三摻雜區44的深度約為2~50 um。
參閱圖7，再進行步驟C，形成另一遮覆該等第三摻雜區44及部分的該第一摻雜區41的圖案化光罩，並自未被該圖案化光罩遮覆的該第一摻雜區41頂面以離子佈值方式形成分佈於該等第三摻雜區44並具有P型摻雜的井區42，該等井區42的摻雜濃度大於該等第三摻雜區44，且深度介於0.2~3 um。其中，未被摻雜形成該等井區42，而自頂面露出的該第一摻雜區41則形成該第二摻雜區43。
參閱圖8，接著進行步驟D，利用圖案化光罩及離子佈植方式，自位於該第二摻雜區43沿該第二方向Y的兩側邊的該等井區42的頂面向下形成具有N型摻雜且深度不超過該等井區42的多個源極S。其中，該等源極S的深度約為0.05~1 um。
接著，配合參閱圖9，進行步驟E。其中，圖9是以沿圖8之A-A割線的剖視結構進行說明，且該A-A割線位置即相當於圖1之IV-IV割線的位置。
該步驟E是利用蝕刻方式，自與每一個源極S的兩側邊相鄰的該井區42的頂面向下形成沿該第一方向X延伸，深度超過該井區的該等閘極溝渠101、一條自該第二摻雜區43(整流區RA)頂面向下形成，深度不大於該井區42且沿該第一方向X延伸的該第一溝渠201、分別自該等源極S頂面向下形成，深度不大於該井區42且沿該第一方向X橫跨延伸的第二溝渠301，及多條位於該等第二溝渠301外側，自該等第三摻雜區44及該井區32的頂面向下形成，深度不大於該井區32且沿該第一方向X延伸的第三溝渠401。其中，該等閘極溝渠101與該等第一溝渠201、第二溝渠301，及第三溝渠401相互平行，且該等閘極溝渠101的寬度大於該等第一溝渠201、第二溝渠301，及第三溝渠401的寬度。
然後，配合參閱圖10，其中，圖10是以接續圖9的剖視結構續加以說明。進行步驟F，利用離子佈值於對應每一個溝渠(閘極溝渠101、第一溝渠201、第二溝渠301、第三溝渠401)下方的半導體材料進行離子摻雜後退火，形成與該等溝渠(閘極溝渠101、第一溝渠201、第二溝渠301、第三溝渠401)的底部鄰接並具有P型摻雜的重摻雜部HD，且該等重摻雜區HD的摻雜濃度大於該井區42。
接著，參閱圖11，其中，圖11是以接續圖10的剖視結構續加以說明進行步驟G，於該等溝渠的表面沉積形成由絕緣材料構成的絕緣層並經退火處理，而該到該絕緣層102。
要說明的是，前述該步驟E及步驟G形成的該等閘極溝渠101的深度及該絕緣層102的厚度是依據所欲製得的功率元件的耐壓性而有不同，因為絕緣材料(例如半導體常用的高介電絕緣材料，如氮化矽(Si 3N 4)、氧化矽(SiO 2)或氮氧化矽(SiON x))的選擇，以及該等閘極溝渠101的深度與該絕緣層102的厚度與功率元件耐壓性之間的關係為本技術領域者所周知，因此，不再多加說明。
接著，參閱圖12，進行步驟H。圖12是以接續圖11的剖視結構續加以說明該步驟H形成的結構。於該等閘極溝渠101中填置覆蓋該絕緣層102的多晶矽，形成該等閘極電極103，得到一半成品。
再參閱圖13，進行步驟I，圖13是以接續圖12的剖視結構續加以說明該步驟I形成的結構。於該半成品的頂面形成該介電絕緣層5，並於該介電絕緣層5對應該等閘極溝渠101、第一溝渠201、第二溝渠301、第三溝渠401的位置向下蝕刻移除填置於該等第一溝渠201、第二溝渠301、第三溝渠401的絕緣材料形成穿孔，並經由該等穿孔於該等第一溝渠201、第二溝渠301、第三溝渠401沉積金屬，以形成與該半成品的半導體材料成歐姆接觸的導電金屬302、402，以及與半導體材料成蕭特基接觸(Schottky contact)的導電金屬202，以及填置於該等穿孔並分別與該等導電金屬202、302、402及閘極電極102連接的導電插塞62。
最後，參閱圖14，進行步驟K，於該介電絕緣層5上形成分別與該等導電插塞62連接的該等接觸電極線61及該等閘極電極線(圖未示)，並於該基板2反向該介電絕緣層5的表面形成與該基板2成歐姆接觸的該汲極電極3，即可製得如圖1所示的該溝渠式閘極電晶體元件。
綜上所述，本發明該溝渠式閘極電晶體元件利用讓該電晶體4的該等主動部A及整流結構SD與結構中的超級接面SJ的分佈方向彼此正交，因此，該等超級接面SJ的寬度調整與該主動部A的通道寬度的調整可各自獨立不相互影響，而可避免習知以共平面方向分佈的主動部及超級接面彼此相互影響的缺點，而可以令元件結構可具有較大的調整彈性。此外，藉由將該整流結構SD整合於該電晶體4結構中，還可減少該溝渠式功率電晶體於順向導通及關閉時回覆時間(recovery)的功耗，故確實能達成本發明的目的。
惟以上所述者，僅為本發明的實施例而已，當不能以此限定本發明實施的範圍，凡是依本發明申請專利範圍及專利說明書內容所作的簡單的等效變化與修飾，皆仍屬本發明專利涵蓋的範圍內。
2:基板
3:汲極電極
4:電晶體
41:第一摻雜區
42:井區
43:第二摻雜區
44:第三摻雜區
5:介電絕緣層
6:導電單元
61:接觸電極線
62:導電插塞
RA:整流區
AA:主動區
PA:外圍區
SD:整流結構
A:主動部
S:源極
TG:溝渠式閘極結構
101:閘極溝渠
102:絕緣層
103:閘極電極
SJ:超級接面
TC:溝渠式接觸電極
201:第一溝渠
301:第二溝渠
401:第三溝渠
202、302、402:導電金屬
HD:重摻雜部
X:第一方向
Y:第二方向
本發明的其他的特徵及功效，將於參照圖式的實施方式中清楚地呈現，其中： 圖1是一立體示意圖，說明本發明溝渠式閘極電晶體元件的實施例的結構示意圖； 圖2是一剖視示意圖，沿圖1的II-II割面線的剖視結構，輔助說明圖1； 圖3是一剖視示意圖，沿圖1的III-III割面線的剖視結構，輔助說明圖1； 圖4是一剖視示意圖，沿圖1的IV-IV割面線的剖視結構，輔助說明圖1； 圖5是一結構示意圖，輔助說明經過步驟A形成的結構； 圖6是一結構示意圖，輔助說明經過步驟B形成的結構； 圖7是一結構示意圖，輔助說明經過步驟C形成的結構； 圖8是一結構示意圖，輔助說明經過步驟D形成的結構； 圖9是一剖視結構示意圖，以沿圖8的A-A割面線的剖視結構說明經過步驟E形成的結構； 圖10是一剖視結構示意圖，是以接續圖9的剖視結構續加以說明經過步驟F形成的結構； 圖11是一剖視結構示意圖，是以接續圖10的剖視結構續加以說明經過步驟G形成的結構； 圖12是一剖視結構示意圖，是以接續圖11的剖視結構續加以說明經過步驟H形成的結構； 圖13是一剖視結構示意圖，是以接續圖12的剖視結構續加以說明經過步驟I形成的結構；及 圖14是一剖視結構示意圖，是以接續圖13的剖視結構續加以說明經過步驟K形成的結構。
2:基板
3:汲極電極
4:電晶體
41:第一摻雜區
42:井區
43:第二摻雜區
44:第三摻雜區
S:源極
SJ:超級接面

Claims (9)

  1. 一種溝渠式閘極電晶體元件，包含一基板及形成於該基板上的電晶體，該基板為第一型摻雜碳化矽，該電晶體為一構成材料為碳化矽的磊晶積層，包括：一整流區，具有至少一由蕭特基二極體構成的整流結構；至少一主動部，位於該整流區沿一第二方向的其中至少一側邊，且與該整流結構沿該第二方向排列分佈；及多個超級接面，沿一與該第二方向相交之第一方向分佈，其中，該電晶體具有一形成於該基板上，具有第一型摻雜且摻雜濃度小於該基板的第一摻雜區、一位於該第一摻雜區頂面並具有第二型摻雜的井區、自該井區頂面向下至與該第一摻雜區連接的第二摻雜區，及多條自該井區的頂面向下延伸至該第一摻雜區，並沿該第二方向延伸成長條柱狀的第三摻雜區，且該等第三摻雜區沿一與該第二方向相交的第一方向平行間隔排列，該至少一主動部具有至少一源極，該至少一源極是自該井區頂面向下延伸不超出該井區且位於該第二摻雜區沿該第二方向的其中至少一側邊，該第一摻雜區及該第二摻雜區為同型摻雜且具有相同摻雜濃度，該井區與該第三摻雜區為同型摻雜，且該井區的摻雜濃度大於該第三摻雜區，該第二摻雜區即定義出該整流區，且沿該第一方向排列的該等第三摻雜區與該第一摻雜區共同定義出該等超級接面。
  2. 如請求項1所述的溝渠式閘極電晶體元件，其中，該電晶體具有多個主動部，每一主動部具有一源極，及一溝渠式閘極結構，該等主動部分別分佈於該整流區沿該第二方向的相對兩側邊，且每一個溝渠式閘極結構分別與相應的其中一源極的側邊鄰接。
  3. 如請求項2所述的溝渠式閘極電晶體元件，其中，該整流區的兩側邊與相鄰的源極之間分別夾設一溝渠式閘極結構，且該溝渠式閘極結構的兩側邊分別與相鄰的該整流區及該源極相連接。
  4. 如請求項2所述的溝渠式閘極電晶體元件，其中，該整流區的兩側邊與相鄰的源極之間不具有該等溝渠式閘極結構。
  5. 如請求項2所述的溝渠式閘極電晶體元件，其中，每一溝渠式閘極結構具有自該主動部的頂面向下並沿該第一方向延伸，深度超過該井區且與該源極的側邊鄰接的閘極溝渠、一形成於該閘極溝渠的內側表面的絕緣層，及填置於該閘極溝渠並覆蓋該絕緣層的閘極電極，該溝渠式閘極電晶體元件還包含一覆蓋該電晶體的介電絕緣層，及一形成於該介電絕緣層上的導電單元，該導電單元具有多條閘極電極線，每一條閘極電極線可穿過該介電絕緣層與填置於該閘極溝渠的該閘極電極電連接，而令該等閘極電極線沿該第二方向間隔分佈。
  6. 如請求項5所述的溝渠式閘極電晶體元件，其中，該絕緣層選自氧化物或氮氧化物，該絕緣層的底部具有最大厚度且厚度不小於1000Å。
  7. 如請求項5所述的溝渠式閘極電晶體元件，該電晶體還包括一位於該整流區及該等主動部之外側的外圍區及多個溝渠式接觸電極，該等溝渠式接觸電極具有至少一自該整流區頂面向下形成，深度不大於該井區且沿該第一方向延伸的第一溝渠、多條自該主動區頂面向下形成，深度不大於該井區且沿該第一方向延伸的第二溝渠，及多條自該外圍區的頂面向下形成，深度不大於該井區且沿該第一方向延伸的第三溝渠，及多個分別填置於該至少一第一溝渠、該等第二溝渠及該等第三溝渠並與該磊晶積層成歐姆接觸的金屬層，該導電單元還具有多條接觸電極線，每一條接觸電極線分別穿過該介電絕緣層與相應的該等金屬層連接，而令該等接觸電極線沿該第二方向與該等閘極電極線間隔交錯分佈。
  8. 如請求項7所述的溝渠式閘極電晶體元件，其中，該電晶體還包含多個位於該磊晶積層並分別對應位於該等閘極溝渠、該至少一第一溝渠、該等第二溝渠，及該等第二溝渠的底部且為第二型摻雜的重摻雜區。
  9. 如請求項7所述的溝渠式閘極電晶體元件，其中，該導電單元還具有多個穿設於該介電絕緣層的導電插塞，該等接觸電極線及該等閘極電極線可透過等導電插塞分別與該等閘極電極及該等金屬層電連接。
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TW201427035A (zh) * 2012-12-20 2014-07-01 Ind Tech Res Inst 接面位障蕭特基二極體嵌於金氧半場效電晶體單元陣列之整合元件
TW202027269A (zh) * 2019-01-11 2020-07-16 力源半導體股份有限公司 溝渠式功率電晶體及其製作方法

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TW201427035A (zh) * 2012-12-20 2014-07-01 Ind Tech Res Inst 接面位障蕭特基二極體嵌於金氧半場效電晶體單元陣列之整合元件
TW202027269A (zh) * 2019-01-11 2020-07-16 力源半導體股份有限公司 溝渠式功率電晶體及其製作方法

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