TWI590450B - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
TWI590450B
TWI590450B TW104128923A TW104128923A TWI590450B TW I590450 B TWI590450 B TW I590450B TW 104128923 A TW104128923 A TW 104128923A TW 104128923 A TW104128923 A TW 104128923A TW I590450 B TWI590450 B TW I590450B
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sic
type
disposed
sic region
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TW104128923A
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TW201635538A (zh
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Hiroshi Kono
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Toshiba Kk
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Description

半導體裝置 [相關申請案]
本申請案享有以日本專利申請2015-52275號(申請日：2015年3月16日)作為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之全部內容。
本發明之實施形態係關於一種半導體裝置。
作為新一代半導體器件用之材料，期待SiC(碳化矽)。SiC與Si(矽)相比，具有帶隙為3倍、擊穿電場強度約為10倍、及熱導率約為3倍之優異物性。若充分利用該特性，則可實現低損耗且可於高溫下進行動作之半導體器件。
若對MOSFET(Metal Oxide Semiconductor Field Effect Transistor，金屬氧半導體場效應電晶體)之電極間施加突波電壓，則會產生突崩潰。若於例如胞區域以外之設計上未預料到之位置產生突崩潰，則有引起器件之破壞之虞。
SiC與Si相比，具有例如p型雜質區域之薄片電阻或對p型雜質區域之接觸電阻較高之特殊性。於提高器件之突崩耐量之方面，亦要求考慮上述SiC之特殊性之器件設計。
本發明之實施形態提供一種可提高突崩耐量之半導體裝置。
實施形態之半導體裝置係具備胞區域、閘極焊墊區域或閘極配線 區域、及上述胞區域與上述閘極焊墊區域或上述閘極配線區域之間之胞端區域者，且上述胞區域具有：SiC基板，其具備第一面與第二面；n型第一SiC區域，其設置於上述SiC基板內之上述第一面；p型第二SiC區域，其設置於上述第一SiC區域與上述第二面之間；n型第三SiC區域，其設置於上述第二SiC區域與上述第二面之間；p型第四SiC區域，其設置於上述第二SiC區域內之上述第一面，且p型雜質濃度高於上述第二SiC區域；閘極絕緣膜，其設置於上述第二SiC區域上；第一閘極電極，其設置於上述閘極絕緣膜上；第一電極，其設置於上述第一面上，且藉由第一接觸部而與上述第一SiC區域及上述第四SiC區域相接；及第二電極，其設置於第二面上；上述閘極焊墊區域或上述閘極配線區域具有：場絕緣膜，其設置於上述第一面上，且膜厚較上述閘極絕緣膜厚；第二閘極電極，其設置於上述場絕緣膜上；及p型第五SiC區域，其設置於上述第三SiC區域與上述場絕緣膜之間，與上述第一面相接，且p型雜質之峰濃度為1×1018cm-3以上；上述胞端區域具有：p型第六SiC區域，其與上述第五SiC區域連接；p型第七SiC區域，其設置於上述第六SiC區域內之上述第一面，且p型雜質濃度高於上述第六SiC區域；及上述第一電極，其藉由第二接觸部而與上述第七SiC區域相接；藉由上述第二接觸部而與上述第一電極相接之上述第一面之整個面為p型SiC區域。
10‧‧‧SiC基板
12‧‧‧n+型源極區域(第一SiC區域)
14‧‧‧p型基極區域(第二SiC區域)
16‧‧‧n-型漂移區域(第三SiC區域)
18‧‧‧p+型接觸區域(第四SiC區域)
20‧‧‧汲極區域
22‧‧‧閘極絕緣膜
24‧‧‧胞閘極電極(第一閘極電極)
26‧‧‧源極電極(第一電極)
28‧‧‧汲極電極(第二電極)
30‧‧‧層間絕緣膜
32‧‧‧場絕緣膜
34‧‧‧引出閘極電極(第二閘極電極)
36‧‧‧p型場p區域(第五SiC區域)
38‧‧‧閘極焊墊電極
40‧‧‧p型胞端p區域(第六SiC區域)
42‧‧‧p型胞端接觸區域(第七SiC區域)
44‧‧‧n型胞端接觸區域
100‧‧‧MOSFET(半導體裝置)
200‧‧‧MOSFET(半導體裝置)
300‧‧‧MOSFET(半導體裝置)
400‧‧‧MOSFET(半導體裝置)
500‧‧‧MOSFET(半導體裝置)
900‧‧‧MOSFET(半導體裝置)
A‧‧‧第一接觸部
B‧‧‧第二接觸部
d1‧‧‧深度
d2‧‧‧深度
圖1係第一實施形態之半導體裝置之模式剖視圖。
圖2係比較形態之半導體裝置之模式剖視圖。
圖3係第二實施形態之半導體裝置之模式剖視圖。
圖4係第三實施形態之半導體裝置之模式剖視圖。
圖5係第四實施形態之半導體裝置之模式剖視圖。
圖6係第五實施形態之半導體裝置之模式剖視圖。
以下，一面參照圖式，一面對本發明之實施形態進行說明。再者，以下之說明中，對相同之構件等標附相同之符號，對於已說明過一次之構件等，適當省略其說明。
又，於以下之說明中，n+、n、n-及p+、p、p-之記法表示各導電型中之雜質濃度之相對之高低。即，n+表示n型雜質濃度相對高於n，n-表示n型雜質濃度相對低於n。又，p+表示p型雜質濃度相對高於p，p-表示p型雜質濃度相對低於p。再者，亦有將n+型、n-型僅記為n型，將p+型、p-型僅記為p型之情形。
雜質濃度例如可利用SIMS(Secondary Ion Mass Spectrometry，二次離子質譜法)進行測定。又，雜質濃度之相對之高低例如亦可根據藉由SCM(Scanning Capacitance Microscopy，掃描電容顯微術)而求出之載子濃度之高低進行判斷。
本說明書中，所謂「SiC基板」係亦包含例如藉由磊晶生長而形成於基板上之SiC層之概念。
(第一實施形態)
本實施形態之半導體裝置係具備胞區域、閘極焊墊區域或閘極配線區域、及胞區域與閘極焊墊區域或閘極配線區域之間之胞端區域者，且胞區域具有：SiC基板，其具備第一面與第二面；n型第一SiC區域，其設置於SiC基板內之第一面；p型第二SiC區域，其設置於第一SiC區域與第二面之間；n型第三SiC區域，其設置於第二SiC區域與第二面之間；p型第四SiC區域，其設置於第二SiC區域內之第一面，且p型雜質濃度高於第二SiC區域；閘極絕緣膜，其設置於第一面之第二SiC區域上；第一閘極電極，其設置於閘極絕緣膜上；第一電極，其設置於第一面上，且藉由第一接觸部而與第一SiC區域及第四SiC區域相接；及第二電極，其設置於第二面上；閘極焊墊區域或閘極配線區域 具有：場絕緣膜，其設置於第一面上，且膜厚較閘極絕緣膜厚；第二閘極電極，其設置於場絕緣膜上；及p型第五SiC區域，其設置於第三SiC區域與場絕緣膜之間，且與第一面相接；胞端區域具有：p型第六SiC區域，其與第五SiC區域連接；p型第七SiC區域，其設置於第六SiC區域內，且p型雜質濃度高於第六SiC區域；及第一電極，其藉由第二接觸部而與第七SiC區域相接；藉由第二接觸部而與第一電極相接之第一面之整個面為p型SiC區域。
圖1係本實施形態之半導體裝置之模式剖視圖。本實施形態之半導體裝置為MOSFET。
MOSFET 100係使用SiC基板10而形成。於MOSFET 100，設置有胞區域、胞端區域、及閘極焊墊區域或閘極配線區域。
胞區域係規律地排列有複數個縱型MOSFET之胞之區域。各胞之形狀、配置並無特別限定。
閘極焊墊區域係形成有用以對MOSFET之各胞之閘極電極施加電壓之金屬之焊墊電極的區域。又，閘極配線區域係形成有用以對MOSFET之各胞之閘極電極施加電壓之金屬之閘極配線的區域。使用閘極配線，將MOSFET之各胞之閘極電極與焊墊電極連接。閘極配線區域亦被稱為閘極指狀區域。閘極焊墊區域與閘極配線區域之層構造基本上相同。因此，以下，以閘極焊墊區域為例進行說明。
胞端區域係胞區域與閘極焊墊區域或閘極配線區域之間之區域。設置有用以將胞區域內之MOSFET之各胞之閘極電極引出至閘極焊墊區域或閘極配線區域之構造。
MOSFET 100於胞區域具備：SiC基板10、n+型源極區域(第一SiC區域)12、p型基極區域(第二SiC區域)14、n-型漂移區域(第三SiC區域)16、p+型接觸區域(第四SiC區域)18、n+型汲極區域20、閘極絕緣膜22、胞閘極電極(第一閘極電極)24、源極電極(第一電極)26、汲極電極 (第二電極)28、及層間絕緣膜30。
又，於閘極焊墊區域，具備場絕緣膜32、引出閘極電極(第二閘極電極)34、p型場p區域(第五SiC區域)36、閘極焊墊電極38。
進而，於胞端區域，具備p型胞端p區域(第六SiC區域)40、及p型胞端接觸區域(第七SiC區域)42。
SiC基板10具備第一面及第二面。圖1中，所謂第一面係SiC基板10之上側之面。又，圖1中，所謂第二面係SiC基板10之下側之面。SiC基板10例如為4H-SiC結構之SiC。SiC基板10之厚度為例如250μm以上且500μm以下。
n+型源極區域(第一SiC區域)12設置於SiC基板10之第一面。n+型源極區域12含有n型雜質。n型雜質例如為氮(N)。n型雜質之雜質濃度為例如1×1019cm-3以上且5×1020cm-3以下。n+型源極區域12之深度為例如0.1μm以上且0.3μm以下。
p型基極區域(第二SiC區域)14設置於n+型源極區域12與第二面之間。基極區域14作為MOSFET 100之通道區域發揮功能。基極區域14含有p型雜質。p型雜質例如為鋁(Al)。關於p型雜質之雜質濃度，於基極區域14之表面，為例如1×1016cm-3以上且5×1017cm-3以下。p型雜質之雜質濃度以峰濃度計為例如1×1018cm-3以上且1×1019cm-3以下。基極區域14之深度為例如0.6μm以上且1.0μm以下。
n-型漂移區域(第三SiC區域)16設置於基極區域14與第二面之間。漂移區域16含有n型雜質。n型雜質例如為氮(N)。漂移區域16之n型雜質之雜質濃度、深度根據所要求之元件耐壓而不同。例如，若作為額定1200V之元件欲獲得耐壓1400V~1700V，則雜質濃度為約7×1015cm-3以上且1×1016cm-3以下。又，於此情形時，漂移區域16之深度較理想為例如9μm以上且11μm以下。
p+型接觸區域(第四SiC區域)18設置於基極區域14內之第一面。接 觸區域18具備降低源極電極26對基極區域14之接觸電阻之功能。
接觸區域18含有p型雜質。接觸區域18之p型雜質濃度高於p型基極區域14。p型雜質例如為鋁(Al)。p型雜質之雜質濃度為例如1×1019cm-3以上且5×1020cm-3以下。接觸區域18之深度為例如0.1μm以上且0.3μm以下。
n+型汲極區域20設置於SiC基板10之第二面。汲極區域20含有n型雜質。n型雜質例如為氮(N)。n型雜質之雜質濃度為例如5×1018以上且1×1020cm-3以下。汲極區域20之厚度為例如100μm以上且500μm以下。
閘極絕緣膜22設置於SiC基板10之第一面上。閘極絕緣膜22設置於p型基極區域14上。閘極絕緣膜22例如為氧化矽膜。
胞閘極電極(第一閘極電極)24設置於閘極絕緣膜22上。胞閘極電極24例如為摻雜有雜質之多晶矽。
層間絕緣膜30設置於胞閘極電極24上。層間絕緣膜30例如為氧化矽膜。
源極電極(第一電極)26設置於SiC基板10之第一面側。源極電極26設置於層間絕緣膜30上。源極電極26藉由胞區域之第一接觸部A而同時與源極區域12與接觸區域18相接。
源極電極26例如為金屬。源極電極26例如為鈦(Ti)與鋁(Al)之積層膜。
亦可於源極電極26之與源極區域12或接觸區域18相接之部分設置矽化物層。矽化物層例如為矽化鎳。源極電極26與源極區域12及接觸區域18之接觸較理想為歐姆接觸。
汲極電極(第二電極)28係與SiC基板10之第二面相接而設置。汲極電極28係與汲極區域20相接而設置。
汲極電極28例如為金屬。汲極電極28例如為鈦(Ti)與鎳(Ni)之積層膜。
亦可於汲極電極28之與汲極區域20相接之部分設置矽化物層。矽化物層例如為矽化鎳。汲極電極28與汲極區域20之接觸較理想為歐姆接觸。
場絕緣膜32設置於閘極焊墊區域之第一面上。場絕緣膜32之膜厚較閘極絕緣膜22厚。場絕緣膜32具備使SiC基板10與引出閘極電極(第二閘極電極)34之間絕緣之功能。場絕緣膜32例如為氧化膜。場絕緣膜32例如為氧化矽膜。
引出閘極電極(第二閘極電極)34設置於場絕緣膜32上。引出閘極電極34係為了將胞閘極電極24自胞區域引出至閘極焊墊區域而設置。引出閘極電極34例如為摻雜有雜質之多晶矽。引出閘極電極34於圖1之紙面之裏側或近前與胞閘極電極24連接。對於連接，例如使用多晶矽單體、或於多晶矽積層金屬膜而成之構造。
p型場p區域(第五SiC區域)36設置於漂移區域16與場絕緣膜32之間。場p區域36具備於MOSFET 100斷開時緩和施加於場絕緣膜32之電場而抑制場絕緣膜32之絕緣破壞之功能。
場p區域36含有p型雜質。p型雜質例如為鋁(Al)。場p區域36之p型雜質之峰濃度為1×1018cm-3以上。
為緩和施加於場絕緣膜32之電場，必須於MOSFET 100斷開時，場p區域36不會完全空乏化。就抑制完全空乏化之觀點而言，場p區域36之p型雜質之峰濃度必須為1×1018cm-3以上。場p區域36之p型雜質之峰濃度較理想為5×1018cm-3以上，更理想為1×1019cm-3以上。
場p區域36之深度為例如0.4μm以上且1.0μm以下。
閘極焊墊電極38設置於閘極焊墊區域之層間絕緣膜30上。閘極焊墊電極38具備對胞閘極電極24賦予閘極電位之功能。閘極焊墊電極38與引出閘極電極34連接。
閘極焊墊電極38例如為金屬。閘極焊墊電極38例如為鈦(Ti)與鋁 (Al)之積層膜。
p型胞端p區域(第六SiC區域)40設置於胞端區域。胞端p區域40與場p區域36連接。胞端p區域40含有p型雜質。p型雜質例如為鋁(Al)。關於p型雜質之雜質濃度，於胞端p區域40之表面，為例如1×1016cm-3以上且5×1017cm-3以下。p型雜質之雜質濃度以峰濃度計為例如1×1018cm-3以上且1×1019cm-3以下。胞端p區域40之深度為例如0.6μm以上且1.0μm以下。胞端p區域40例如具備與胞區域之基極區域14大致相同之p型雜質濃度及深度。
p型胞端接觸區域(第七SiC區域)42設置於胞端p區域40內。胞端接觸區域42設置於第一面。胞端接觸區域42具備降低源極電極26對胞端p區域40之接觸電阻之功能。
胞端接觸區域42含有p型雜質。胞端接觸區域42之p型雜質濃度高於胞端p區域40。p型雜質例如為鋁(Al)。p型雜質之雜質濃度為例如1×1019cm-3以上且5×1020cm-3以下。胞端接觸區域42之深度為例如0.1μm以上且0.3μm以下。胞端接觸區域42例如具備與接觸區域18大致相同之p型雜質濃度及深度。
源極電極26藉由胞端區域之第二接觸部B而與胞端接觸區域42相接。藉由第二接觸部B而與源極電極26相接之第一面之整個面為p型SiC區域。換言之，於與源極電極26相接之第一面不存在n型SiC區域。
繼而，對本實施形態之作用及效果進行說明。圖2係比較形態之半導體裝置之模式剖視圖。
比較形態之半導體裝置為MOSFET。MOSFET 900除於胞端區域之第二接觸部B中在與源極電極26相接之第一面設置有n型胞端接觸區域44以外，與第一實施形態之MOSFET 100相同。
MOSFET 900之第二接觸部B之下方之雜質區域之構成與第一接觸部A之下方之雜質區域之構成相同。為提高胞區域與胞端區域之製 程整合性，而形成有相同構成之雜質區域。
閘極焊墊區域之場p區域36與胞區域之基極區域14相比，寬度較大。並且，用於抑制場p區域36之電位之源極電極26之接點僅設置於胞端區域之第二接觸部B。
因此，若對MOSFET 900之源極電極26與汲極電極28之間施加突波電壓，則尤其是距第二接觸部B較遠之場p區域36之電位上升，有於閘極焊墊區域產生突崩潰之虞。於此情形時，有大電流集中於第二接觸部B，而於第二接觸部B產生器件之破壞之虞。因此，MOSFET 900之突崩耐量降低。
又，若於閘極焊墊區域產生突崩潰，則有因流至第二接觸部B之電洞電流而使胞端區域之寄生電晶體進行動作之虞。於此情形時，亦有大電流集中於第二接觸部B，而於第二接觸部B產生器件之破壞之虞。因此，MOSFET 900之突崩耐量降低。
再者，所謂胞端區域之寄生電晶體係包含n型胞端接觸區域44、p型胞端p區域40、及n-型漂移區域16之npn電晶體。有因電洞電流流至相當於npn電晶體之基極且與場p區域36連接之胞端p區域40而使npn電晶體導通之虞。
尤其是SiC與Si相比，難以降低例如p型雜質區域之薄片電阻或對p型雜質區域之接觸電阻。因此，場p區域36之薄片電阻之降低亦較困難，容易於閘極焊墊區域產生突崩潰。又，第二接觸部B之接觸電阻之降低亦較困難，難以抑制流過大電流時之破壞。
本實施形態之MOSFET 100中，於與第二源極電極26相接之第一面不存在n型SiC區域。具體而言，第二源極電極26僅與p型胞端接觸區域42接觸。因此，與比較形態之MOSFET 900相比，對胞端p區域40之有效之接觸電阻降低。
因此，即便假設大電流流至第二接觸部B，亦可抑制於第二接觸 部B之器件之破壞。因此，MOSFET 100之突崩耐量提高。
又，藉由對胞端p區域40之有效之接觸電阻之降低，而可抑制場p區域36之電位上升。因此，不易於閘極焊墊區域產生突崩潰。因此，MOSFET 100之突崩耐量提高。
根據本實施形態之MOSFET 100，可抑制突崩潰時之胞端區域之接觸部之破壞。又，可抑制場p區域36之電位上升。因此，可實現突崩耐量較高之MOSFET 100。
又，較理想為於基極區域14與漂移區域16之間、及胞端p區域40與漂移區域16之間，設置n型雜質濃度高於漂移區域16之n型區域。藉由設置n型區域，而降低胞區域及胞端區域之耐壓。因此，不易閘極焊墊區域產生突崩潰。因此，MOSFET 100之突崩耐量進一步提高。n型區域例如可藉由氮(N)之離子注入而形成。
(第二實施形態)
本實施形態之半導體裝置係具備胞區域、閘極焊墊區域或閘極配線區域、及胞區域與閘極焊墊區域或閘極配線區域之間之胞端區域者，且胞區域具有：SiC基板，其具備第一面與第二面；n型第一SiC區域，其設置於SiC基板內之第一面；p型第二SiC區域，其設置於第一SiC區域與第二面之間；n型第三SiC區域，其設置於第二SiC區域與第二面之間；p型第四SiC區域，其設置於第二SiC區域內之第一面，且p型雜質濃度高於第二SiC區域；閘極絕緣膜，其設置於第一面之第二SiC區域上；第一閘極電極，其設置於閘極絕緣膜上；第一電極，其設置於第一面上，且藉由第一接觸部而與第一SiC區域及第四SiC區域相接；及第二電極，其設置於第二面上；閘極焊墊區域或閘極配線區域具有：場絕緣膜，其設置於第一面上，且膜厚較閘極絕緣膜厚；第二閘極電極，其設置於場絕緣膜上；及p型第五SiC區域，其設置於第三SiC區域與場絕緣膜之間，與第一面相接，p型雜質濃度高於第一閘極 電極與第二面之間之第二SiC區域之p型雜質濃度，且p型雜質之峰濃度為1×1018cm-3以上；胞端區域具有：p型第六SiC區域，其與第五SiC區域連接；p型第七SiC區域，其設置於第六SiC區域內之第一面，且p型雜質濃度高於第六SiC區域；及第一電極，其藉由第二接觸部而與第七SiC區域相接。
本實施形態之半導體裝置於第五SiC區域之p型雜質濃度高於第一閘極電極與第二面之間之第二SiC區域之p型雜質濃度之方面與第一實施形態不同。又，於在第二接觸部B設置有n型胞端接觸區域之方面與第一實施形態不同。以下，對於與第一實施形態重複之內容，省略一部分記述。
圖3係本實施形態之半導體裝置之模式剖視圖。本實施形態之半導體裝置為MOSFET。
MOSFET 200中，p型場p區域(第五SiC區域)36之p型雜質濃度高於胞閘極電極(第一電極)24與第二面之間之p型基極區域(第二SiC區域)14之p型雜質濃度。具體而言，MOSFET 200中，p型場p區域36之p型雜質之峰濃度高於存在於胞閘極電極24下方之與漂移區域16之間之p型基極區域14之p型雜質之峰濃度。或者，p型場p區域36之p型雜質之平均濃度高於存在於胞閘極電極24下方之與漂移區域16之間之p型基極區域14之p型雜質之平均濃度。
場p區域36之p型雜質之峰濃度為1×1018cm-3以上。場p區域36之p型雜質之峰濃度較理想為5×1018cm-3以上，更理想為1×1019cm-3以上。
藉由將場p區域36之p型雜質之峰濃度設定為上述範圍，可獲得降低薄片電阻之效果。又，亦可獲得抑制場p區域36之完全空乏化之效果。
另一方面，存在於胞閘極電極24下方之至漂移區域16之間之p型基極區域14之p型雜質之峰濃度較理想為1×1018cm-3以上，更理想為5×1018cm-3以上，進而較理想為1×1019cm-3以上。
根據本實施形態之MOSFET 200，藉由提高場p區域36之p型雜質濃度之濃度，而降低場p區域36之薄片電阻。場p區域36之薄片電阻低於基極區域14之薄片電阻。因此，即便對源極電極26與汲極電極28之間施加突波電壓，場p區域36之電位亦不易上升。因此，可抑制於閘極焊墊區域或胞端區域產生突崩潰。
但，已知若與SiC基板之界面之p型雜質濃度、尤其是鋁(Al)濃度變高，則SiC基板上之絕緣膜、尤其是氧化矽膜之絕緣破壞耐壓會劣化。
因此，就使場p區域36之第一面之p型雜質濃度降低而不使場氧化膜32之絕緣破壞耐壓劣化之觀點而言，場p區域36之p型雜質濃度之峰位置距第一面之距離較理想為0.1μm以上。又，就容易藉由離子注入形成高濃度之區域之觀點而言，峰位置距第一面之距離較理想為0.3μm以下。
又，就不使場氧化膜32之絕緣破壞耐壓劣化之觀點而言，場p區域36之p型雜質之峰濃度較理想為1×1020cm-3以下，更理想為5×1019cm-3以下。
又，就不使場氧化膜32之絕緣破壞耐壓劣化之觀點而言，場p區域36之第一面中之p型雜質濃度較理想為5×1018cm-3以下，更理想為1×1018cm-3以下。
根據本實施形態之MOSFET 200，可抑制於閘極焊墊區域或閘極配線區域產生突崩潰。因此，可實現突崩耐量較高之MOSFET 200。
又，較理想為於基極區域14與漂移區域16之間、及胞端p區域40與漂移區域16之間設置n型雜質濃度高於漂移區域16之n型區域。藉由設置n型區域，而降低胞區域及胞端區域之耐壓。因此，不易於閘極焊墊區域產生突崩潰。因此，MOSFET 200之突崩耐量進一步提高。n型區域例如可藉由氮(N)之離子注入而形成。
(第三實施形態)
本實施形態之半導體裝置係具備胞區域、閘極焊墊區域或閘極配線區域、及胞區域與閘極焊墊區域或閘極配線區域之間之胞端區域者，且胞區域具有：SiC基板，其具備第一面與第二面；n型第一SiC區域，其設置於SiC基板內之第一面；p型第二SiC區域，其設置於第一SiC區域與第二面之間；n型第三SiC區域，其設置於第二SiC區域與第二面之間；p型第四SiC區域，其設置於第二SiC區域內之第一面，且p型雜質濃度高於第二SiC區域；閘極絕緣膜，其設置於第一面之第二SiC區域上；第一閘極電極，其設置於閘極絕緣膜上；第一電極，其設置於第一面上，且藉由第一接觸部而與第一SiC區域及第四SiC區域相接；及第二電極，其設置於第二面上；閘極焊墊區域或閘極配線區域具有：場絕緣膜，其設置於第一面上，且膜厚較閘極絕緣膜厚；第二閘極電極，其設置於場絕緣膜上；p型第五SiC區域，其設置於第三SiC區域與場絕緣膜之間，與第一面相接，較第二SiC區域之深度淺，且p型雜質之峰濃度為1×1018cm-3以上；胞端區域具有：p型第六SiC區域，其與第五SiC區域連接；p型第七SiC區域，其設置於第六SiC區域內之第一面，且p型雜質濃度高於第六SiC區域；及第一電極，其藉由第二接觸部而與第七SiC區域相接。
本實施形態之半導體裝置於第五SiC區域之深度較第二SiC區域之深度淺之方面與第一實施形態不同。又，於在第二接觸部B設置有n型胞端接觸區域之方面與第一實施形態不同。以下，對於與第一實施形態重複之內容，省略一部分記述。
圖4係本實施形態之半導體裝置之模式剖視圖。本實施形態之半導體裝置為MOSFET。
MOSFET 300中，p型場p區域(第五SiC區域)36之深度(圖4中之“d2”)較p型基極區域(第二SiC區域)14之深度(圖4中之“d1”)淺。
因此，場p區域36下方之漂移區域16之厚度較基極區域14下方之 漂移區域16之厚度厚。
根據本實施形態之MOSFET 300，閘極焊墊區域或閘極配線區域下方之漂移區域16之厚度與胞區域之漂移區域16之厚度相比變厚。因此，閘極焊墊區域或閘極配線區域之接面耐壓變高。因此，可抑制於閘極焊墊區域或閘極配線區域產生突崩潰。
就提高閘極焊墊區域或閘極配線區域之接面耐壓之觀點而言，場p區域36之深度(圖4中之“d2”)較理想為基極區域14之深度(圖4中之“d1”)之一半以下。
就提高閘極焊墊區域或閘極配線區域之接面耐壓之觀點而言，場p區域36之深度(圖4中之“d2”)較佳為較基極區域14之深度(圖4中之“d1”)淺0.1μm以上，更理想為淺0.3μm以上。
就使成為低耐壓區域之p型胞端p區域(第六SiC區域)40之寬度與場p區域36相比變窄之觀點而言，第二接觸部B與場p區域36之距離較理想為5μm以下，更理想為3μm以下。
就抑制場p區域36之完全空乏化之觀點而言，場p區域36之p型雜質之峰濃度較理想為5×1018cm-3以上，更理想為1×1019cm-3以上。
根據本實施形態之MOSFET 300，可抑制於閘極焊墊區域或閘極配線區域產生突崩潰。因此，可實現突崩耐量較高之MOSFET 300。
(第四實施形態)
本實施形態之半導體裝置除於第二接觸部B未設置n型胞端接觸區域以外，與第二實施形態相同。因此，對於與第二實施形態重複之內容，省略一部分記述。
圖5係本實施形態之半導體裝置之模式剖視圖。本實施形態之半導體裝置為MOSFET。
MOSFET 400中，p型場p區域(第五SiC區域)36之p型雜質濃度高於胞閘極電極(第一電極)24與第二面之間之p型基極區域(第二SiC區 域)14之p型雜質濃度。
又，於第二接觸部B，與源極電極26相接之第一面之整個面為p型SiC區域。換言之，於與源極電極26相接之第一面不存在n型SiC區域。
根據本實施形態之MOSFET 400，藉由與第二實施形態相同之效果，可抑制於閘極焊墊區域或閘極配線區域產生突崩潰。又，藉由與第一實施形態相同之效果，可抑制突崩潰時之胞端區域之接觸部之破壞。因此，可實現突崩耐量較高之MOSFET 400。
(第五實施形態)
本實施形態之半導體裝置除於第二接觸部B未設置n型胞端接觸區域以外，與第三實施形態相同。因此，對於與第三實施形態重複之內容，省略一部分記述。
圖6係本實施形態之半導體裝置之模式剖視圖。本實施形態之半導體裝置為MOSFET。
MOSFET 500中，p型場p區域(第五SiC區域)36之深度(圖6中之“d2”)較p型基極區域(第二SiC區域)14之深度(圖6中之“d1”)淺。
又，於第二接觸部B，與源極電極26相接之第一面之整個面為p型SiC區域。換言之，於與源極電極26相接之第一面不存在n型SiC區域。
根據本實施形態之MOSFET 500，藉由與第三實施形態相同之效果，可抑制於閘極焊墊區域或閘極配線區域產生突崩潰。又，藉由與第一實施形態相同之效果，可抑制突崩潰時之胞端區域之接觸部之破壞。因此，可實現突崩耐量較高之MOSFET 500。
第一至第五實施形態中，以平面型MOSFET為例進行了說明，但本發明亦可應用於溝槽內具備閘極電極之溝槽型MOSFET。
第一至第五實施形態中，以MOSFET為例進行了說明，但本發明亦可應用於IGBT(Insulated Gate Bipolar Transistor，絕緣閘雙極電晶體)。
已對本發明之若干實施形態進行了說明，但該等實施形態係作為示例而提出者，並不意圖限定發明之範圍。該等新穎之實施形態能以其他各種形態實施，且可於不脫離發明之主旨之範圍內進行各種省略、置換、變更。例如，亦可將一實施形態之構成要素與其他實施形態之構成要素置換或變更。該等實施形態或其變化包含於發明之範圍或主旨，並且包含於申請專利範圍所記載之發明及其均等之範圍內。
10‧‧‧SiC基板
12‧‧‧n+型源極區域(第一SiC區域)
14‧‧‧p型基極區域(第二SiC區域)
16‧‧‧n-型漂移區域(第三SiC區域)
18‧‧‧p+型接觸區域(第四SiC區域)
20‧‧‧汲極區域
22‧‧‧閘極絕緣膜
24‧‧‧胞閘極電極(第一閘極電極)
26‧‧‧源極電極(第一電極)
28‧‧‧汲極電極(第二電極)
30‧‧‧層間絕緣膜
32‧‧‧場絕緣膜
34‧‧‧引出閘極電極(第二閘極電極)
36‧‧‧p型場p區域(第五SiC區域)
38‧‧‧閘極焊墊電極
40‧‧‧p型胞端p區域(第六SiC區域)
42‧‧‧p型胞端接觸區域(第七SiC區域)
100‧‧‧MOSFET(半導體裝置)
A‧‧‧第一接觸部
B‧‧‧第二接觸部

Claims (10)

  1. 一種半導體裝置，其係包括胞(cell)區域、閘極焊墊區域或閘極配線區域、及上述胞區域與上述閘極焊墊區域或上述閘極配線區域之間之胞端區域者；且上述胞區域具有：SiC基板，其包括第一面與第二面；n型第一SiC區域，其設置於上述SiC基板內之上述第一面；p型第二SiC區域，其設置於上述第一SiC區域與上述第二面之間；n型第三SiC區域，其設置於上述第二SiC區域與上述第二面之間；p型第四SiC區域，其設置於上述第二SiC區域內之上述第一面，且p型雜質濃度高於上述第二SiC區域；閘極絕緣膜，其設置於上述第二SiC區域上；第一閘極電極，其設置於上述閘極絕緣膜上；第一電極，其設置於上述第一面上，且藉由第一接觸部而與上述第一SiC區域及上述第四SiC區域相接；及第二電極，其設置於上述第二面上；上述閘極焊墊區域或上述閘極配線區域具有：場絕緣膜，其設置於上述第一面上，且膜厚較上述閘極絕緣膜厚；第二閘極電極，其設置於上述場絕緣膜上；及p型第五SiC區域，其設置於上述第三SiC區域與上述場絕緣膜之間，與上述第一面相接，p型雜質濃度較上述第一閘極電極與上述第二面之間之上述第二SiC區域之p型雜質濃度高，且p型雜 質之峰濃度為1×1018cm-3以上；上述胞端區域具有：p型第六SiC區域，其與上述第五SiC區域連接；p型第七SiC區域，其設置於上述第六SiC區域內之上述第一面，且p型雜質濃度高於上述第六SiC區域；及上述第一電極，其藉由第二接觸部而與上述第七SiC區域相接；且藉由上述第二接觸部而與上述第一電極相接之上述第一面之整個面為p型SiC區域。
  2. 如請求項1之半導體裝置，其中上述第五SiC區域之p型雜質濃度之峰位置距上述第一面之距離為0.1μm以上且0.3μm以下。
  3. 如請求項1之半導體裝置，其中上述第五SiC區域之深度較上述第二SiC區域之深度淺。
  4. 如請求項3之半導體裝置，其中上述第五SiC區域之深度為上述第二SiC區域之深度之一半以下。
  5. 如請求項1至4中任一項之半導體裝置，其中上述場絕緣膜為氧化矽膜。
  6. 如請求項1至4中任一項之半導體裝置，其中上述第五SiC區域之p型雜質為鋁(Al)。
  7. 一種半導體裝置，其係包括胞區域、閘極焊墊區域或閘極配線區域、及上述胞區域與上述閘極焊墊區域或上述閘極配線區域之間之胞端區域者；且上述胞區域具有：SiC基板，其包括第一面與第二面；n型第一SiC區域，其設置於上述SiC基板內之上述第一面；p型第二SiC區域，其設置於上述第一SiC區域與上述第二面之 間；n型第三SiC區域，其設置於上述第二SiC區域與上述第二面之間；p型第四SiC區域，其設置於上述第二SiC區域內之上述第一面，且p型雜質濃度高於上述第二SiC區域；閘極絕緣膜，其設置於上述第二SiC區域上；第一閘極電極，其設置於上述閘極絕緣膜上；第一電極，其設置於上述第一面上，且藉由第一接觸部而與上述第一SiC區域及上述第四SiC區域相接；及第二電極，其設置於上述第二面上；上述閘極焊墊區域或上述閘極配線區域具有：場絕緣膜，其設置於上述第一面上，且膜厚較上述閘極絕緣膜厚；第二閘極電極，其設置於上述場絕緣膜上；及p型第五SiC區域，其設置於上述第三SiC區域與上述場絕緣膜之間，與上述第一面相接，p型雜質濃度高於上述第一閘極電極與上述第二面之間之上述第二SiC區域之p型雜質濃度，且p型雜質之峰濃度為1×1018cm-3以上；上述胞端區域具有：p型第六SiC區域，其與上述第五SiC區域連接；p型第七SiC區域，其設置於上述第六SiC區域內之上述第一面，且p型雜質濃度高於上述第六SiC區域；及上述第一電極，其藉由第二接觸部而與上述第七SiC區域相接。
  8. 如請求項7之半導體裝置，其中上述第五SiC區域之p型雜質濃度之峰位置距上述第一面之距離為0.1μm以上且0.3μm以下。
  9. 一種半導體裝置，其包括胞區域、閘極焊墊區域或閘極配線區 域、及上述胞區域與上述閘極焊墊區域或上述閘極配線區域之間之胞端區域者；且上述胞區域具有：SiC基板，其包括第一面與第二面；n型第一SiC區域，其設置於上述SiC基板內之上述第一面；p型第二SiC區域，其設置於上述第一SiC區域與上述第二面之間；n型第三SiC區域，其設置於上述第二SiC區域與上述第二面之間；p型第四SiC區域，其設置於上述第二SiC區域內之上述第一面，且p型雜質濃度高於上述第二SiC區域；閘極絕緣膜，其設置於上述第二SiC區域上；第一閘極電極，其設置於上述閘極絕緣膜上；第一電極，其設置於上述第一面上，且藉由第一接觸部而與上述第一SiC區域及上述第四SiC區域相接；及第二電極，其設置於上述第二面上；上述閘極焊墊區域或上述閘極配線區域具有：場絕緣膜，其設置於上述第一面上，且膜厚較上述閘極絕緣膜厚；第二閘極電極，其設置於上述場絕緣膜上；及p型第五SiC區域，其設置於上述第三SiC區域與上述場絕緣膜之間，與上述第一面相接，較上述第二SiC區域之深度淺，p型雜質濃度較上述第一閘極電極與上述第二面之間之上述第二SiC區域之p型雜質濃度高，且p型雜質之峰濃度為1×1018cm-3以上；上述胞端區域具有：p型第六SiC區域，其與上述第五SiC區域連接；p型第七SiC區 域，其設置於上述第六SiC區域內之上述第一面，且p型雜質濃度高於上述第六SiC區域；及上述第一電極，其藉由第二接觸部而與上述第七SiC區域相接。
  10. 如請求項9之半導體裝置，其中上述第五SiC區域之深度為上述第二SiC區域之深度之一半以下。
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