TW201606814A - 電壓非線性電阻元件及其製法 - Google Patents
電壓非線性電阻元件及其製法 Download PDFInfo
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- TW201606814A TW201606814A TW104108740A TW104108740A TW201606814A TW 201606814 A TW201606814 A TW 201606814A TW 104108740 A TW104108740 A TW 104108740A TW 104108740 A TW104108740 A TW 104108740A TW 201606814 A TW201606814 A TW 201606814A
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- C04B35/453—Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on oxide ceramics based on zinc, tin, or bismuth oxides or solid solutions thereof with other oxides, e.g. zincates, stannates or bismuthates
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Abstract
於氧化鋅系的電壓非線性電阻元件中,將高電流區域
的限制電壓抑制為低。
電壓非線性電阻元件10包括電阻體14以及一對
的電極16、18,前述電阻體14具有1個以氧化鋅為主成分且體積電阻率為1.0×10-1Ωcm以下的氧化鋅陶瓷層12a與以氧化鉍為主成分的氧化鉍層12b所接合的接合體12,前述電極16、18以導電通路橫穿前述氧化鋅陶瓷層12a與前述氧化鉍層12b的q接合面之方式形成於前述電阻體14上。此元件10的接合體12的氧化鋅陶瓷層12a,使用比以往的體積電阻率為低者。因此,高電流區域的限制電壓能夠抑制的比以往為低。
Description
本發明是有關於電壓非線性電阻元件及其製法。
電壓非線性電阻元件(壓敏電阻元件)是將電壓非線性電阻體以一對電極挾持的結構之元件,作為從異常電壓保護電子電路等的元件,而廣泛的應用於濕度感測器、溫度感測器等的各種的感測器。作為此種的電壓非線性電阻元件,在專利文獻1中揭示有在一對電極挾持電阻體的電壓非線性電阻元件,其中電阻體是在2個氧化鋅系瓷器之間挾持氧化物膜的結構,且氧化鋅系瓷器含有作為摻質的Al2O3等的氧化物,氧化物膜含有Bi2O3、Sb2O3等的2種氧化物。如依此元件,起始電壓V1mA(1mA(由元件形狀為0.4A/cm2)的電流流動時的兩端子間的電壓)被抑制在3V程度。
專利文獻1:日本專利公開2000-228302號公報
一般而言,與未含有摻質的氧化鋅相較之下,含有摻質的氧化鋅為低電阻,但專利文獻1的氧化鋅系瓷器是對ZnO添加0.009~0.018質量%之摻質的Al2O3,由於摻質的添加量極低而不能認定為電阻充分低。因此,專利文獻1的電壓非線性電阻元件在高電流區域(例如是流動20A/cm2的電流的情形)可能發生大的電壓。
本發明是為了解決上述課題而成者,主要的目的在於在氧化鋅系的電壓非線性電阻元件中,將高電流區域的限制電壓抑制為低。
本發明的電壓非線性電阻元件包括:電壓非線性電阻體,包含至少1個以氧化鋅為主成分且體積電阻率為1.0×10-1Ωcm以下的氧化鋅陶瓷層與以氧化鉍為主成分的氧化鉍層所接合的接合體;以及一對的電極,以導電通路橫穿前述氧化鋅陶瓷層與前述氧化鉍層的接合面之方式形成於前述電壓非線性電阻體上。
此電壓非線性電阻元件,作為電壓非線性電阻體的氧化鋅陶瓷層,使用與以往相比體積電阻率低的氧化鋅陶瓷層。因此,高電流區域(例如是流動20A/cm2的電流的情形)的限制電壓與以往相比能夠抑制為低。其結果,例如即使是因靜電而使大電流於本發明的電壓非線性電阻元件流動,能夠將電壓的上昇抑制為小,並能夠防止元件本身的絕緣破壞的產生。
於本發明的電壓非線性電阻元件中,前述氧化鋅陶瓷層亦可以含有選自由Al2O3、In2O3以及Ga2O3所組之組群中的1種以上。藉由添加此種的3價的金屬離子,能夠使氧化鋅陶瓷層的體積電阻率比較容易成為低電阻。
於本發明的電壓非線性電阻元件中,前述的氧化鉍層亦可以藉由於前述氧化鋅陶瓷層上濺鍍而形成。依此,由於能夠不將氧化鋅陶瓷層暴露於高溫而形成氧化鉍層,氧化鋅陶瓷層能夠迴避因受熱的影響而使體積電阻率上昇的疑慮。
於本發明的電壓非線性電阻元件中,前述電壓非線性電阻體亦可以構成為積層2個以上的前述接合體,並於相鄰的氧化鋅陶瓷層彼此之間,挾持有氧化鉍層,或挾持有氧化鉍層與導體層,或挾持有氧化鉍層、導體層與氧化鉍層。依此,藉由適當設定電壓非線性電阻元件內所積層的接合體的數目,能夠對應種種的壓敏電阻電壓。
本發明的電壓非線性電阻元件的製法包括:(a)於以氧化鋅為主成分且體積電阻率為1.0×10-1Ωcm以下的氧化鋅陶瓷層上,藉由濺鍍形成以氧化鉍為主成分的氧化鉍層而得到接合體的步驟;(b)準備至少2個前述接合體,在一方的接合體的前述氧化鉍層與另一方的接合體的前述氧化鋅陶瓷層之間挾持導體箔並疊合,或者是未挾持而直接疊合,於此狀態於惰性氣體環境中進行300~700℃的熱處理,藉此將前述接合體接合並積層以得到電壓非線性電阻體的步驟;以及(c)以導電通路橫穿前述氧化鋅陶瓷層與前述氧化鉍層
的接合面之方式,形成一對的電極的步驟,或是包括:(a)於以氧化鋅為主成分且體積電阻率為1.0×10-1Ωcm以下的氧化鋅陶瓷層上,藉由濺鍍形成以氧化鉍為主成分的氧化鉍層而得到接合體的步驟;(b)準備至少2個前述接合體,在一方的接合體的前述氧化鉍層與另一方的接合體的前述氧化鉍層之間挾持導體箔並疊合,或者是未挾持而直接疊合,於此狀態於惰性氣體環境中進行300~700℃的熱處理,藉此將前述接合體接合並積層以得到電壓非線性電阻體的步驟;以及(c)以導電通路橫穿前述氧化鋅陶瓷層與前述氧化鉍層的接合面之方式,形成一對的電極的步驟。
藉由此些的製法,能夠較容易的製造在電壓非線性電阻體內積層複數接合體的電壓非線性電阻元件。而且,由於步驟(b)的熱處理的溫度為較低的300~700℃,能夠防止因熱的影響所致的氧化鋅陶瓷層的體積電阻率的上昇。特別是,在步驟(b)的熱處理的溫度在300~500℃的情形,此效果變得顯著。
10、30、40、130、140‧‧‧電壓非線性電阻元件
12、42‧‧‧接合體
12a‧‧‧氧化鋅陶瓷層
12b‧‧‧氧化鉍層
14、34、44、134、144‧‧‧電壓非線性電阻體(電阻體)
16、18‧‧‧電極
33、43‧‧‧導體層
第1圖所示為電壓非線性電阻元件10的剖面圖。
第2圖所示為電壓非線性電阻元件30的剖面圖。
第3圖所示為電壓非線性電阻元件130的剖面圖。
第4圖所示為電壓非線性電阻元件40的剖面圖。
第5圖所示為電壓非線性電阻元件140的剖面圖。
第6圖所示為實施例1、2以及比較例1~3的電壓非線性電阻元件的電流-電壓特性的圖。
第7圖所示為氧化鋅陶瓷層的體積電阻率(Ωcm)與20A/cm2相當的電流值之限制電壓的關係的圖。
本發明的較佳實施型態,一邊參照圖式並說明如下。第1圖所示為電壓非線性電阻元件10的剖面圖。
電壓非線性電阻元件10包括電壓非線性電阻體14(簡稱為電阻體)與挾持此電阻體14的一對的電極16、18。
電阻體14具有1個氧化鋅陶瓷層12a與以氧化鉍為主成分的氧化鉍層12b接合的接合體12。氧化鋅陶瓷層12a為以氧化鋅為主成分、且體積電阻率為1.0×10-1Ωcm以下的層。體積電阻率較佳為1.0×10-3Ωcm以下。依此,高電流區域的限制電壓與以往相比能夠抑制為更進一步的低。氧化鉍層12b的厚度較佳為0.01~1μm,更佳為0.05~0.5μm。
一對的電極16、18以導電通路橫穿氧化鋅陶瓷層12a以及氧化鉍層12b的接合面的方式,形成於電阻體14上。電極16、18只要是與氧化鋅陶瓷呈現良好的歐姆性之導電性佳的材料,並沒有特別的限制,例如是可舉出金、銀、鉑、鋁等。此處,可得到將電極18作為陽極而施加電壓的情形容易使電流流動,相反的將電極16作為陽極而施加電壓的情形呈現電壓非線性的元件。
其次,以下說明電壓非線性電阻元件10的製造例。
˙氧化鋅陶瓷層12a的製作
氧化鋅陶瓷層12a,可藉由從體積電阻率為1.0×10-1Ωcm以下,較佳為1.0×10-3Ωcm以下的氧化鋅陶瓷塊切割出規定尺寸的板材而得到。氧化鋅陶瓷塊是藉由使作為摻質的Al、Ga、In等的3價離子固溶於氧化鋅陶瓷中,並將氧化鋅粉末於非氧化氣體環境中燒成而導入氧缺陷,而能夠獲得。對於固溶有摻質的氧化鋅陶瓷塊的獲得,首先,以於氧化鋅粉末中Al2O3、Ga2O3、In2O3等的3價金屬氧化物粉末成為0.05~2.0質量%的方式混合,並成形為規定形狀的成形體。其次,將此成形體於非氧化氣體環境(例如是氮氣體環境或氬氣體環境)下,以900~1200℃保持數小時後,再昇溫至1300~1500℃以數小時燒成。依此,能夠較容易的得到體積電阻率低的氧化鋅陶瓷塊。對於成為目的值之體積電阻率的方法,可調整氧化鋅粉末所混合的3價金屬氧化物粉末的質量%、或調整燒成溫度。而且,用作為原料的氧化鋅粉末,平均粒徑較佳為0.02~5μm 。3價金屬氧化物粉末的平均粒徑較佳為0.01~0.5μm。作為3價金屬氧化物粉末較佳為Al2O3粉末。作為Al2O3粉末可使用θ氧化鋁,亦可使用γ氧化鋁或勃姆石等。另一方面,對於將氧化鋅粉末於非氧化氣體環境燒成而得到體積電阻率低的氧化鋅陶瓷塊,例如是將氧化鋅粉末於非氧化氣體環境(例如是氮氣體環境或氬氣體環境)下,以1300~1500℃保持數小時而燒成。
˙氧化鉍層12b的製作
氧化鉍層12b可為氧化鉍單體,亦可以以氧化鉍為主成分而含有其他的氧化物(例如是Sb2O3、Cr2O3、MnO、CoO、ZnO、
SiO2等)作為副成分。於氧化鉍層12b為氧化鉍單體的情形,例如是可以藉由將氧化鉍作為靶材而濺鍍於氧化鋅陶瓷層12a上,以形成氧化鉍層12b。除了濺鍍之外亦可以使用真空蒸鍍或離子鍍等。或者是可以將含有氧化鉍粉末的糊料塗布於氧化鋅陶瓷層12a並乾燥,並於較低溫(例如是200~700℃,較佳是200~500℃)熱處理以作成氧化鉍層12b。另一方面,在氧化鉍層12b含有副成分的情形,可以在氧化鉍之外亦使用副成分作為靶材,藉由多元同時濺鍍以在氧化鋅陶瓷層12a上形成氧化鉍層12b。或者是可以將含有除了氧化鉍粉末之外的副成分的粉末之糊料塗布於氧化鋅陶瓷層12a並乾燥,並於較低溫熱處理以作成氧化鉍層12b。於熱處理的情形,由於較為低溫而氧化鋅陶瓷層12a幾乎不具有受熱的影響而體積電阻率上昇的疑慮,但在濺鍍的情形由於能夠以更低溫處理,因而能夠確實的迴避此疑慮。
˙電極16、18的製作
於本實施型態,電阻體14具有一個氧化鋅陶瓷層12a與氧化鉍層12b所接合的接合體12。電極16、18可藉由將電極材料蒸鍍或濺鍍於此電阻體14的兩面以製作。作為電極材料,可舉出金、銀、鉑、鋁等。或者是亦可以準備板狀的電極16、18而將此些經由導電性接合材料接合於電阻體14的各面。
如藉由以上所詳述的電壓非線性電阻元件10,在將電極16作為陽極而施加電壓時顯示電壓非線性,並能夠將高電流區域(例如是流動20A/cm2的電流的情形)的限制電壓抑制的比以往為低。其結果,例如即使是因靜電而使大電流於
電壓非線性電阻元件10流動,能夠將電壓的上昇抑制為小,並能夠防止元件本身的絕緣破壞的產生。
尚且,本發明並不限定於上述的實施型態,只要是屬於本發明的技術範圍,自然能夠以種種的型態實施。
例如是,上述電壓非線性電阻元件10是在具有1個接合體12的電阻體14的兩面設置電極16、18,亦可以使用複數的接合體12積層的電阻體以取代電阻體14。藉由使用此種的積層型的電阻體,變得能夠控制壓敏電阻電壓,而能夠得到因應用途的壓敏電壓的電壓非線性電阻元件。使用積層型的電阻體的例子如第2圖~第5圖所示。
第2圖所示的電壓非線性電阻元件30,是在電阻體34的兩面設置電極16、18,其中電阻體34為將2個接合體12經由導體層33積層並接合而成的積層型的電阻體。電阻體34是在相鄰的氧化鋅陶瓷層12a之間挾持氧化鉍層12b以及導體層33。電阻體34的製造例如下所述。首先,準備2個接合體12,將一方的接合體12的氧化鋅陶瓷層12a與另一方的接合體12的氧化鉍層12b相對向對合,於其間挾持、疊合作為導體箔的硬焊料(例如是Au-Ge合金箔、Au-Sn合金箔、Au-Si合金箔等),將此些加壓而一體化。將其於惰性氣體環境中昇溫至特定的接合溫度(例如是300~700℃,較佳為300~500℃),保持預定時間後降溫。依此,由於硬焊料經熔融或軟化後固化而成為導體層33,能夠得到電阻體34。如依此電壓非線性電阻元件30,可得到與上述元件10相同的效果。而且,由於使用2個接合體12所積層的電阻體34,與實施例1的電
壓非線性電阻元件10相比能夠使限制電壓約為2倍。進而,使用在作為氧化鋅陶瓷層12a的氧化鋅陶瓷中添加多量的摻質(3價離子)並以惰性氣體環境熱處理而多數形成氧缺陷、藉此而低電阻化者的情形,有可能因接合溫度過高(例如是900℃或1000℃)而使摻質析出且氧缺陷消失而使電阻提高,由於此處的接合溫度為700℃以下,較佳為500℃以下,能夠維持氧化鋅陶瓷層12a的低電阻。
第3圖所示的電壓非線性電阻元件130,是在電阻體134的兩面設置電極16、18,其中電阻體134是將3個接合體12個別經由導體層33積層並接合而成的電阻體。電阻體134是在相鄰的氧化鋅陶瓷層12a之間挾持氧化鉍層12b以及導體層33。由於基本的構成與所得的效果與第2圖的電壓非線性電阻元件30相同,此處省略詳細的內容。但是,由於元件130使用3個接合體12積層的電阻體134,與實施例1的電壓非線性電阻元件10相比能夠使限制電壓約為3倍。
第4圖所示的電壓非線性電阻元件40,是在電阻體44的兩面設置電極16、18,其中電阻體44為將2個接合體12經由導體層43積層並接合而成的積層型的電阻體。電阻體44是在相鄰的氧化鋅陶瓷層12a之間挾持氧化鉍層12b、導體層43以及氧化鉍層12b。電阻體44的製造例如下所述。首先,準備2個接合體12,將一方的接合體12的氧化鉍層12b與另一方的接合體12的氧化鉍層12b相對向對合,於其間挾持、疊合前述的硬焊料,將此些加壓而一體化。然後,與電壓非線性電阻元件30的情形相同,藉由於惰性氣體環境中進行熱處
理,由於硬焊料經熔融或軟化後固化而成為導體層43,能夠得到電阻體44。如依此電壓非線性電阻元件40,將電極16與電極18的任1個作為陽極而施加電壓的情形亦顯示電壓非線性,此時的限制電壓與實施例1的電壓非線性電阻元件10幾乎相同。進而,與電壓非線性電阻元件30相同的理由,能夠維持氧化鋅陶瓷層12a的低電阻。
第5圖所示的電壓非線性電阻元件140,是在電阻體144的兩面設置電極16、18,其中電阻體144為將2個接合體12與1個3層結構的接合體42經由導體層43積層並接合而成的積層型的電阻體。電阻體144是在相鄰的氧化鋅陶瓷層12a之間挾持氧化鉍層12b、導體層43以及氧化鉍層12b。電阻體144的製造例如下所述。首先,準備2個接合體12。而且,在氧化鋅陶瓷層12a兩面形成氧化鉍層12b而成為3層結構的接合體42。然後,將1個接合體12的氧化鉍層12b與3層結構的接合體42的一方的氧化鉍層12b之間挾持前述的硬焊料,將3層結構的接合體42的另一方的氧化鉍層12b與第2個接合體12的氧化鉍層12b之間挾持前述硬焊料,並依此狀態將此些加壓而一體化。然後,與電壓非線性電阻元件30的情形相同,藉由於惰性氣體環境中進行熱處理,由於硬焊料經熔融或軟化後固化而成為導體層43,能夠得到電阻體144。如依此電壓非線性電阻元件140,將電極16與電極18的任1個作為陽極而施加電壓的情形亦顯示電壓非線性,此時的限制電壓與實施例1的電壓相比為約2倍。
上述第2圖~第5圖的實施型態是將複數的接合體
12經由導體層33、43接合,但是於接合時亦可以不使用硬焊料,直接將接合體12彼此直接接合。此時,較佳是接合體12彼此以較低溫(例如是300~700℃,較佳為300~500℃)接合。
[實施例1]
將氧化鋅(平均粒徑1.5μm)中混合1質量%θ氧化鋁(平均粒徑0.02μm)而成形的成形體,在N2氣體環境以1100℃保持5小時後,再昇溫至1400℃進行5小時的燒成,以製作氧化鋅陶瓷塊。此氧化鋅陶瓷塊的體積電阻率為9.3×10-4Ωcm。將所得的氧化鋅陶瓷塊切割為10mm×10mm×1mm的板狀以得到氧化鋅陶瓷薄板。將此薄板的表面研磨、洗淨後,將氧化鉍用作為靶材進行高頻電漿濺鍍,於氧化鋅陶瓷薄板的表面成膜氧化鉍的濺鍍膜(厚度0.3μm),以得到接合體。於濺鍍使用ULVAC機工製RFS-200。成膜條件如下。靶材尺寸:直徑80mm,RF輸出:20W,氣體壓(Ar);2.0Pa,成膜時間:15分。
所得的接合體直接作為電阻體使用,於電阻體的兩面設置Al蒸鍍電極,以得到電壓非線性電阻元件(請參照第1圖)。對此電壓非線性電阻元件的兩電極施加電壓以測定電流-電壓特性。尚且,將設置於氧化鋅陶瓷薄板側的電極作為陽極,將設置於氧化鉍的濺鍍膜的電極作為陰極。測定結果表示於表1以及第6圖。1mA/cm2相當的電流值的限制電壓為2.7V,20A/cm2相當的電流值的限制電壓為4.3V。
表1
[實施例2]
除了於氧化鋅中混合2質量%θ氧化鋁以外,以與實施例1相同的製作氧化鋅陶瓷塊。此氧化鋅陶瓷塊的體積電阻率為1.1×10-4Ωcm。將此氧化鋅陶瓷塊切割為10mm×10mm×1mm的板狀以作為氧化鋅陶瓷薄板。使用此薄板以與實施例1相同的製造接合體。所得的接合體直接作為電阻體使用,於電阻體的兩面設置Al蒸鍍電極,以作為電壓非線性電阻元件。對此電壓非線性電阻元件的兩電極如同實施例1的施加電壓以測定電流-電壓特性。測定結果表示於表1以及第6圖。1mA/cm2相當的電流值的限制電壓為2.7V,20A/cm2相當的電流值的限制電壓為3.4V。
[比較例1]
以換算為Al2O3而成為0.001質量%的方式於氧化鋅中添加硝酸鋁水溶液,並以水分量成為50質量%的方式添加水,進而添加微量的結合劑以及消泡劑後,藉由超音波攪拌30分鐘、葉輪攪拌30分鐘以進行混合。混合後藉由噴霧乾燥器造粒以得到造粒物。將造粒物經由網眼為200μm的篩而篩選之後,經成形、脫脂之後於大氣環境以1400℃、5小時燒成,以製作氧
化鋅陶瓷塊。此氧化鋅陶瓷塊的體積電阻率為3.0×10-1Ωcm。將所得的氧化鋅陶瓷塊切割為10mm×10mm×1mm的板狀以得到氧化鋅陶瓷薄板。於此氧化鋅陶瓷薄板的表面如同實施例1的成膜氧化鉍的濺鍍膜,以得到接合體。所得的接合體直接作為電阻體使用,於電阻體的兩面設置Al蒸鍍電極,以作為電壓非線性電阻元件。對此電壓非線性電阻元件的兩電極如同實施例1的施加電壓以測定電流-電壓特性。測定結果表示於表1以及第6圖。1mA/cm2相當的電流值的限制電壓為2.5V,20A/cm2相當的電流值的限制電壓為10.2V。
[比較例2]
除了以換算為Al2O3而成為0.002質量%的方式於氧化鋅中添加硝酸鋁水溶液以外,以與比較例1相同的製作氧化鋅陶瓷塊。此氧化鋅陶瓷塊的體積電阻率為1.5×10-1Ωcm。將此氧化鋅陶瓷塊切割為10mm×10mm×1mm的板狀以作為氧化鋅陶瓷薄板,使用此薄板以與實施例1相同的製造接合體。所得的接合體直接作為電阻體使用,於電阻體的兩面設置Al蒸鍍電極,以作為電壓非線性電阻元件。對此電壓非線性電阻元件的兩電極如同實施例1的施加電壓以測定電流-電壓特性。測定結果表示於表1以及第6圖。1mA/cm2相當的電流值的限制電壓為2.6V,20A/cm2相當的電流值的限制電壓為8.8V。
[比較例3]
以Co3O4、MnO2、NiO粉末相對於氧化鋅分別成為1.2、0.50、0.47質量%的方式混合於氧化鋅中,並添加換算為Al2O3而為0.0018質量%的硝酸鋁水溶液。將此混合粉成形並於大氣
環境以1300℃、1小時進行熱壓燒成,以製作氧化鋅陶瓷塊。此氧化鋅陶瓷塊的體積電阻率為2.1×10-1Ωcm。將此氧化鋅陶瓷塊切割為10mm×10mm×1mm的板狀以作為氧化鋅陶瓷薄板,使用此薄板以與實施例1相同的製造接合體。所得的接合體直接作為電阻體使用,於電阻體的兩面設置Al蒸鍍電極,以作為電壓非線性電阻元件。對此電壓非線性電阻元件的兩電極如同實施例1的施加電壓以測定電流-電壓特性。測定結果表示於表1以及第6圖。1mA/cm2相當的電流值的限制電壓為2.7V,20A/cm2相當的電流值的限制電壓為9.0V。
如同上述,可了解與使用體積電阻率為3.0×10-1Ωcm的氧化鋅陶瓷薄板之比較例1的電壓非線性電阻元件相較之下,使用體積電阻為1.0×10-1Ωcm以下(特別是1.0×10-3Ωcm以下)的氧化鋅陶瓷薄板之實施例1、2的電壓非線性電阻元件,在高電流區域(例如是20A/cm2以上的區域)的產生電壓低,電子電路的保護功能優良。
[實施例3]
準備2個與實施例2相同而製作的接合體。於一方的接合體的氧化鋅陶瓷薄板與另一方的接合體的氧化鉍的濺鍍膜之間挾持Au-Ge合金(以質量比Au/Ge為88/12)的箔(厚度50μm)而將兩接合體重合。於此狀態於惰性氣體環境進行420℃、10分鐘的熱處理,將兩接合體接合而得到積層型的電阻體。於所得的電阻體的兩面設置Al蒸鍍電極,以得到電壓非線性電阻元件(請參照第2圖)。對此電壓非線性電阻元件的兩電極施加電壓以測定電流-電壓特性。尚且,將設置於氧化鋅陶瓷薄
板的電極作為陽極,將設置於濺鍍膜的電極作為陰極。其結果雖未圖示,但確認得到與實施例2相同的電壓非線性電阻特性。此情形的非線性區域(電流0.01~2A/cm2的區域)的限制電壓與實施例2相比為約2倍。
[實施例4]
除了以換算為Al2O3而成為0.1質量%的方式於氧化鋅中添加硝酸鋁水溶液以外,以與比較例1相同的製作氧化鋅陶瓷塊。此氧化鋅陶瓷塊的體積電阻率為1.0×10-1Ωcm。將此氧化鋅陶瓷塊切割為10mm×10mm×1mm的板狀以作為氧化鋅陶瓷薄板,使用此薄板以與實施例1相同的製造接合體。所得的接合體直接作為電阻體使用,於電阻體的兩面設置Al蒸鍍電極,以作為電壓非線性電阻元件。對此電壓非線性電阻元件的兩電極如同實施例1的施加電壓以測定電流-電壓特性。測定結果表示於表1以及第6圖。1mA/cm2相當的電流值的限制電壓為2.6V,20A/cm2相當的電流值的限制電壓為6.1V。
[實施例5]
除了於氧化鋅中混合0.5質量%θ氧化鋁以外,以與實施例1相同的製作氧化鋅陶瓷塊。此氧化鋅陶瓷塊的體積電阻率為8.9×10-3Ωcm。將此氧化鋅陶瓷塊切割為10mm×10mm×1mm的板狀以作為氧化鋅陶瓷薄板,使用此薄板以與實施例1相同的製造接合體。所得的接合體直接作為電阻體使用,於電阻體的兩面設置Al蒸鍍電極,以作為電壓非線性電阻元件。對此電壓非線性電阻元件的兩電極如同實施例1的施加電壓以測定電流-電壓特性。測定結果表示於表1以及第6圖。1mA/cm2
相當的電流值的限制電壓為2.7V,20A/cm2相當的電流值的限制電壓為5.2V。
對於以上的實施例1、2、4、5以及比較例1~3,將表示氧化鋅陶瓷層的體積電阻率(Ωcm)與20A/cm2相當的電流值之限制電壓的關係的圖表示於第7圖。根據第7圖可知,以氧化鋅陶瓷層的體積電阻率1.0×10-1Ωcm為邊界,20A/cm2相當的電流值之限制電壓具有大的變化。亦即是,可知氧化鋅陶瓷層的體積電阻率在超過1.0×10-1Ωcm的區域,20A/cm2相當的電流值之限制電壓為大的值,但在以1.0×10-1Ωcm為邊界的其以下的區域的限制電壓急遽變小。
[實施例6]
將與實施例2相同而製作的氧化鋅陶瓷塊切割為10mm×10mm×1mm的板狀以得到氧化鋅陶瓷薄板。對此薄板的表面進行研磨、洗淨之後,使用以Sb2O3、Co3O4、MnO2粉末相對於氧化鉍分別成為2.5、6.7、1.8質量%的方式混合至氧化鉍中並成形,且於大氣環境中以700℃、2小時燒成者作為靶材,進行高頻電漿濺鍍,於氧化鋅陶瓷薄板的表面成膜以氧化鉍為主成分的濺鍍膜(厚度0.3μm),以得到接合體。於濺鍍使用ULVAC機工製RFS-200。成膜條件如下。靶材尺寸:直徑80mm,RF輸出:20W,氣體壓(Ar);2.0Pa,成膜時間:20分。所得的接合體直接作為電阻體使用,於電阻體的兩面設置Al蒸鍍電極,以作為電壓非線性電阻元件。對此電壓非線性電阻元件的兩電極如同實施例1的施加電壓以測定電流-電壓特性。其結果雖未圖示,確認顯示與實施例2相同的電壓非
線性電阻特性。測定結果表示於表2。1mA/cm2相當的電流值的限制電壓為2.6V,20A/cm2相當的電流值的限制電壓為3.2V。
[實施例7]
準備2個與實施例6相同而製作的接合體。於一方的接合體的氧化鋅陶瓷薄板與另一方的接合體的氧化鉍的濺鍍膜之間挾持Au-Ge合金(以質量比Au/Ge為88/12)的箔(厚度50μm)而將兩接合體重合。於此狀態於惰性氣體以420℃進行10分鐘的熱處理,將兩接合體接合而得到積層型的電阻體。於所得的電阻體的兩面設置Al蒸鍍電極,以得到電壓非線性電阻元件(請參照第2圖)。對此電壓非線性電阻元件的兩電極施加電壓以測定電流-電壓特性。尚且,將設置於氧化鋅陶瓷薄板的電極作為陽極,將設置於濺鍍膜的電極作為陰極。對此電壓非線性電阻元件的兩電極如同實施例1的施加電壓以測定電流-電壓特性。其結果雖未圖示,確認顯示與實施例2相同的電壓非線性電阻特性。測定結果表示於表2。1mA/cm2相當的電流值的限制電壓為5.2V,20A/cm2相當的電流值的限制電壓為6.4V,為實施例6的2倍。
[實施例8]
準備2個與實施例6相同而製作的接合體。於一方的接合體的氧化鋅陶瓷薄板與另一方的接合體的氧化鉍的濺鍍膜之間挾持Ag箔(厚度20μm)而將兩接合體重合。於惰性氣體以700℃進行30分鐘的熱處理,將兩接合體接合而得到積層型的電阻體。於所得的電阻體的兩面設置Al蒸鍍電極,以得到電壓非線性電阻元件(請參照第2圖)。對此電壓非線性電阻元件的兩電極施加電壓以測定電流-電壓特性。尚且,將設置於氧化鋅陶瓷薄板的電極作為陽極,將設置於濺鍍膜的電極作為陰極。對此電壓非線性電阻元件的兩電極如同實施例1的施加電壓以測定電流-電壓特性。其結果雖未圖示,確認顯示與實施例2相同的電壓非線性電阻特性。測定結果表示於表2。1mA/cm2相當的電流值的限制電壓為5.3V,20A/cm2相當的電流值的限制電壓為6.6V,為實施例6的約2倍。
[比較例4]
準備2個與實施例6相同而製作的接合體。於一方的接合體的氧化鋅陶瓷薄板與另一方的接合體的氧化鉍的濺鍍膜之間挾持Ag箔(厚度20μm)而將兩接合體重合。於惰性氣體環境下進行900℃、30分鐘的熱處理,將兩接合體接合而得到積層型的電阻體。於所得的電阻體的兩面設置Al蒸鍍電極,以得到電壓非線性電阻元件(請參照第2圖)。對此電壓非線性電阻元件的兩電極施加電壓以測定電流-電壓特性。尚且,將設置於氧化鋅陶瓷薄板的電極作為陽極,將設置於濺鍍膜的電極作為陰極。對此電壓非線性電阻元件的兩電極如同實施例1
的施加電壓以測定電流-電壓特性。其結果,由所製作的電阻體並未顯示電壓非線性電阻特性。測定結果表示於表2。即使是顯示電壓非線性電阻特性者,1mA/cm2相當的電流值的限制電壓為5.3V,20A/cm2相當的電流值的限制電壓為15.0V,為比實施例6的2倍遠為高的限制電壓。
由以上的實施例6~8以及比較例4可知,在氧化鉍層中含有氧化鉍以外的其他氧化物(此處為Sb2O3、Co3O4、MnO2)的情形,如藉由比700℃高的溫度的熱處理將接合體彼此接合的話,電壓非線性特性的發現成為不穩定,且限制電壓變高,具有無法得到將高電流區域的產生電壓抑制為低之電壓非線性電阻元件的疑慮。
尚且,上述的實施例僅為本發明的一個例子,本發明並不限定於此些實施例。
10‧‧‧電壓非線性電阻元件
12‧‧‧接合體
12a‧‧‧氧化鋅陶瓷層
12b‧‧‧氧化鉍層
14‧‧‧電阻體
16、18‧‧‧電極
Claims (7)
- 一種電壓非線性電阻元件,包括:電壓非線性電阻體,包含至少1個以氧化鋅為主成分且體積電阻率為1.0×10-1Ωcm以下的氧化鋅陶瓷層與以氧化鉍為主成分的氧化鉍層所接合的接合體;以及一對的電極,以導電通路橫穿前述氧化鋅陶瓷層與前述氧化鉍層的接合面之方式形成於前述電壓非線性電阻體上。
- 如申請專利範圍第1項所記載的電壓非線性電阻元件,其中前述氧化鋅陶瓷層含有選自由Al2O3、In2O3以及Ga2O3所組之組群中的1種以上。
- 如申請專利範圍第1或2項所記載的電壓非線性電阻元件,其中前述氧化鉍層藉由於前述氧化鋅陶瓷層上濺鍍而形成。
- 如申請專利範圍第1至3項中任一項所記載的電壓非線性電阻元件,其中前述電壓非線性電阻體為積層2個以上的前述接合體,並於相鄰的氧化鋅陶瓷層彼此之間,挾持有氧化鉍層,或挾持有氧化鉍層與導體層,或挾持有氧化鉍層、導體層與氧化鉍層。
- 一種電壓非線性電阻元件的製法,包括:(a)於以氧化鋅為主成分且體積電阻率為1.0×10-1Ωcm以下的氧化鋅陶瓷層上,藉由濺鍍形成以氧化鉍為主成分的氧化鉍層而得到接合體的步驟;(b)準備至少2個前述接合體,在一方的接合體的前述氧化鉍層與另一方的接合體的前述氧化鋅陶瓷層之間挾持導 體箔並疊合,或者是未挾持而直接疊合,於此狀態於惰性氣體環境中進行300~700℃的熱處理,藉此將前述接合體接合並積層以得到電壓非線性電阻體的步驟;以及(c)以導電通路橫穿前述氧化鋅陶瓷層與前述氧化鉍層的接合面之方式,形成一對的電極的步驟。
- 一種電壓非線性電阻元件的製法,包括:(a)於以氧化鋅為主成分且體積電阻率為1.0×10-1Ωcm以下的氧化鋅陶瓷層上,藉由濺鍍形成以氧化鉍為主成分的氧化鉍層而得到接合體的步驟;(b)準備至少2個前述接合體,在一方的接合體的前述氧化鉍層與另一方的接合體的前述氧化鉍層之間挾持導體箔並疊合,或者是未挾持而直接疊合,於此狀態於惰性氣體環境中進行300~700℃的熱處理,藉此將前述接合體接合並積層以得到電壓非線性電阻體的步驟;以及(c)以導電通路橫穿前述氧化鋅陶瓷層與前述氧化鉍層的接合面之方式,形成一對的電極的步驟。
- 如申請專利範圍第5或6項所記載的電壓非線性電阻元件的製法,其中步驟(b)的熱處理的溫度為300~500℃。
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US10020415B2 (en) * | 2016-01-12 | 2018-07-10 | National University Of Singapore | Device incorporating an oxide film and method of fabricating the same |
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CN106673641B (zh) * | 2017-01-03 | 2019-08-20 | 华南理工大学 | 一种低压压敏陶瓷片及其制备方法 |
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