TW201505154A - 半導體裝置結構與其製法 - Google Patents

半導體裝置結構與其製法 Download PDF

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Publication number
TW201505154A
TW201505154A TW103115771A TW103115771A TW201505154A TW 201505154 A TW201505154 A TW 201505154A TW 103115771 A TW103115771 A TW 103115771A TW 103115771 A TW103115771 A TW 103115771A TW 201505154 A TW201505154 A TW 201505154A
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semiconductor wafer
semiconductor
substrate
front side
substrate via
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TW103115771A
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TWI531046B (zh
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Jing-Cheng Lin
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Taiwan Semiconductor Mfg Co Ltd
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Abstract

本揭露提供一種半導體裝置結構，包括：一第一半導體晶圓，其中該第一半導體晶圓包括一第一電晶體形成在該第一半導體晶圓之一前側；一第二半導體晶圓，其中該第二半導體晶圓包括一第二電晶體形成在該第二半導體晶圓之一前側，其中該第二半導體晶圓之一背側接合至該第一半導體晶圓之該前側；一內連線結構，形成在該第二半導體晶圓之該前側；以及至少一第一基板穿孔(through substrate via,TSV)直接接觸該第一半導體晶圓之一導電特徵與該內連線結構。

Description

半導體裝置結構與其製法
本揭露係有關於一種半導體裝置結構，且特別是有關於一種半導體裝置結構與其製造方法。
半導體裝置使用於各種電子應用中，舉例而言，諸如個人電腦、手機、數位相機以及其他電子設備。半導體裝置的製造通常是藉由在半導體基板上依序沉積絕緣或介電層材料、導電層材料以及半導體層材料，接著使用微影製程圖案化所形成的各種材料層，以形成電路組件和零件於此半導體基板之上。通常許多積體電路製作於單一半導體晶圓中，且沿著切割線(scribe line)切割相鄰的積體電路，以切割位在晶圓上的各晶粒。舉例而言，通常各自的晶粒被分別封裝在多種晶片模組(multi-chip modules)或其他類似的封裝結構中。
在半導體業界，不斷降低最小特徵尺寸，如此一來可允許更多的裝置集積於一個特定的區域中，藉此持續改善各種電子裝置(例如電晶體、二極體、電阻、電容等等)的集積密度。在某些應用中，相較於過去的產品，這些尺寸更小的電子裝置需要利用較少區域及/或較低高度之更小的封裝。
因此，目前已經開始發展新的封裝技術，其中半 導體晶粒堆疊於另一個半導體晶粒上，例如封裝體堆疊(package on package,PoP)與系統級封裝(system-in-package,SiP)技術。可藉由將晶粒放置在半導體晶圓上而完成一些三維積體電路堆疊(3DICs)結構。舉例而言，因為在堆疊晶粒之間的內連線結構具有降低的長度，三維積體電路堆疊(3DICs)結構提供較佳的積集密度(integration density)與其他優點，例如較快的速度與較高的帶寬(bandwidth)。然而，三維積體電路堆疊(3DICs)結構仍須面對其他挑戰。
本揭露提供一種半導體裝置結構，包括：一第一半導體晶圓，其中該第一半導體晶圓包括一第一電晶體形成在該第一半導體晶圓之一前側；一第二半導體晶圓，其中該第二半導體晶圓包括一第二電晶體形成在該第二半導體晶圓之一前側，其中該第二半導體晶圓之一背側接合至該第一半導體晶圓之該前側；一內連線結構，形成在該第二半導體晶圓之該前側；以及至少一第一基板穿孔(through substrate via,TSV)直接接觸該第一半導體晶圓之一導電特徵與該內連線結構。
本揭露另提供一種半導體裝置結構，包括：一第一半導體晶圓，其中該第一半導體晶圓包括一第一電晶體形成在該第一半導體晶圓之一前側與一第一接合層形成在該第一電晶體之上；一第二半導體晶圓，其中該第二半導體晶圓包括一第二電晶體形成在該第二半導體晶圓之一前側與一第二接合層形成於該第二半導體晶圓之一背側，其中該第二接合層接合至該第一接合層；至少一第一基板穿孔(through substrate via, TSV)形成在該第二半導體晶圓之中，其中該第一基板穿孔(TSV)具有一第一高度；以及至少一第二基板穿孔形成在該第一半導體晶圓之中與該第二半導體晶圓之中，其中該第二基板穿孔具有一大於該第一高度之第二高度。
本揭露亦提供一種半導體裝置結構之製法，包括以下步驟：提供一第一半導體晶圓與一第二半導體晶圓，其中該第一電晶體形成在該第一半導體晶圓之一前側，且沒有任何裝置形成在該第二半導體晶圓中；接合該第一半導體晶圓之該前側至該第二半導體晶圓之一背側；薄化該第二半導體晶圓之一前側；形成一第二電晶體在該第二半導體晶圓之該前側；以及形成至少一第一基板穿孔(TSV)在該第二半導體晶圓之中，其中該第一基板穿孔直接接觸該第一半導體晶圓之一導電特徵結構。
11‧‧‧薄化製程
100‧‧‧半導體晶圓
100a‧‧‧半導體晶圓之前側
100b‧‧‧半導體晶圓之背側
103‧‧‧裝置區域
104‧‧‧半導體基板
104a‧‧‧半導體基板之上表面
104b‧‧‧半導體基板之下表面
106‧‧‧閘極介電層
107‧‧‧介電層
108‧‧‧閘極電極
109‧‧‧閘極結構
110‧‧‧源極/汲極(S/D)區域
112‧‧‧隔離結構
114‧‧‧接觸插塞(contact plug)
122‧‧‧金屬化結構
124、124a‧‧‧導電特徵結構
126‧‧‧絕緣材料
142‧‧‧接合層
150‧‧‧結合結構
160‧‧‧重新佈線結構
162‧‧‧金屬墊
164‧‧‧保護層
165‧‧‧凸塊底層金屬層
166‧‧‧導電元件
200‧‧‧半導體晶圓
200a‧‧‧半導體晶圓之前側
200b‧‧‧半導體晶圓之背側
203‧‧‧裝置區域
204‧‧‧基板
204a‧‧‧半導體晶圓之上表面
204b‧‧‧半導體晶圓之下表面
206‧‧‧閘極介電層
207‧‧‧介電層
208‧‧‧閘極電極
209‧‧‧閘極結構
210‧‧‧源極/汲極區域
212‧‧‧隔離結構
214‧‧‧接觸插塞
242‧‧‧接合層
300、300’‧‧‧三維積體電路堆疊結構(3DIC stacking structure)
400、400b‧‧‧基板穿孔(through substrate via,TSV)
400a‧‧‧基板穿孔的側壁
410、410b‧‧‧襯層
420、420b‧‧‧擴散阻障層(diffusion barrier layer)
430、430b‧‧‧導電材料
500‧‧‧內連線結構
510‧‧‧導電特徵結構
520‧‧‧絕緣材料
H1、H2、H3‧‧‧高度
D1、D2‧‧‧深度
W1、W3‧‧‧寬度
W2‧‧‧距離
第1A-1F圖為一系列剖面圖，用於顯示本揭露實施例形成半導體裝置結構之各個製程階段。
第2A-2C圖為一系列剖面圖，用於顯示本揭露實施例形成半導體裝置結構之各個製程階段。
以下特舉出本揭露之實施例，並配合所附圖式作詳細說明。以下實施例的裝置和設計係為了簡化所揭露之發明，並非用以限定本揭露。本揭露於各個實施例中可能使用重複的參考符號及/或用字。這些重複符號或用字係為了簡化與 清晰的目的，並非用以限定各個實施例及/或所述結構之間的關係。此外，說明書中提到在第二製程進行之前實施第一製程可包括第二製程於第一製程之後立即進行第二製程，也可包括有其他製程介於第一製程與第二製程之間的實施例。下述圖形並非依據尺寸繪製，該些圖式僅為了幫助說明。再者，說明書中提及形成第一特徵結構位於第二特徵結構之上，其包括第一特徵結構與第二特徵結構是直接接觸的實施例，另外也包括於第一特徵結構與第二特徵結構之間另外有其他特徵結構的實施例，亦即，第一特徵結構與第二特徵結構並非直接接觸。
本揭露提供形成半導體裝置結構之各種實施例。依據本揭露之實施例，第1A圖~第1F圖顯示形成半導體裝置結構之各個製程階段的剖面圖。依據本揭露之實施例，請參見第1A圖，其顯示半導體晶圓100之一部份與其他半導體晶圓200之一部份。
半導體晶圓100包括半導體基板104，其由矽或其他半導體材料所組成，且半導體基板104具有上表面104a與下表面104b。另外，半導體基板104可包括其他元素半導體，例如鍺。在一些實施例中，半導體基板104由化合物半導體所組成，例如，碳化矽(silicon carbide)、砷化鎵(gallium arsenic)、砷化銦(indium arsenide)或磷化銦(indium phosphide)。在一些實施例中，半導體基板104由合金半導體所組成，例如矽鍺(silicon germanium)、矽鍺碳(silicon germanium carbide)、磷化鎵砷(gallium arsenic phosphide)或磷化鎵銦(gallium indium phosphide)。在一些實施例中，半導體基板104具有磊晶層。舉 例而言，半導體基板104具有磊晶層位於塊狀半導體(bulk semiconductor)之上。
在一些實施例中，請參見第1A圖，在前段製程(front-end-of-line(FEOL)process)中，裝置區域103形成在半導體晶圓100之前側100a中。每一個裝置區域103包括閘極結構109埋設於介電層107之中、源極/汲極(S/D)區域110以及隔離結構112(例如淺溝隔離結構(STI))。閘極結構109包括閘極介電層106、閘極電極108以及間隙物(spacer)(圖中未顯示)。顯示於第1圖中的裝置區域103僅是舉例說明，亦可形成其他裝置在裝置區域103中。
可形成各種N型金屬氧化半導體(NMOS)裝置及/或P型金屬氧化半導體(PMOS)裝置在裝置區域103，例如電晶體或記憶體，以及類似裝置，連接以執行一或多種功能。亦可形成其他裝置在半導體基板104之中，例如電容(capacitors)、電阻(resistors)、二極體(diodes)、光二極體(photo-diodes)，保險絲(fuses)以及類似之裝置。這些裝置的功能可包括記憶體(memory)、處理器(processing)、感測器(sensors)、放大器(amplifiers)、電源分配(power distribution)、輸入/輸出電路(input/output circuitry)或類似之功能。於一些實施例中，裝置區域103包括N型金屬氧化半導體(NMOS)及/或P型金屬氧化半導體(PMOS)電晶體。
金屬化結構122形成在半導體基板104之上，例如位於裝置區域103之上。在一些實施例中，金屬化結構122包括內連線結構，例如接觸插塞(contact plug)114與導電特徵結構 124。導電特徵結構124埋設於絕緣材料126之中。在一些實施例中，金屬化結構122形成在後段製程(back-end-of-line(BEOL)process)中。在一些實施例中，接觸插塞(contact plug)114由導電材料所組成，例如銅、銅合金、鋁、鋁合金或上述之組合。導電特徵結構124也由導電材料所組成。另外，亦可使用其他材料。在一些實施例中，接觸插塞(contact plug)114與導電特徵結構124由導電材料所組成，這些導電材料具有耐熱性(heat resistant)，例如鎢(W)、銅(Cu)、鋁(Al)或鋁銅合金(AlCu)。在一些實施例中，絕緣材料126由氧化矽所組成。在一些實施例中，絕緣材料126包括多層介電材料所組成之介電層。一或多層介電層由低介電常數(low-k)所組成。在一些實施例中，多層介電層之最上層介電層由二氧化矽(SiO2)所組成。顯示之金屬化結構122僅是舉例說明。金屬化結構122可包括其他構造或包括一或多層導電線或接觸導通孔層(conductive lines and via layers)。
接合層142，其為介電層，形成在半導體晶圓100之前側100a，例如金屬化結構122之上。在一些實施例中，接合層142由含矽的介電材料所組成，例如氧化矽、氮氧化矽或矽烷氧化物(silane oxide)所組成。
在一些實施例中，接合層142由電漿增強型化學氣相沉積法(plasma enhanced chemical vapor deposition(PECVD))所形成。在一些其他實施例中，接合層142由旋轉塗佈法(spin-on method)所形成。在一些實施例中，接合層142具有厚度範圍介於約5nm至約300nm。
如第1A圖所示，裝置，例如包括閘極結構109的電晶體，形成在半導體晶圓100之前側100a，然而沒有任何裝置形成在半導體晶圓100之背側100b。
半導體晶圓200包括基板204，其類似半導體基板104。基板204具有上表面204a與下表面204b。接合層242，其為一介電層，形成在半導體晶圓200之背側200b上，例如基板204之下表面204b。在一些實施例中，接合層242類似於接合層142。沒有任何裝置預先形成在半導體晶圓200中。
如第1A圖所示，基板204從上表面204a到下表面204b具有高度範圍介於約50μm至約775μm。
在半導體晶圓100與200接合之前，處理接合層142與242。藉由乾式處理法或濕式處理法處理接合層142與242。乾式處理法包括電漿處理。在鈍氣環境下進行電漿處理，例如環境中充滿包括氮氣(N2)、氬氣(Ar)或上述組合之惰性氣體。另外地，也可使用其他處理方法。在一些實施例中，接合層142與242皆由氧化矽所組成，在進行接合之前，對接合層142與242進行電漿製程，以形成矽-氫氧(Si-OH)鍵在接合層142與242之表面上。
請參見第1B圖，在進行對準之後，半導體晶圓100接合至半導體晶圓200，以形成三維積體電路堆疊結構(3DIC stacking structure)300。如第1B圖所示，當半導體晶圓200接合至半導體晶圓100時，基板204的下表面204b面對基板104的上表面104a，且接合層142接合至接合層242。在壓力與熱的條件下進行半導體晶圓100與200之接合。在一些實施例中，接合的 壓力範圍為約0.7bar至約10bar。在一些實施例中，施加熱到半導體晶圓100與200包括，在溫度約20度至約1000度的範圍內進行退火步驟。可在氮氣環境(N2)、氬氣環境(Ar)、混合惰性氣體的環境或上述之組合下進行接合製程(bonding process)。
如第1B圖所示，堆疊結構(stacking structure)300包括接合結構150。接合結構150包括接合在一起的結合層142與242。因此，半導體晶圓200的背側200b接合至半導體晶圓100的前側100a。如果在接合之前，有裝置先形成在半導體晶圓200中，必須先準確對準半導體晶圓100與200。相反地，既然沒有裝置預先形成在半導體晶圓200中，因而不需要對準製程以對準半導體晶圓100與200。
請參見第1C圖，在接合半導體晶圓100與200之後，對半導體晶圓200的上表面204a進行薄化製程11。薄化製程11可包括研磨步驟與拋光步驟(例如化學機械研磨製程chemical mechanical polishing(CMP))。在薄化製程11之後，進行濕式蝕刻步驟，以移除形成在半導體晶圓200的上表面204a上的缺陷(defects)。在薄化製程11之後，基板204具有高度H2從基板204之上表面204a’到下表面204b，高度H2的範圍為約0.2μm到10μm。高度H2小於高度H1。在一些實施例中，高度H2與高度H1的比值(H2/H1)為約0.0002至約0.99。
請參見第1D圖，在薄化半導體晶圓200之後，裝置區域203形成在半導體晶圓200之前側200a中。在一些實施例中，裝置區域203形成在半導體前段製程(front-end-of-line (FEOL)process)。每個裝置區域203包括埋設於介電層207中的 閘極結構209、源極/汲極區域210、隔離結構212(例如淺溝隔離結構shallow trench isolation(STI)structures)。閘極結構209包括閘極介電層206、閘極電極208、間隙物(spacers)(圖中未顯示)。接觸插塞214形成在裝置區域203之上，例如在閘極結構209之上。在一些實施例中，在相對低的溫度下形成裝置區域203與接觸插塞214，以使金屬化結構122不會在製程期間被傷害。然而，在一些實施例中，包括接觸插塞144與導電特徵結構124的金屬化結構122由耐熱導電材料所組成，因此，裝置區域203與接觸插塞214的形成方法與材料可類似於裝置區域103與接觸插塞114中的形成方法與材料。在一些實施例中，裝置區域203包括N型金屬氧化半導體(NMOS)裝置及/或P型金屬氧化半導體(PMOS)裝置。
如第1D圖所示，裝置，例如包括閘極結構209的電晶體，形成在半導體晶圓200之前側200a，然而沒有任何裝置形成在半導體晶圓200之背側200b。此外，半導體晶圓200之背側200b接合至半導體晶圓100之前側100a，因此形成的堆疊結構300為前側對背側堆疊結構(face-to-back stacking structure)。
請參見第1E圖，形成裝置區域203之後，形成基板穿孔(through substrate via,TSV)400穿過半導體晶圓200。基板穿孔(TSV)400用於提供三維積體電路堆疊結構(3DIC stacking structure)300電性連接與散熱。雖然第1E圖僅顯示一個基板穿孔，亦可形成一或多個基板穿孔穿過半導體晶圓200。
基板穿孔(TSV)400包括襯層410、擴散阻障層(diffusion barrier layer)420與導電材料430。基板穿孔(TSV)400 由下述步驟所形成。首先，藉由一或多個蝕刻製程，形成基板穿孔開口(opening)延伸到半導體晶圓100之導電特徵結構124a。當基板穿孔開口形成之後，襯層410形成在基板穿孔開口之側壁，以作為隔離層，使得基板穿孔400之導電材料與半導體基板204不會彼此直接接觸。之後，在襯層410之上與基板穿孔開口之底部順應性地形成擴散阻障層420。擴散阻障層420用於避免導電材料(之後才會形成)遷移(migrating)到裝置區域103與203。在擴散阻障層420形成之後，導電材料430用於填充基板穿孔開口。之後，藉由一平坦化製程(例如化學機械研磨製程)移除形成在基板穿孔開口之外的過量襯層410、擴散阻障層420與導電材料430，雖然亦可使用其他移除製程。
襯層410由絕緣材料所組成，例如氧化物或氮化物。襯層410可藉由電漿增強型化學氣相沉積製程(PECVD)或其他適合的製程所形成。襯層410可以是單一層或多層。在一些實施例中，襯層410的厚度範圍為約100埃至約5000埃。
在一些實施例中，擴散阻障層420由鉭(Ta)、氮化鉭(TaN)、鈦(Ti)、氮化鈦(TiN)或鈷鎢合金(CoW)所組成。在一些實施例中，擴散阻障層420由物理氣相沉積製程(physically vapor deposition(PVD)process)所形成。在一些實施例中，擴散阻障層420由電鍍法所形成。在一些實施例中，導電材料430由銅、銅合金、鋁、鋁合金或上述之組合所組成。另外地，亦可使用其他合適的材料形成導電材料。
如第1E圖所示，在一些實施例中，基板穿孔(TSV)400具有寬度W1範圍為約0.025μm至約4μm。在一些實施 例中，基板穿孔(TSV)400具有深度D1範圍為約0.2μm至約10μm。在一些實施例中，基板穿孔(TSV)400具有深寬比(aspect ratio)(D1/W1)範圍為約2至約15。
如第1E圖所示，基板穿孔(TSV)400用於連接位於半導體晶圓100上的導電特徵結構124a到半導體晶圓200。如果有一個類似於基板穿孔400的基板穿孔形成在半導體晶圓200中且具有如第1B圖所示的高度H1，此基板穿孔會具有比基板穿孔400較高的深寬比。因為具有較高的深寬比，填充材料到基板穿孔開口中會變成一項挑戰。孔洞(voids)可能會形成在基板穿孔開口中。此外，如果襯層410或擴散阻障層420的側壁覆蓋不完全，可能會發生關於導電材料430的一些凸出或是擴散問題。相反地，如第1E圖所示，既然半導體晶圓200之高度已經從高度H1降低至高度H2，基板穿孔(TSV)400具有相對較小的深寬比。因此，可以解決或大幅地改善由於高深寬比的基板穿孔所導致的孔洞問題、突出或擴散問題。再者，可以降低三維積體電路堆疊結構(3DIC stacking structure)300的整體封裝高度，以符合先進封裝結構的需求。因此，三維積體電路堆疊結構(3DIC stacking structure)300可獲得較小的外觀尺寸(form factor)。
此外，因為基板穿孔會產生的應力，因此位在基板穿孔附近的裝置的性能會受到嚴重的影響。排除區域(keep-out zone,KOZ)是用於定義一區域，此區域不能有裝置設置於此。在一些實施例中，係由距離W2定義排除區域(KOZ)，此距離W2是從基板穿孔400的側壁400a開始測量到最靠近閘極 結構209的地方。因為薄化步驟，使半導體晶圓200具有相對較小的高度H2，且因為基板穿孔400的深度變小，使基板穿孔(TSV)400具有較小寬度W1。因此，因為基板穿孔400所導致的整體應力因而降低，且在第1E圖中的距離W2也因此變小。在一些實施例中，距離W2的範圍介於約0.01μm至約3μm。當距離W2變小時，可使用的裝置區域203的面積會因此提高。如此一來，會進一步提高在裝置區域203中的裝置的密度。
請參見第1F圖，當基板穿孔400形成之後，內連線結構500形成在半導體晶圓200之前側。內連線結構500藉由基板穿孔400電性連接到半導體晶圓100的導電特徵結構124a。內連線結構500包括導電特徵結構510，例如導電線(conductive lines)、導孔(vias)或導電墊(conductive pads)，形成在絕緣材料520之中。顯示在第1F圖中的導電特徵結構的金屬佈線(metal routings)僅是舉例說明。另外地，可依據實際之應用，設計其他導電特徵結構的金屬佈線。
如第1F圖所示，在堆疊結構300中，裝置，例如包括閘極結構109的電晶體，形成在半導體晶圓100之前側100a，然而沒有任何裝置形成在半導體晶圓100之背側100b。裝置，例如包括閘極結構209的電晶體，形成在半導體晶圓200之前側200a，然而沒有任何裝置形成在半導體晶圓200之背側200b。半導體晶圓200之背側200b接合到半導體晶圓100之前側100a，因此堆疊結構300為一種前側對背側的結構(front-to-back structure)。此外，內連線結構500形成在半導體晶圓200之前側200a上，且基板穿孔400直接接觸內連線結構 500與半導體晶圓100之導電特徵結構124a。
如果在半導體晶圓200接合到半導體晶圓100之前，有裝置預先形成在半導體晶圓200上。因為有裝置形成在半導體晶圓200之前側200a上，因此半導體晶圓200不可能被薄化。因此，很難形成小的基板穿孔(TSV)。相反地，因為沒有裝置預先形成在半導體晶圓200上，因此，半導體晶圓200可以從基板204的上表面204a開始被薄化。在薄化製程11之後，可以依序形成裝置(例如包括閘極結構209之電晶體)以及基板穿孔400在半導體晶圓200之前側200a上。如此一來，可以在前側對背側的三維積體電路堆疊結構300中形成相對較小的基板穿孔400。
此外，亦可對三維積體電路堆疊結構300執行其他製程步驟，且之後可將三維積體電路堆疊結構300切割成各自的晶片。
依據本接露之實施例，第2A-2C圖為一系列剖面圖，用於顯示形成半導體裝置結構之各個製程階段。如第2A圖所示，在2A圖中的三維積體電路堆疊結構300’類似於三維積體電路堆疊結構300，差別在於有額外的基板穿孔400b形成在半導體晶圓200中。堆疊結構300’的形成可牽涉額外的圖案化製程與蝕刻製程。舉例而言，藉由穿過半導體晶圓200以形成第一基板穿孔開口，並暴露一部分半導體晶圓100之導電特徵結構124a。在第一基板穿孔開口形成之後，藉由穿過第二半導體晶圓200以形成第二基板穿孔開口，以延伸到半導體晶圓100的裝置區域103上。之後，將襯層410b與410、擴散阻障層420b 與420以及導電材料430b與430填充到第一與第二基板穿孔，以形成基板穿孔400b與400。如第2A圖所示，基板穿孔400b包括類似於襯層410之襯層410b、類似於擴散阻障層420之擴散阻障層420b以及類似於導電材料430之導電材料430b，但是基板穿孔400b進一步延伸到半導體晶圓100的背側100b區域中。
在一些實施例中，基板穿孔400b具有寬度W3，寬度W3的範圍介於約0.3μm至約10μm。在一些實施例中，基板穿孔400b具有深度D2，深度D2的範圍介於約15μm至約100μm。在一些實施例中，基板穿孔400b具有深寬比(D2/W3)，深寬比的範圍介於約5至約15。深度D2比深度D1的比值為約2至約15。
請參見第2B圖，形成內連線結構500在半導體晶圓200的前側200a。內連線結構500包括導電特徵結構，例如導電線(conductive lines)、導孔(vias)或導電墊(conductive pads)，形成在絕緣材料之中。顯示在第2B圖中的導電特徵結構的金屬佈線(metal routings)僅是舉例說明。另外地，可依據實際之應用，設計其他導電特徵結構的金屬佈線。在一些實施例中，基板104具有高度H3，高度H3的範圍介於約10μm至約100μm。
請參見第2C圖，在形成內連線結構500之後，從基板104的下表面104b對半導體晶圓100進行薄化，以暴露基板穿孔400b的底部。在薄化製程之後，在半導體晶圓100的背側100b形成重新佈線結構(redistribution(RDL)structure)160(例如形成在基板104的薄化背側表面104b’上)。重新佈線結構(redistribution(RDL)structure)160包括金屬墊162形成在保護 層164中。金屬墊162電性連接到暴露的基板穿孔400b。在一些實施例中，金屬墊162由具有低電阻的導電材料所組成，例如銅(copper,Cu)、鋁(aluminum,Al)、銅合金(Cu alloys)、鋁合金(Al alloys)或其他合適的材料。雖然第2C圖僅顯示一個重新佈線結構(redistribution(RDL)structure)160，但也可以形成多於一個重新佈線結構。
凸塊底層金屬層(under bump metallization(UBM)layer)165形成在金屬墊162之上，以及導電元件166(例如焊料球)形成在凸塊底層金屬層165之上。凸塊底層金屬層165可包括一黏著層(adhesion layer)及/或潤濕層(wetting layer)。在一些實施例中，凸塊底層金屬層165由鈦(titanium,Ti)、氮化鈦(titanium nitride,TiN)、氮化鉭(tantalum nitride,TaN)、鉭(tantalum,Ta)或類似之材料所形成。在一些實施例中，凸塊底層金屬層165更包括銅晶種層。在一些實施例中，導電元件166由具有低電阻的導電材料所組成，例如焊料或焊料合金。示範性的焊料合金可包括錫(Sn)、鉛(Pb)、銀(Ag)、銅(Cu)、鎳(Ni)、鉍(Bi)或上述之組合。
在一些實施例中，內連線結構500藉由基板穿孔400b、重新佈線結構(redistribution(RDL)structure)160與導電元件166電性連接至位於半導體晶圓100的背側100b上的另一封裝結構(圖中未顯示)。在一些實施例中，其他導電元件，例如其他重新佈線結構形成在內連線結構500之上，以使半導體晶圓100與200能連接到其他封裝基板(圖中未顯示)。
如第2C圖所示，基板穿孔400與400b各自提供不同 的功能。基板穿孔400直接接觸內連線結構500與導電特徵結構124a，以及基板穿孔400b直接接觸內連線結構500與重新佈線結構160。因此，半導體晶圓200藉由基板穿孔400電性連接至半導體晶圓100，且半導體晶圓200藉由內連線結構500與基板穿孔400b電性連接至另一封裝結構(圖中未顯示)。基板穿孔400與400b提供快速的導電路徑以連接半導體晶圓100、半導體晶圓200及/或其他封裝結構，而不需要形成其他複雜的金屬佈線(metal routings)。
本揭露提供形成半導體裝置的各種實施例。第二半導體晶圓的背側接合至第一半導體晶圓之前側，第一半導體晶圓具有裝置，例如電晶體形成在其中。當第二半導體晶圓接合到第一半導體晶圓之後，薄化第二半導體晶圓的前側，其中第二半導體晶圓中沒有預先形成其他裝置。當薄化製程之後，裝置，例如電晶體，形成在第二半導體晶圓之前側，以形成前側對背側(front-to-back)(面對背face-to-back)的堆疊結構。相對較小的基板穿孔(TSV)形成在前側對背側堆疊結構之中。另外地，形成不同尺寸的基板穿孔(TSV)在前側對背側堆疊結構之中。
雖然本揭露已以數個較佳實施例揭露如上，然其並非用以限定本揭露，任何所屬技術領域中具有通常知識者，在不脫離本揭露之精神和範圍內，當可作任意之更動與潤飾，因此本揭露之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧半導體晶圓
100a‧‧‧半導體晶圓之前側
100b‧‧‧半導體晶圓之背側
103‧‧‧裝置區域
104‧‧‧半導體基板
124a‧‧‧導電特徵結構
126‧‧‧絕緣材料
200‧‧‧半導體晶圓
200a‧‧‧半導體晶圓之前側
200b‧‧‧半導體晶圓之背側
203‧‧‧裝置區域
204a‧‧‧基板之上表面
204b‧‧‧基板之下表面
214‧‧‧接觸插塞
300‧‧‧三維積體電路堆疊結構(3DIC stacking structure)
400‧‧‧基板穿孔(through substrate via,TSV)
400a‧‧‧基板穿孔的側壁
410‧‧‧襯層
420‧‧‧擴散阻障層(diffusion barrier layer)
430‧‧‧導電材料
H2‧‧‧高度
D1‧‧‧深度
W1‧‧‧寬度
W2‧‧‧距離

Claims (10)

  1. 一種半導體裝置結構，包括：一第一半導體晶圓，其中該第一半導體晶圓包括一第一電晶體形成在該第一半導體晶圓之一前側；一第二半導體晶圓，其中該第二半導體晶圓包括一第二電晶體形成在該第二半導體晶圓之一前側，其中該第二半導體晶圓之一背側接合至該第一半導體晶圓之該前側；一內連線結構，形成在該第二半導體晶圓之該前側；以及至少一第一基板穿孔(through substrate via,TSV)直接接觸該第一半導體晶圓之一導電特徵與該內連線結構。
  2. 如申請專利範圍第1項所述之半導體裝置結構，尚包括：一第一重新佈線結構(first redistribution(RDL)structure)，形成在該第一半導體晶圓之一背側。
  3. 如申請專利範圍第1項所述之半導體裝置結構，其中該第一半導體晶圓尚包括一第一接合層於該第一半導體晶圓之該前側，該第二半導體晶圓尚包括一第二接合層於該第二半導體晶圓之該背側，且該第一接合層接合至該第二接合層。
  4. 如申請專利範圍第1項所述之半導體裝置結構，其中該第一基板穿孔(first TSV)具有深寬比為約2至約15。
  5. 如申請專利範圍第1項所述之半導體裝置結構，其中一排除區域(keep-out zone,KOZ)定義為介於該第一基板穿孔(TSV)之側壁與該第二半導體晶圓之一裝置之一距離，且該距離介於約0.01μm至約3μm。
  6. 一種半導體裝置結構，包括： 一第一半導體晶圓，其中該第一半導體晶圓包括一第一電晶體形成在該第一半導體晶圓之一前側與一第一接合層形成在該第一電晶體之上；一第二半導體晶圓，其中該第二半導體晶圓包括一第二電晶體形成在該第二半導體晶圓之一前側與一第二接合層形成於該第二半導體晶圓之一背側，其中該第二接合層接合至該第一接合層；至少一第一基板穿孔(through substrate via,TSV)形成在該第二半導體晶圓之中，其中該第一基板穿孔(TSV)具有一第一高度；以及至少一第二基板穿孔形成在該第一半導體晶圓之中與該第二半導體晶圓之中，其中該第二基板穿孔具有一大於該第一高度之第二高度。
  7. 如申請專利範圍第6項所述之半導體裝置結構，其中該第一基板穿孔具有一深寬比為約2至約15，且該第二基板穿孔具有一深寬比為約5至約15。
  8. 如申請專利範圍第6項所述之半導體裝置結構，尚包括：一內連線結構，形成在該第二半導體晶圓之該前側。
  9. 一種半導體裝置結構之製法，包括以下步驟：提供一第一半導體晶圓與一第二半導體晶圓，其中該第一電晶體形成在該第一半導體晶圓之一前側，且沒有任何裝置形成在該第二半導體晶圓中；接合該第一半導體晶圓之該前側至該第二半導體晶圓之一背側； 薄化該第二半導體晶圓之一前側；形成一第二電晶體在該第二半導體晶圓之該前側；以及形成至少一第一基板穿孔(TSV)在該第二半導體晶圓之中，其中該第一基板穿孔直接接觸該第一半導體晶圓之一導電特徵結構。
  10. 如申請專利範圍第9項所述之半導體裝置結構之製法，尚包括：形成至少一第二基板穿孔在該第一半導體晶圓之中與該第二半導體晶圓之中，以直接接觸形成在該第一半導體晶圓之一背側上的一重新佈線(RDL)結構。
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