TW201436171A - 具有嵌入微電子元件的載體上主動晶片或疊層晶片 - Google Patents

具有嵌入微電子元件的載體上主動晶片或疊層晶片 Download PDF

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TW201436171A
TW201436171A TW103115684A TW103115684A TW201436171A TW 201436171 A TW201436171 A TW 201436171A TW 103115684 A TW103115684 A TW 103115684A TW 103115684 A TW103115684 A TW 103115684A TW 201436171 A TW201436171 A TW 201436171A
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Taiwan
Prior art keywords
wafer
cavity
channel
front surface
active
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TW103115684A
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English (en)
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TWI570885B (zh
Inventor
Vage Oganesian
Ilyas Mohammed
Craig Mitchell
Belgacem Haba
Piyush Savalia
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Tessera Inc
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Publication of TWI570885B publication Critical patent/TWI570885B/zh

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Abstract

本發明係關於一種結構，其包括第一半導體晶片，該第一半導體晶片具有前表面及後表面及該後表面中之空腔。第二半導體晶片安裝在該空腔內。該第一晶片可具有自該空腔延伸至該前表面的通道及此等通道內用於將額外微電子元件連接於該第一晶片之主動元件的通道導體。該結構可具有與單獨之第一晶片體積類似的體積，但提供多晶片總成之功能。併有主體及安裝於該主體之前表面上之半導體材料層的複合晶片可類似地具有自後表面延伸至該主體中的空腔，且可具有安裝於該空腔中之額外微電子元件。

Description

具有嵌入微電子元件的載體上主動晶片或疊層晶片
本發明係關於諸如半導體晶片之微電子元件及併有其之結構。
習知半導體晶片藉由於結晶晶圓(例如矽晶圓)上形成主動半導體元件(諸如電晶體及併有其之電路)來製造。主動器件由諸如磊晶生長、摻雜及其類似方法之方法形成以於晶圓前表面上在極薄層(通常數微米厚或更薄)中形成主動器件。其他元件(諸如導體及電阻器)亦可於晶圓上主動層內或接近主動層之其他層中形成。主動層可包括多個元件子層。晶圓另外具有電連接於主動層中之組件的導電接點。晶圓通常具有位於主動層上且覆蓋晶圓中除接點以外之前表面的惰性層，通常稱作「鈍化」層。隨後將該晶圓切割成個別半導體晶片，其各自併有晶圓之一部分，包括適當電路及與其連接之電接點。因此，各晶片具有對應於晶圓前表面之前表面及對應於晶圓原始後表面之面向相對方向的後表面。主動元件及其他功能組件置於接近晶片前表面之薄主動層中，且接點暴露在晶片前表面。晶片之大部分厚度由原始晶圓之惰性材料佔據。
半導體晶片通常安裝於電路面板上，其中晶片前表面或後表面面向電路面板且一般平行於電路面板表面延伸。晶片可如此安裝於電路 面板。然而，最常在稱作晶片封裝之結構中或該結構上提供晶片。晶片封裝可在物理上保護晶片且可提供在晶片之接點與電路板之導電元件之間形成互連的導電特徵。
在晶片之任何物理配置中，尺寸為重要考慮因素。隨著攜帶型電子器件之快速發展，對晶片之更緊密物理配置的需要變得愈加強烈。僅舉例而言，通常稱作「智慧型手機」之器件整合蜂巢式電話與強大資料處理器、記憶器件及輔助器件(諸如全球定位系統接收器、電子相機及區域網路連接以及高解析度顯示器及相關圖像處理晶片)之功能。該等器件可提供如下能力，諸如完整網際網路連接、娛樂(包括全解析度視訊)、導航、電子銀行業務及更多能力，所有均於袖珍器件中提供。複合攜帶型器件需要於小空間中裝入多個晶片。此外，一些晶片具有許多輸入及輸出連接，通常稱作「I/O's」。此等I/O's必須與其他晶片之I/O's互連。該等互連應較短且應具有低阻抗而使信號傳播延遲降至最低。形成互連之組件不應極大地增加總成之尺寸。其他應用中產生類似需求，例如資料伺服器，諸如網際網路搜尋引擎中所用之資料伺服器。舉例而言，在複合晶片之間提供多個低阻抗短互連的結構可增加搜尋引擎之頻寬且減少其功率消耗。
已作出許多努力以減小晶片及經封裝晶片在平行於晶片前表面及後表面之水平維度(亦稱作「X」方向及「Y」方向)上的尺寸，以便使晶片或經封裝晶片所佔據之電路板面積降至最低。亦使用所謂「堆疊」晶片配置。在堆疊晶片配置中，複數個晶片彼此相疊安置，使得堆疊沿垂直方向延伸。該堆疊可藉由於單個封裝中提供多個晶片隨後將該封裝安裝於電路板上，或藉由提供多個晶片封裝，該等晶片封裝經配置使得晶片封裝可以彼此相疊方式堆疊而形成。此配置使各種晶片在水平方向上所佔據之總面積降至最低，但增加總成高度或垂直尺寸(亦稱作「Z」方向)。堆疊配置應提供簡單且有效的方式在各晶片之間產生垂直連接。形成垂直互連 之組件理想上不應極大地增加總成之體積。
按常規，多個晶片之任何集合體所佔據之體積不小於個別未封裝晶片體積之總和且通常大很多。長期以來，已認識到個別未封裝晶片之體積及因此併有該晶片之任何總成的體積可藉由減小晶片厚度而減小。如上所述，個別晶片之大部分厚度由原始晶圓之惰性材料佔據。因此，此項技術中之常見操作為藉由在將晶圓切割成個別晶片之前或之後自晶片後表面移除晶圓之一些惰性材料而使晶片「薄化」。在現行操作中，使一些晶片薄化至約100至200微米。然而，該薄化製程不能無限持續。儘管晶片之電學主動組件容納於前表面之薄層內，但該晶片仍必須具有足夠厚度以在處理及加工期間提供物理穩定性。此外，簡單地使晶片薄化不減小由晶片與封裝之間或晶片與堆疊配置中其他晶片之間互連所佔據的體積。
本文中稱作「複合晶片」之結構包括具有面向相對方向之前表面與後表面且類似於習知半導體晶片主體的主體，且包括結合於主體前表面之個別形成之半導體層。半導體層可為相當薄(例如厚度為約10微米或小於10微米)之層。該複合晶片可例如藉由於第一半導體晶圓之前表面上形成主動層且使該晶圓之前表面結合於第二半導體晶圓(亦稱作「載體晶圓」)製成。使第一半導體晶圓薄化使得僅留下在載體或第二晶圓前表面適當位置處包括主動層之極薄半導體層，從而形成複合晶圓。隨後將複合晶圓切割成個別複合晶片。將具有此性質之結構例如用於所謂「後表面照明」圖像感應器中。在該結構中，半導體層中之主動組件包括光敏組件。光敏組件曝露於照射在半導體層背對載體或主體之表面上的光。複合晶片可與例如普通半導體晶片聯合使用，且可以大體上類似於安裝及封裝普通晶片之方式安裝及封裝。
儘管在此項技術中所有努力均致力於安裝及封裝晶片，但仍需要其他改良。
本發明之一態樣提供一種微電子結構，其包括第一半導體晶片，該半導體晶片具有含面向相對方向之前表面與後表面的主體及自後表面延伸至主體中之空腔。該第一晶片適宜具有置於與前表面相鄰之主動層中與主體形成整體的主動電路元件。本發明此態樣之結構亦包括置於空腔內之額外微電子元件。該結構整體上較佳界定實質上平坦的結構後表面，其包括第一半導體晶片之後表面。舉例而言，第一晶片在空腔內可具有面向後方之空腔底表面及限定空腔且自空腔底表面向後突出至第一半導體晶片之後表面的壁。額外微電子元件可具有置於第一晶片空腔內且面向前方朝向空腔底表面之前表面。結構後表面可包括第一晶片及第二晶片之後表面，該等後表面彼此共平面。或者或另外，結構後表面可包括第一晶片後表面及密封材料。
第一晶片可包括自空腔底表面向前延伸至第一晶片中的通道。此等通道可包括空腔底表面附近相對大直徑第一部分及遠離空腔底表面之相對小直徑第二部分。第一晶片可在遠離空腔底且接近第一晶片前表面之主動層中包括主動元件。通道之第二部分適宜延伸穿過主動層。因為通道之第二部分適宜具有相對小直徑，故其可在第一晶片之主動元件之間延伸。第一晶片之主動元件適宜提供於實質上整個晶片區域，包括位於空腔上之晶片區域。因此，本發明某些實施例之結構可在通常單個晶片佔據之體積內提供複數個晶片之功能。
在通道內延伸之通道導體可在額外微電子元件與第一晶片之間提供連接。在另一態樣中，額外微電子元件可具有暴露在該元件之上表面且電連接於第一晶片中至少一些通道導體之上接點，且亦可具有暴露在額外微電子元件之下表面的下接點。額外微電子元件可具有延伸穿過其之通道及此等通道內之通道導體。如下文進一步論述，此結構及下述其他 結構可提供穿過整個結構之連接。本發明某些態樣之結構可以彼此相疊之方式堆疊。
本發明之另一態樣提供複合晶片，其併有具有前表面及後表面之主體及併有安裝於主體前表面上之主動元件的半導體材料層。該主體具有自後表面延伸至其中之空腔，且額外微電子元件安裝於主體內。主體亦適宜具有延伸穿過其之通道，例如在包圍空腔之壁中，且額外微電子元件可經由此等通道電連接於半導體層。本發明此態樣之結構可用於例如提供具有光敏功能之極緊密總成。
本發明之其他態樣提供如下系統，其併有本發明上述態樣之微電子結構、本發明上述態樣之複合晶片或兩者，與其他電子器件之聯合。舉例而言，該系統可置於單個外殼中，該外殼可為攜帶型外殼。本發明此態樣之較佳實施例的系統可比類似習知系統緊密。
本發明之另一態樣提供製造方法。
20‧‧‧第一半導體晶片/第一晶片
22‧‧‧主體
24‧‧‧前表面
26‧‧‧後表面
28‧‧‧主動元件
30‧‧‧主動層
32‧‧‧鈍化層
34‧‧‧接點
36‧‧‧空腔
38‧‧‧底表面
40‧‧‧壁
42‧‧‧內表面
44‧‧‧底表面鈍化層/底表面介電層
48‧‧‧通道
50‧‧‧第一部分
52‧‧‧第二部分
54‧‧‧通道導體
56‧‧‧底表面墊
58‧‧‧前表面墊
60‧‧‧襯層/端子
62‧‧‧凸塊
64‧‧‧焊接/共熔結合材料
70‧‧‧第二微電子元件/第二晶片
72‧‧‧主體/晶片
74‧‧‧上表面
76‧‧‧下表面
78‧‧‧主動元件
82‧‧‧上表面鈍化層
84‧‧‧接點
86‧‧‧密封材料
88‧‧‧密封材料表面
102‧‧‧載體
104‧‧‧暫時結合層
106‧‧‧連續平坦後表面
108‧‧‧邊界
120‧‧‧晶圓
124‧‧‧前表面
220‧‧‧第一晶片
226‧‧‧後表面
236‧‧‧空腔
270‧‧‧第二晶片
288‧‧‧密封材料表面
302‧‧‧通道
304‧‧‧通道導體
306‧‧‧墊
308‧‧‧再分配跡線
310‧‧‧端子
320‧‧‧第一晶片
328‧‧‧特徵
354‧‧‧通道導體
360‧‧‧端子
370‧‧‧第二晶片
374‧‧‧上表面
376‧‧‧下表面
378‧‧‧主動元件/特徵/主動層
400‧‧‧結構
402‧‧‧通道
404‧‧‧通道導體
405‧‧‧再分配導體
406‧‧‧接點/端子
407‧‧‧向後再分配跡線/向後再分配導體
409‧‧‧墊/後表面端子
413‧‧‧墊/前表面端子
415‧‧‧再分配導體/再分配跡線
419‧‧‧導電結合物
420‧‧‧第一晶片
421‧‧‧短跡線
424‧‧‧前表面
426‧‧‧後表面
431‧‧‧焊接結合物
436‧‧‧空腔
438‧‧‧底表面
440‧‧‧壁
442‧‧‧壁表面/內表面
448‧‧‧通道
454‧‧‧通道導體
470‧‧‧第二晶片
474‧‧‧上表面
480‧‧‧密封材料
491‧‧‧電路面板
493‧‧‧導電墊
502‧‧‧通道
503‧‧‧通道
504‧‧‧通道導體
505‧‧‧底表面再分配跡線
510‧‧‧後表面端子
515‧‧‧上表面再分配跡線
520‧‧‧第一晶片
536‧‧‧空腔
570‧‧‧第二晶片
578‧‧‧特徵
586‧‧‧密封材料
588‧‧‧表面
602‧‧‧第二半導體晶片/總成
604‧‧‧空腔
606‧‧‧第三半導體晶片
608‧‧‧通道導體
610‧‧‧導電結合物
620‧‧‧第一半導體晶片
623‧‧‧前表面
625‧‧‧後表面
636‧‧‧空腔
670‧‧‧第二微電子元件
702‧‧‧半導體層
704‧‧‧導電元件
706‧‧‧導電元件
708‧‧‧黏著層
710‧‧‧前表面/通道/層
712‧‧‧通道導體/端子/墊/導電特徵
720‧‧‧複合晶片
722‧‧‧主體
724‧‧‧前表面
726‧‧‧後表面
728‧‧‧主動元件/光敏主動元件
733‧‧‧額外導電元件/額外導電特徵
735‧‧‧端子/導電特徵
736‧‧‧空腔
738‧‧‧底表面
739‧‧‧鈍化層
770‧‧‧第二半導體晶片
774‧‧‧上表面
776‧‧‧接點
777‧‧‧下表面
778‧‧‧內部組件
791‧‧‧微透鏡
793‧‧‧彩色濾光片
795‧‧‧透明板
797‧‧‧框架/間隔元件
850‧‧‧第一部分
852‧‧‧第二部分
853‧‧‧部分
854‧‧‧導體部分
859‧‧‧理論直線
900‧‧‧系統
901‧‧‧外殼
902‧‧‧電路面板
904‧‧‧導體
906‧‧‧結構
908‧‧‧其他電子組件
910‧‧‧其他電子組件/螢幕
911‧‧‧透鏡
圖1為本發明一實施例之結構的圖解剖視圖。
圖2為圖1結構中所用晶片的圖解平面圖。
圖3為圖1及圖2中所示晶片之一部分的部分斷裂剖面圖解圖。
圖4為圖1至3之晶片之一區域的部分斷裂剖面透視圖。
圖5為描述在本發明另一實施例之方法中，在製造階段圖1所示結構之元件的斷裂圖解剖視圖。
圖6、7及8為類似於圖1但描述本發明其他實施例之結構的圖。
圖9為描述圖8及圖9所示結構之特徵的示意性平面圖。
圖10為描述併有複數個圖及圖9所示結構以及其他組件之 總成的斷裂圖解剖視圖。
圖11為類似於圖1但描述本發明另一實施例之結構的圖。
圖12為描述本發明另一實施例之結構的示意性剖視圖。
圖13為描述本發明另一實施例之結構的圖解剖視圖。
圖14為描述本發明另一實施例之結構之部分的斷裂圖解透視圖。
圖15為本發明一實施例之系統的示意性描述。
本發明一實施例之微電子結構(圖1)包括具有主體22的第一半導體晶片20，主體22具有面向前方朝向圖1中圖式上部的前表面24，及面向相對之後方的後表面26。後表面26一般平行於前表面24。平行於前表面24之方向在本文中稱作「水平」方向，且在本文中亦稱作「X」及「Y」方向；而垂直於前表面之方向在本文中稱作向前方向及向後方向，且在本文中亦稱作「垂直」或「Z」方向。本文提及之方向處於所提及結構之參考座標中。因此，此等方向可位於法線或重力參考座標之任何定向。主體22包括在圖1中以28示意性表示的主動電路元件。主動電路元件28置於與主體前表面24相鄰的相對薄層中。主動電路元件可包括諸如電晶體、二極體及其他元件之器件及併有其之電路。當然，為清楚說明，在圖1中極大放大主動電路元件之尺寸。通常，主動電路元件具有約數微米或更小之尺寸。
主動電路元件與主體22形成整體。舉例而言，主體22可由結晶材料形成，而主動電路元件可藉由諸如於結晶材料上磊晶沈積之方法形成。僅舉例而言，晶片可為習知矽晶片，其中主體由矽形成且主動電路元件包括摻雜矽於主體之矽上磊晶生長。或者，形成主體之主要部分與主動元件之結晶材料之間可能存在顯著組成差異，例如其中主體由藍寶石或碳化矽形成，而主動電路元件由III-V半導體(諸如GaAs、GaN)形成。將主 動電路元件置於與主體前表面24相鄰的主動層30中。主動層可包括彼此垂直地疊加之主動元件。主動層通常亦包括多個被動元件，諸如導體、電阻器、電容器及電感器，且可包括界定主動元件之間的複合互連(未示)的導電及絕緣元件。主體22亦包括至少覆蓋晶片之主動元件且通常在整個前表面上延伸的鈍化層32。鈍化層32可例如藉由生長氧化物或氮化物層而與主體成為整體而形成，或可包括不連續層，諸如聚合物介電質，例如旋塗聚醯亞胺。晶片內之一些或所有主動元件可直接或間接連接於暴露在沿前表面之點處的金屬化物(metallization)。金屬化物形成可用於連接主動元件與外部電路元件的接點34。金屬化物可置於鈍化層32之後且經由鈍化層中之孔暴露於前表面，或可向前延伸穿過鈍化層中之孔，如圖1所述。
第一晶片20具有自後表面26延伸至主體22中之空腔36。該空腔具有面向後方之底表面38。主體22界定自底表面38向後延伸至後表面26的壁40。如最佳在圖2中可見，壁40限定空腔36及底表面38之相對側。在圖1及圖2所示之特定實施例中，有四個壁限定空腔36之所有四個側面從而完全環繞空腔。然而，在其他實施例中，僅有兩個壁40置於空腔之兩個相對側。各壁40具有向內面向空腔36之內表面42。內表面在水平方向上彼此遠離傾斜，使得空腔在底表面38至後表面26之向後方向上之水平尺寸增加。後表面26由壁遠離底表面38的末端界定。除空腔以外，後表面26一般適宜為平坦的。主體22可在底表面22上具有覆蓋主體之結晶材料的介電層，諸如聚合物介電質44。
如在底表面38上所量測，空腔可佔據晶片面積之實質部分，通常約25%或大於25%，且在一些情況下50%或大於50%。除非另外規定，否則如本文所用之晶片特徵之「面積」為在水平面中之面積。因此，空腔面積可視為底表面38之面積，而晶片面積可視為在水平面中可見之整個晶片面積，亦即前表面24或後表面26之總面積，包括空腔及壁所佔據的 面積。主體22之厚度(亦即前表面24與後表面26之間的距離TF)可視需要選擇，但通常小於約200微米以提供相對緊密之總成。如沿垂直方向自底表面28至後表面26量測的空腔深度DC可為厚度TF之實質部分，使得主體22中位於空腔36及底表面38上之區域形成在壁40之間延伸的相對薄的膜片樣結構。如在前表面24與底表面28之間量測的膜片厚度TD可僅略大於主動層30之厚度。舉例而言，td可為約25微米至50微米。壁40可用於加強薄膜片且在整體上限制第一晶片沿垂直於前表面24之水平面的方向彎曲。併入壁40中之材料相較於在整個晶片區域上以均勻厚度層形式分佈的等體積材料提供顯著較大之加強來對抗該彎曲。
第一晶片20具有自空腔底表面38延伸至主體22中之通道48。如本發明所用之術語「通道」係指主體材料中之垂直延伸開口。圖1中所述之通道延伸穿過主體之膜片部分從而延伸至前表面鈍化層32且穿過該層。然而，此並非必需；一些或所有通道可在前表面鈍化層下或在主體自身之半導體材料內終止。主動層30在晶片之膜片部分內延伸使得一些或所有主動電路元件置於主體之膜片部分中且位於空腔36上。換言之，一些或所有主動元件28可經安置使得自此等元件沿向後方向繪製之線將穿過空腔。至少一些通道48延伸至主動層30中及穿過主動層30且在主動元件28之間延伸。置於主動層30內之通道48之彼等區域適宜具有相對小之直徑，較佳小於約50微米且更適宜約1至約20微米。此使主動層內通道所佔據之面積降至最低且從而使得主動層中所需特徵(包括主動元件及傳輸導體(routing conductor))緊密置放。較佳地，各通道具有與空腔底表面36相鄰安置的第一部分50及在主動層30內延伸的第二部分52，該第二部分之直徑或水平方向上之尺寸小於第一部分之直徑或水平尺寸。通道及通道導體可藉由諸如以下中更詳細揭示之方法形成：標題為「MICROELECTRONIC ELEMENTS HAVING METALLIC PADS OVERLYING VIAS」、 「MICROELECTRONIC ELEMENTS WITH REAR CONTACTS CONNECTED WITH VIA FIRST OR VIA MIDDLE STRUCTURES」、「METHOD OF FORMING SEMICONDUCTOR ELEMENTS USING MICRO-ABRASIVE PARTICLE STREAM」、「NON-LITHOGRAPHIC FORMATION OF THREE-DIMENSIONAL CONDUCTIVE ELEMENTS」及「MICROELECTRONIC ELEMENTS WITH POST-ASSEMBLY PLANARIZATION」且與本發明同一日期申請的同在申請中共同受讓之美國專利申請案及已公開之美國專利申請公開案第20080246136號，其揭示內容以引用的方式併入本文中。舉例而言，第二部分52可藉由經小心控制之高精密方法(諸如反應離子蝕刻或其類似方法)由通道前表面開始形成；而第一部分50可藉由相對粗略的方法(例如機械方法，諸如噴砂)由半導體主體之相對表面開始形成。使用該粗略方法使得可快速移除主體之材料從而使與通道形成有關之成本降至最低。在以引用的方式併入本文中的上述應用中所揭示的其他實施例中，可形成通道之第一部分，且塗佈於第一部分內之暫時層或永久層可充當蝕刻通道之第二部分的遮罩。因為第一部分50位於主動層30之後，故第一部分50所佔據之區域仍可用於置放主動層內之組件。又，第一部分50無需為避開主動層內之特徵而精確置放。通道之任一部分或兩部分可在用於製造主動層內之結構的製程之前或之後形成。
由導電材料(例如金屬，諸如銅)形成之通道導體54在各通道48內延伸。各通道導體54在與底表面38相鄰之底表面連接墊56(圖1及圖4)中終止。通道導體之前端於與主體前表面24相鄰的前表面連接墊58中終止。如最佳在圖4中可見，各通道導體之底表面墊56與通道之第一部分50對準，使得墊56之周邊位於通道第一部分50之周邊內。在其他配置中，若墊56具有較大直徑，則該等墊可在某種程度上在通道外與底表面38重疊。在前表面之墊58亦與通道開口對準。襯層60(圖1)置於各通道內且 包圍通道導體54。襯層60適宜由彈性模數低於構成主體22之材料的材料、最佳介電材料(諸如聚合物)形成。襯層之聚合物可與構成鈍化層32及底表面鈍化層44之聚合材料混合。底表面墊56暴露在空腔底表面38。舉例而言，墊56可置於鈍化層44面向後方之表面上或可埋於鈍化層內但經由鈍化層中之孔暴露。類似地，前表面墊58可暴露在主體之前表面24上。
如以引用的方式併入本文中的應用中進一步論述，低模數介電襯層至少在某種程度上使通道導體54及墊56及58與主體之相對硬性材料機械分離，且因此減小由通道導體及主體之不同熱膨脹及熱收縮特徵所致之局部應力。舉例而言，若通道導體為金屬且熱膨脹係數大於主體22，則會限制與主體材料接觸之通道導體沿水平方向膨脹。因此，當加熱總成時，例如在操作期間或在製造程序(諸如焊接結合)期間，通道導體將趨向於以更大程度沿垂直方向膨脹。此大程度垂直膨脹趨向於破壞墊且破壞與其他總成之結合。相比之下，若提供襯層，則通道導體可徑向膨脹及收縮，從而使沿垂直方向之膨脹程度減小。此外，因為通道導體及墊與主體至少部分機械分離，故通道導體及墊可在某種程度上在外部施加之負荷(例如結合於墊之其他元件施加之負荷)影響下移動。此趨向於減小其他元件與墊之間結合之應力。
在第一晶片20之前表面24上提供適用於連接於較大組件的端子60。在所示特定實施例中，各端子包括在前表面上經由介電材料形成之凸塊或突出件62支撐的金屬墊。此介電材料可與前表面鈍化層32具有相同組成，或可為不同材料，諸如具有較低彈性模數的材料。端子60可具有結合冶金材料(metallurgy)，例如焊接或共熔接合材料64。
端子60、通道導體54及主動層30中之元件(諸如主動元件28)視電路功能需要彼此互連。舉例而言，一些或所有前表面墊58可藉由沿晶片前表面延伸且延伸至凸塊62上的跡線66連接於一些或所有端子60。 又，一些或所有前表面墊可藉由沿前表面延伸至接點34之額外跡線連接於主動元件28。該等跡線可以與前表面墊成為整體之形式形成或以各別元件形式形成。在本文中稱跡線「沿」前表面延伸而不一定在最終暴露表面處。舉例而言，跡線可在前表面鈍化層24之最終暴露表面上，在鈍化層內或在鈍化層與主體22之間。在另一配置(未示)中，在前表面後方終止之通道導體可藉由跡線連接於主動層內之內部組件或晶片之其他導電組件。
該總成另外包括第二微電子元件70，在此情況下其為第二半導體晶片，該第二半導體晶片具有含一般平坦的上表面74及面向相對方向之一般平坦的下表面76的主體72。第二晶片70包括置於接近上表面74之主動層中的主動元件78。如同第一晶片，主動層亦可包括諸如被動組件、導體及絕緣體之元件。第二晶片可在上表面74上包括上表面鈍化層82及暴露在上表面74之導電接點84。接點可在鈍化層82背對主體72之表面上，或可在鈍化層內或在鈍化層下且經由鈍化層中之開口暴露。
第二晶片70置於空腔36內，其中第二晶片之上表面74面向關於第一晶片向前之方向從而面向空腔之底表面38。第二晶片之接點84與一些或所有底表面墊58對準且結合於一些或所有底表面墊58。因此，第二晶片內之主動元件78經由接點84及通道導體54電連接於第一晶片之前表面24上載有的端子60，且亦連接於第一晶片之主動層30內的主動元件28及其他組件。
第二晶片之接點84藉由提供良好物理連接及良好電連接的任何適合結合冶金材料結合於第一晶片之底表面接觸墊56。舉例而言，可使用焊接結合、共熔結合及其類似結合。
第二微電子元件之下表面76與第一晶片或微電子元件之後表面26實質上共平面。換言之，第二晶片或額外微電子元件之厚度，亦即上表面74與下表面76之間的距離等於或略小於空腔36之深度DC。密封材 料86填充空腔內第二微電子元件或晶片70周圍之空間，且該密封材料界定實質上與第一晶片之後表面26及第二晶片之下表面76共平面的小表面86，使得密封材料及晶片共同界定面向第一微電子元件之前表面24之相對方向的實質上連續平坦表面。
第一晶片20總厚度TF適宜接近在製造及處理中達成物理穩定性所需之最小厚度。第二晶片70之厚度必需小於TF。然而，因為第二晶片70安裝在空腔內，故其受第一晶片物理保護。如下所述，在接近製造製程結束時在第二晶片已安裝在空腔內且固定在適當位置之後，第二晶片70可薄化至其在成品總成中具有的厚度。此時，第二晶片由第一晶片且由周圍之密封材料物理上加強。換言之，第二晶片70之厚度可小於當第二晶片以各別獨立晶片形式提供時該第二晶片達成物理穩定性所需的厚度。舉例而言，第二晶片之厚度可小於約100微米，例如小於約50微米或約5至約50微米。
密封材料86適宜在第一晶片與第二晶片之間形成物理結合，使得第二晶片與第一晶片機械連接。此連接無需為硬性連接。密封材料86之彈性模數可低於構成晶片之材料的彈性模數。此外，第二晶片之接點84與第一晶片之底表面墊56之間的電互連亦於第一晶片與第二晶片之間提供機械連接。
儘管密封材料86展示為與底表面鈍化層44及上表面鈍化層82分離且插在此等鈍化層之間，但鈍化層可彼此接觸且可直接彼此結合，例如在鈍化層具有黏著特性或可達成鈍化層彼此結合之狀態的情況下。在該情況下，晶片72之邊緣周圍可能仍存在或可能不存在一些各別密封材料。
該結構整體包括第一晶片與第二晶片之功能。因為第一晶片之主動元件可在實質上第一晶片之整個區域上延伸，故第一晶片之水平尺寸可與所形成之無通道及通道導體之類似第一晶片相同或略大。因此，整 個總成(包括第一晶片及第二晶片)之體積可與僅具有第一晶片功能之第一晶片之體積基本上相同或僅略大。
圖1所述之總成可藉由在晶圓120(圖5)上形成主動層30之主動元件及其他組件而製成。在製程之此階段，厚度TW或晶圓120之前表面與後表面之間的距離適宜略大於完成之總成中第一晶片之所要厚度TF(圖1)。晶圓120包括多個區域，其各自在成品總成中形成一個第一晶片20(圖1)。在圖5中為清楚說明，將此等區域描述為由邊界108分隔，但在製程之此階段無需存在實體邊界。在晶圓120之前表面124上或附近之主動層中形成主動元件及通常一些或所有其他組件之後，將前表面124暫時固定於載體102(圖5)，諸如具有顯著物理硬性及強度的額外晶圓或其他元件。晶圓120可藉由暫時結合層104固定於載體102。空腔36在晶圓之後表面中形成，較佳藉由諸如噴砂之機械技術形成。空腔形成步驟可在形成主動層及連接於載體102之前或更通常之後執行。
形成空腔36之後，完成通道48。可在此時形成整個通道48。或者，接近晶圓前表面124之通道第二部分52可與主動層之主動元件及其他特徵同時形成，且僅第一部分50可在形成空腔之後形成。如上所述，第一部分50可藉由諸如噴砂之機械方法形成。通道襯層60及底表面介電層44可藉由於空腔36及通道之第一部分中沈積介電材料形成。另外在此處，若通道之第二部分52較早形成，則通道襯層之一些部分可在製程之早期形成。可隨後形成通道導體54及在空腔底表面之結合墊56(圖1)。形成通道導體及底表面墊之後，將第二晶片70置於空腔36中，且電連接於底表面墊，且將密封材料86引入空腔中且固化。
密封材料固化之後，晶圓120、第二晶片70及密封材料86例如藉由機械研磨整個總成加工以自第二晶片、晶圓及密封材料之後表面移除材料，且使晶圓達到第一晶片之所要厚度。此方法形成連續平坦後表 面106，在圖5中以虛線指示。加工之後，晶圓120之各區域具有連續平坦後表面，如上關於圖1所述，包括第一晶片之後表面26、密封材料表面88及第二晶片70之下表面76。平坦化之後，將晶圓120自載體移出且沿個別晶圓之間的邊界108單一化或切開以使第一晶片彼此分離且形成如圖1所示之各別總成。該單一化可在自載體移出之前或之後執行。又，在單一化之前或之後，在第一晶片之前表面上形成諸如凸塊62及端子60之特徵。
圖6所示之總成類似於如上關於圖1至5所述之總成，例外為第二晶片270之厚度小於第一晶片220中空腔236之深度DC。因此，完成之總成的後表面由第一晶片之後表面226及由空腔236內之密封材料界定的密封材料表面288組成。此類型之總成可藉由類似於以上關於圖5所述之製程形成，例外為第二晶片270在置放於空腔236內之前薄化至其最終厚度。在此製程之一變化形式中，用於形成第一晶片220之晶圓亦可在置放第二晶片之前薄化至其最終厚度以在晶圓中形成第一晶片之後表面226。置放第二晶片之後，藉由處理密封材料，例如藉由在於空腔236內置放密封材料期間或之後處理密封材料來處理總成。舉例而言，可將後表面226與模具嚙合，且可引入液體形式之密封材料且模製形成與第一晶片後表面226共平面的密封材料表面288。或者，可將密封材料填充於空腔236中以突出超出第一晶片後表面226，且可使用相對軟的研磨劑對總成進行諸如拋光製程的製程，該研磨劑移除突出超出第一晶片後表面之密封材料但不移除晶片後表面自身之材料。
圖7之總成類似於圖1之總成，例外為第二晶片370具有自其上表面374延伸穿過其至其下表面376的通道302。通道302具有通道導體304。第二晶片之上表面374具有導電元件，諸如墊306及細長再分配跡線308。一些或所有此等導電特徵連接於第二晶片之主動層內的組件，例如連接於主動元件378及第二晶片之通道導體304。第二晶片370之下表面376 可具有端子310，其類似於第一晶片320之前表面上形成的端子360。另外在此處，第二晶片370之導電特徵(包括通道導體304)電連接於第一晶片320之通道導體354。兩個晶片之此等導電特徵可視需要彼此電互連以形成電互連之任何所要模式。電互連之模式可包括在第一晶片之通道導體354與第二晶片之通道導體304之間連接，且可連接第一晶片上之一些或所有端子360與第二晶片之端子310，以經由整個穿過總成延伸之連接提供複合物。晶片之一些或所有內部主動特徵(諸如特徵328及378)可連接於此等貫穿導體(through conductor)或第一晶片或第二晶片之端子。第二晶片之通道302、通道導體354及相關組件可類似於如以上關於圖1至4所述之通道48、通道導體54及相關組件。同樣在此情況下，通道之較大部分適宜置於第二晶片之主動層378後方。
如圖7所示之總成可藉由類似於上述程序的程序製造，其額外步驟為在第二晶片370與第一晶片320聯合之前或之後形成通道302之至少較大第一部分。舉例而言，可在晶圓及第二晶片經研磨或以其他方式處理形成總成之下表面之後形成與第二晶片370之下表面376相鄰的至少較大第一部分。又，可在將第二晶片組裝於第一晶片之後且適宜地在形成總成之下表面之後，在通道302中形成介電襯層及通道導體。如圖7所示之總成可以彼此相疊之方式堆疊，其中一個單元上之後表面端子310與下一單元上之上表面端子360對準且結合。該堆疊總成可連接於電路面板，諸如電路板，其係藉由將一個單元之端子310或360結合於電路板而達成。
另一實施例(圖8)之結構400大體上類似於上述結構。另外在此處，第一晶片420具有自後表面426延伸至晶片主體中的空腔436。第一晶片具有限定空腔之壁440，該等壁具有向內面向空腔之傾斜壁表面442。通道402自前表面424延伸穿過第一晶片420至後表面426。在此實施例中，通道延伸穿過壁440，但不穿過晶片位於空腔436上之膜片部分。此 等通道具有通道導體404、在第一晶片前表面上的墊413及在後表面上之墊409，該等墊電連接於通道導體。在此實施例中，墊413及409形成適用於連接於外部元件的端子。
另外在此處，空腔具有面向後方之底表面438。第一晶片具有一組沿空腔底表面438延伸之再分配導體405。此等再分配導體可與晶片之主體接觸或可在置於底表面上之鈍化層中或鈍化層上。再分配向後導體407沿壁440之內表面442延伸。此等再分配向後導體連接於晶片之後表面426上的端子409。一些或所有向後再分配導體407可連接於端子409從而連接於通道導體404。可在第一晶片之前表面及後表面上提供不與通道直接締合的額外端子(未示)，且一些或所有向後再分配導體可連接於後表面上之額外端子。
第二晶片470在其上表面474上具有電連接於第二晶片之內部組件的導電組件(諸如接點406)。第二晶片亦具有沿上表面474延伸之再分配導體415。另外在此處，再分配導體可在上表面上之鈍化層中或在鈍化層上。
再分配導體405及415藉由空腔內之密封材料480而在垂直方向上彼此間隔且彼此分離。因此，兩個晶片之再分配導體可彼此交叉而不會彼此接觸，或可如藉由施用於交叉點之結合材料而彼此連接。如最佳在圖9中可見，為清楚說明而以虛線描述之第一晶片之底表面再分配導體405主要沿第一水平方向(在本文中稱作「X」方向)延伸；而第二晶片之再分配導體415主要沿第二垂直水平方向(在本文中稱作「Y」方向)延伸。因此，再分配導體可藉由所選交叉點之導電結合物419選擇性地彼此連接。在圖9中，此等導電結合物由黑色矩形指示。第一晶片之底表面再分配導體415可與沿壁延伸之向後再分配跡線407連續。一些底表面再分配跡線可以沿第二或Y水平方向延伸之短跡線形式提供，此等跡線與亦沿Y或第二 水平方向延伸之向後再分配跡線407連續。此等短跡線421可藉由結合物419連接於第二晶片之上表面再分配跡線415。
如上文關於圖7所述之實施例，第二晶片之端子406及再分配導體415之一些或全部可連接於第一晶片之通道導體454。此外，第一晶片之再分配導體405及第二晶片之再分配導體415之一些或全部可連接於向後再分配導體407從而連接於第一晶片之壁中通道402的貫穿通道導體404。此配置使得在於結構內形成互連方面具有顯著通用性。舉例而言，再分配導體所提供之互連可用於在晶片420及470之一者或另一者內或在此等晶片之間傳輸信號。
如圖10示意性展示，單元400可堆疊形成複合總成，其中一個單元之後表面端子409如藉由焊接結合物431連接於下一相鄰單元之前表面端子413。在所示特定配置中，複合總成藉由將一個單元之後表面端子409結合於電路面板之導電墊493而連接於電路面板491。在其他配置中，前表面端子413可用於連接於電路面板。
另一實施例(圖11)類似於上述實施例，例外為空腔536內之密封材料586提供包圍第二晶片570之邊緣的相對廣區域，且通道502在此區域內形成。此等通道具有提供其他垂直連接之額外通道導體504。結構後表面上之一些端子510在由密封材料界定之表面588上提供。圖11中所述之特定結構無延伸穿過第一晶片520之通道。因此，特徵578(諸如第二晶片570之主動層中的主動元件)藉由通道502中之通道導體504連接於後表面端子510。沿第一晶片中之空腔536之底表面延伸的底表面再分配跡線505及沿第二晶片570之上表面延伸的上表面再分配跡線515將第二晶片之接點連接於通道導體504。與結構後表面上之端子510的額外連接可由延伸穿過第二晶片570中之通道503的額外通道導體提供。
在另一實施例中(圖12)，在第一半導體晶片620之空腔636 內提供的第二微電子元件670並非簡單半導體晶片。更確切地說，第二微電子元件670自身為如下結構：包括界定空腔604之第二半導體晶片602且其中接收第三微電子元件，諸如第三半導體晶片606。任何或所有上述特徵均可用於總成602。各種晶片之通道導體608可藉由導電結合物610以及藉由在各空腔底表面上及各晶片之上表面或前表面上延伸的再分配導體彼此互連。一些或所有該等互連可形成整個穿過總成、在總成之前表面623與後表面625(如圖12所示總成之上部及下部表面)之間延伸的連續導電路徑。各晶片之主動層中的任何或所有主動元件可彼此互連及與總成表面上之端子互連。此方法可進一步擴展以例如在晶片606中之空腔內提供第四半導體晶片。製造如圖12所示之總成的方法可大體上類似於上述方法。僅舉例而言，可藉由研磨或以其他方式同時處理第一晶片之後表面及晶片602及606之下表面以及空腔636及604中所含之密封材料使總成之後表面成為平坦狀態。
本發明另一實施例之結構包括複合晶片720(圖13)。複合晶片併有主體722，其可由結晶材料(例如矽)、多晶材料或部分結晶材料(諸如氧化鋁)或非晶材料形成。主體722具有面向相對方向之前表面724及後表面726。主體722具有在其後表面形成且自後表面延伸至主體中的空腔736。複合晶片另外包括結合於主體722之前表面724的半導體層702。半導體層702併有主動半導體元件，其藉由內部連接(未示)連接於暴露在層702之朝向後方之表面且面向主體722的導電元件704。此等導電元件又連接於沿主體722之前表面724延伸的導電元件706。導電元件706可包括多個各別跡線或墊。層702與主體722之間的結合示意性展示為黏著層708。或者，層702與主體722可藉由不涉及各別黏著層之方法，諸如擴散結合而彼此結合。在圖13所示之特定實施例中，一些主動元件728包括光敏元件，諸如光電二極體、光電晶體或光電導體。層702具有面向前方遠離主體722之前 表面710。層702之厚度TL足夠小以使照射於前表面710之光可穿過該層到達光敏主動元件728。舉例而言，層702厚度可為約15微米或小於15微米，通常厚度為約10微米或小於10微米。層702可形成比該層所要厚度厚很多之一般習知半導體晶圓之一部分。此晶圓可使用一般習知技術疊層於併有主體722之材料的另一晶圓。疊層之後，自併有半導體元件之晶圓移除材料以減小晶圓厚度且形成前表面710。
主體722併有在空腔736周圍延伸且限定空腔736的壁740。另外在此處，壁具有延伸穿過其之通道710及置於通道內之通道導體712。亦在此實施例中，通道710可為多直徑通道。因此，通道中接近主體前表面724之部分的直徑可比接近後表面726之通道部分小很多，且通道導體712同樣可具有沿通道之垂直範圍變化之直徑。通道導體712電連接於沿主體之前表面724延伸的導電元件706且因此電連接於半導體層702之導電元件704。通道導體712具有暴露在主體後表面726之端子712。
第二微電子元件(諸如第二半導體晶片770)置於主體之空腔736內。另外在此處，第二微電子元件具有含電連接於內部組件778的接點或其他導電元件的上表面774，且具有面向上部774之相對方向的下表面777。然而，在此實施例中，第二微電子元件之定向與上述定向相反。因此，第二微電子元件之上表面774面向關於複合晶片向後之方向，且因此背對空腔736之底表面738。第二微電子元件之接點776連接於位於密封材料736之表面上及位於主體之後表面726上的層中提供的額外導電元件733。一些此等額外導電元件可形成在第二微電子元件之接點與通道導體712之間延伸的互連或再分配跡線以在層702內之元件之間提供電互連。一些或所有額外導電元件733可形成其他端子735。端子735以及墊或端子712適宜經調適用於將結構表面安裝於電路面板(諸如電路板)。舉例而言，此等端子可具有大量導電結合材料，諸如焊料。該總成可另外包括位於主體後表面726 上及位於空腔736內之密封材料及第二微電子元件770上的鈍化層739。額外導電特徵733可置於此鈍化層內或此鈍化層上。另外在此處，當主體722為較大晶圓之一部分時，空腔736以及通道710可在將半導體層702結合於主體之前或之後形成。主體及空腔736內之密封材料可經處理而形成大體平坦表面，且導電特徵712、733及735可在此平坦表面上或在塗佈於平坦表面之鈍化層上形成。儘管可使用可用於形成導電特徵的基本上任何技術，但可使用如與本發明同一日期申請的同在申請中之標題為Non-Lithographic Formation of Three-Dimensional Conductive Elements的申請案中更詳細論述的非微影技術。該等非微影技術可包括例如用雷射或用機械方法(諸如研磨或噴砂)選擇性處理表面以沿導電元件以與表面之其他部分不同之方式形成的路徑處理彼等表面部分。舉例而言，可使用雷射或機械方法僅沿一路逕自表面去除或移除材料(諸如犧牲層)從而形成沿該路徑延伸之凹槽。諸如催化劑之材料可隨後在凹槽中沈積，且一或多個金屬層可在凹槽中沈積。
圖13之結構包括位於層702之前表面710上且與該層之光敏元件728對準的一系列微透鏡791及一系列彩色濾光片793。此等結構以習知方式改變照射於光敏元件上之光以使得形成表現彩色圖像之圖像資料。透明蓋795位於微透鏡及濾光片上。該蓋可在層702之前表面710上方藉由結合在該蓋與前表面710之間的框架或間隔元件797支撐。該蓋可在切斷晶圓形成圖13中所述之個別單元之前製造且施用於晶圓片(wafer scale)上。該蓋亦可包括透鏡或用於形成圖像之其他光學元件(未示)。因此，圖13之結構提供感應及處理圖像的整體緊密總成。僅舉例而言，第二晶片770可自層710接收構成圖像之原始資料，且處理原始資料，隨後經由電連接將資料轉移至電路之其他組件。
上述各特徵可彼此組合。舉例而言，可使用上文關於圖8 至10所述之底表面及上表面再分配導體405及415與第一晶片之後表面上或密封材料表面上的端子連接，無論結構是否具有圖10所示之延伸穿過限定空腔之壁的通道。第一晶片之壁中的通道402亦可有或無在第一晶片空腔底表面438與前表面424之間延伸的通道448，且有或無在第二晶片之前表面與後表面之間延伸的通道。
圖13所示之第二微電子元件或第二晶片770之定向可相反，使得第二晶片之上表面面向前方朝向空腔736之底表面。載體中之空腔736可如上關於圖8及圖9所述具有底表面及向後再分配導體或如圖11所示在密封材料中具有通道。或者或另外，如圖7中所述，第二晶片可具有內部通道。相反地，在上文關於圖1至12所述之結構中，第二微電子元件之定向可相反，使得第二微電子元件之上表面面向關於第一晶片向後之方向。在結構(諸如圖1之結構)中，若第二晶片之下表面暴露，則第二晶片可在接近上表面之主動層中包括光敏元件，且可經薄化，薄化程度使得照射於第二晶片之下表面上的光可到達此等光敏元件。
單個通道導體在各通道內延伸且由通道襯層60(圖1)包圍的特定通道結構可替換為其他結構。舉例而言，一些或所有上述通道可為「多對一(many-to-one)」通道。該通道各併有具有相對大直徑之第一部分850(圖14)及多個具有相對小直徑之第二部分852。該通道可具有多個導體，該等導體各包括位於通道之一個小直徑第二部分852內的部分853及延伸穿過第一部分850之另一部分854。導體部分854可形成沿通道壁或沿置於通道壁上之介電層(未示)延伸的跡線。跡線可呈彎曲或Z字形，使得各跡線具有如沿跡線量測比沿通道壁延伸的理論直線859長的長度。如上述同在申請中之申請案中更詳細論述，該等彎曲或Z字形跡線有助於減小跡線中之應力，否則可能因形成通道壁之半導體材料與構成跡線之金屬的熱膨脹差異而產生應力。以類似方式，沿空腔之傾斜壁延伸的向後再分配導體407(圖8及 圖9)可呈彎曲或Z字形以使此等導體中之應力降至最低。彎曲或Z字形導體或跡線可例如使用上述非微影方法形成以界定彎曲或Z字形路徑。
上述結構提供顯著的三維互連能力。此等能力可用於任何類型之晶片。僅舉例而言，上述結構中可包括晶片之以下組合：(i)處理器及與處理器一起使用之記憶體；(ii)複數個相同類型之記憶體晶片；(iii)複數個不同類型之記憶體晶片，諸如DRAM及SRAM；(iv)圖像感應器及用於處理來自感應器之圖像的圖像處理器；(v)特殊應用積體電路(「ASIC」)及記憶體。
上述結構可用於建構不同電子系統。舉例而言，本發明之另一實施例的系統900包括上述結構906與其他電子組件908及910之聯合。在所述實例中，組件908為半導體晶片，而組件910為顯示幕，但可使用任何其他組件。當然，儘管為清楚說明圖15中僅描述兩個額外組件，但系統可包括任何數目之該等組件。上述結構906可為例如如上關於圖13所述之複合晶片，或併有複數個關於圖1至12所述之晶片的結構。在另一變化形式中，可提供兩者，且可使用任何數目之該等結構。結構906及組件908及910安裝於用虛線示意性描述的常用外殼901中且視需要彼此電互連形成所要電路。在所示例示性系統中，系統包括電路面板902(諸如可撓性印刷電路板)，且該電路面板包括多個使組件彼此互連的導體904，其中在圖15中僅描述一個導體。然而，此僅為例示性的；可使用產生電連接之任何適合結構。外殼901描述為可例如用於蜂巢式電話或個人數位助理中之類型的攜帶型外殼，且螢幕910暴露在外殼表面上。若結構906包括感光元件(諸如成像晶片)，則亦可提供透鏡911或其他光學器件以向結構傳輸光。圖15所示之簡化系統亦僅為例示性的；可使用上述結構製造其他系統，包括通常視為固定結構的系統，諸如桌上電腦、路由器及其類似物。
因為在不背離本發明的情況下可使用上述特徵之此等及其他變化形式及組合，故上述較佳實施例之描述應視為說明性的而非限制由 申請專利範圍界定的本發明。
20‧‧‧第一半導體晶片/第一晶片
22‧‧‧主體
24‧‧‧前表面
26‧‧‧後表面
28‧‧‧主動元件
30‧‧‧主動層
32‧‧‧鈍化層
34‧‧‧接點
36‧‧‧空腔
38‧‧‧底表面
40‧‧‧壁
42‧‧‧內表面
44‧‧‧底表面鈍化層/底表面介電層
48‧‧‧通道
50‧‧‧第一部分
52‧‧‧第二部分
54‧‧‧通道導體
56‧‧‧底表面墊
58‧‧‧前表面墊
60‧‧‧襯層/端子
62‧‧‧凸塊
64‧‧‧焊接/共熔結合材料
70‧‧‧第二微電子元件/第二晶片
72‧‧‧主體/晶片
74‧‧‧上表面
76‧‧‧下表面
78‧‧‧主動元件
82‧‧‧上表面鈍化層
84‧‧‧接點
86‧‧‧密封材料
88‧‧‧密封材料表面

Claims (2)

  1. 一種微電子結構，其包含：(a)第一半導體晶片，其具有含面向相對方向之前表面與後表面之主體，及自該後表面延伸至該主體中之空腔，該第一晶片具有置於與該前表面相鄰之主動層中與該主體形成整體的主動電路元件，及(b)置於該空腔內之額外微電子元件，該結構界定實質上平坦之結構後表面，其包括該第一半導體晶片之該後表面。
  2. 一種微電子結構，其包含：(a)第一半導體晶片，其具有含面向相對方向之前表面及後表面之主體，暴露在該前表面之第一接點，自該後表面延伸至該主體中之空腔，該空腔具有面向後方之空腔底表面，該第一半導體晶片具有自該空腔底表面延伸至該第一晶片中之第一通道導體，及(b)置於該空腔內之額外微電子元件，該額外微電子元件具有面向該第一晶片之該空腔底表面的上表面，置於該上表面附近之主動層中之主動電路元件，及面向與該第一晶片之該後表面相同方向的下表面，該額外微電子元件具有暴露在該上表面且電連接於至少一些該等第一通道導體之上接點，該額外微電子元件具有暴露在該下表面之下接點。
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US20180130746A1 (en) 2018-05-10
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US8598695B2 (en) 2013-12-03
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US20140203452A1 (en) 2014-07-24
US10262947B2 (en) 2019-04-16

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