TW201431036A - 堆疊式封裝裝置及成型一堆疊式封裝裝置之方法 - Google Patents

堆疊式封裝裝置及成型一堆疊式封裝裝置之方法 Download PDF

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TW201431036A
TW201431036A TW102146831A TW102146831A TW201431036A TW 201431036 A TW201431036 A TW 201431036A TW 102146831 A TW102146831 A TW 102146831A TW 102146831 A TW102146831 A TW 102146831A TW 201431036 A TW201431036 A TW 201431036A
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Taiwan
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layer
wafer
bonded
conductive
die
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TW102146831A
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TWI509769B (zh
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Chin-Chuan Chang
Jing-Cheng Lin
Nai-Wei Liu
Wan-Ting Shih
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Taiwan Semiconductor Mfg
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    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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Abstract

一種成型一堆疊式封裝裝置之方法，包括：安置一黏著層於一載體底材之上；結合複數個晶片封裝於位於該載體底材上之該黏著層；安置一連結層於該等晶片封裝之上；結合複數個晶片於位於該晶片封裝上之該連結層；以一模鑄化合物封裝該等晶片封裝及位於該載體底材上之該等晶片；研磨該模鑄化合物以暴露該等晶片之複數個連接元件以及該等晶片封裝之複數個第二連接元件；成型一重分佈層於該模鑄化合物、該等連接元件及該等第二連接元件之上；成型一球型陣列於該重分佈層之上；以及剝離該載體底材。

Description

堆疊式封裝裝置及成型一堆疊式封裝裝置之方法
本發明是有關於一種堆疊式封裝裝置及成型一堆疊式封裝裝置之方法，特別是有關於一種成型一堆疊式封裝裝置之方法。
電子學能夠被區分成包括多種裝置之一簡單之階系，例如，積體電路(IC)晶片、封裝、印刷電路板(PCB)等。封裝是位於一電子裝置(例如，一電腦晶片)與一印刷電路板之間的介面。這些裝置是由半導體材料(例如，矽)所製成。積體電路(IC)晶片能夠被組裝成一封裝，例如，一四面扁平封裝(quad flat pack，QFP)、一針型陣列封裝(pin grid array，PGA)或一球型陣列封裝(ball grid array，BGA)。一封裝裝置是被直接附著於一印刷線路板或另外形式之底材，其是被定義為一第二級之封裝。
在球型陣列封裝(BGA)技術之中，一半導體或積體電路(IC)晶片是被固定於一底材之一前表面，以及複數個導電元件(例如，錫球)是以一矩形陣列(習慣上被稱為球型陣列封裝)被配置於底材之一背表面。球型陣列封裝(BGA)可允許半導體封裝被結合於或電性連接於一外部印刷電路板(PCB)或其他的電子裝置。球型陣列封裝(BGA)可以被運用於一記憶體元件之 中，例如，動態隨機存取記憶體(DRAM)以及其他的記憶體裝置。
堆疊式封裝(Package-on-Package，PoP)是一種積體電路封裝技術以允許垂直之結合，舉例來說，離散邏輯與記憶體球型陣列封裝。兩個或多個封裝是被安裝於彼此之上部(例如，堆疊)，有著一標準介面去發送訊號於它們之間。此可允許較高的密度於行動電話/智慧型電話市場之中。
本發明基本上採用如下所詳述之特徵以為了要解決上述之問題。
本發明之一實施例提供一種堆疊式封裝裝置，其包括一晶片封裝；一嵌入式晶片，結合於該晶片封裝；一重分佈層，結合於該晶片封裝以及該嵌入式晶片，其中，該嵌入式晶片係定位於該重分佈層與該晶片封裝之間；以及一球型陣列，結合於該重分佈層，其中，該重分佈層係定位於該球型陣列與該嵌入式晶片之間。
根據上述之實施例，該重分佈層係提供電性耦合於該球型陣列與該嵌入式晶片之間，而無需通孔。
根據上述之實施例，該重分佈層係提供電性耦合於該球型陣列與該晶片封裝之間，以及該重分佈層係定位於該球型陣列與該晶片封裝之間。
根據上述之實施例，該堆疊式封裝裝置更包括一模鑄化合物，係封裝該晶片封裝與該嵌入式晶片，其中，該模鑄化合物係位於該重分佈層之上，並且係圍繞該嵌入式晶片。
根據上述之實施例，該晶片封裝包括一底材；複數個晶片，堆疊於該底材之上；一模鑄化合物，封裝該等晶片，其中，該模鑄化合物係位於底材之上；複數個導電墊，位於該底材之兩側之上；複數個通孔，位於該底材之中，並且係結合於該等導電墊之間；複數個連結線，係被封入該模鑄化合物之中，並且係分別連結該等晶片於該等導電墊；以及複數個錫球，結合於位於該底材之一側上之該等導電墊，相對於被結合之該等晶片及該重分佈層。
根據上述之實施例，該嵌入式晶片包括一晶片；一連結層，連結該晶片及該晶片封裝；複數個導電墊，結合於相對於該連結層之該晶片之一表面；一鈍化保護層，結合於該晶片之該表面以及該等導電墊；以及一聚合物層，結合於相對於該晶片之該鈍化保護層之一表面。
根據上述之實施例，該連結層係為一黏著層或一熱介面材料。
根據上述之實施例，該重分佈層包括一第二聚合物層，結合於相對於該嵌入式晶片之該聚合物層之一表面；一導電層，結合於該嵌入式晶片之該等導電墊以及相對於該嵌入式晶片之該第二聚合物層之一表面；以及一第三聚合物層，結合於相對於該第二聚合物層之該導電層之一表面。
根據上述之實施例，該球型陣列包括複數個導電球，以及該等導電球係結合於相對於該嵌入式晶片之該重分佈層之一表面。
根據上述之實施例，該球型陣列之該等導電球係 透過複數個凸塊底層金屬化元件去結合於該重分佈層，以及該等凸塊底層金屬化元件係定位於該重分佈層與該球型陣列之間。
本發明之另一實施例提供一種堆疊式封裝裝置，包括一晶粒；一晶片，結合於該晶粒；一重分佈層，結合於該晶片，其中，該晶片係嵌入於該晶粒與該重分佈層之間；以及一球型陣列，結合於該重分佈層，其中，該重分佈層係提供電性耦合於該球型陣列、該晶粒以及該晶片之間，而無需使用通孔。
根據上述之實施例，該重分佈層具有相較於一層壓內連接層之一實質上降低之厚度，以及該重分佈層係被使用於連接該球型陣列於該晶片。
根據上述之實施例，該重分佈層具有等於或靠近毫米之一厚度。
本發明之又一實施例提供一種成型一堆疊式封裝裝置之方法，包括：安置一黏著層於一載體底材之上；結合複數個晶片封裝於位於該載體底材上之該黏著層；安置一連結層於該等晶片封裝之上；結合複數個晶片於位於該晶片封裝上之該連結層；以一模鑄化合物封裝該等晶片封裝及位於該載體底材上之該等晶片；研磨該模鑄化合物以暴露該等晶片之複數個連接元件以及該等晶片封裝之複數個第二連接元件；成型一重分佈層於該模鑄化合物、該等連接元件以及該等第二連接元件之上；成型一球型陣列於該重分佈層之上；以及剝離該載體底材。
根據上述之實施例，該成型一堆疊式封裝裝置之方法更包括：移除該黏著層。
根據上述之實施例，該等晶片係被嵌入至位於該等晶片封裝之該等第二連接元件之中。
根據上述之實施例，該等晶片封裝係利用一轉移層及一覆晶製程被轉移至及結合於該黏著層。
根據上述之實施例，該等晶片係利用一轉移層及一覆晶製程被轉移至及結合於該連結層。
根據上述之實施例，該成型一堆疊式封裝裝置之方法更包括：鋸開該等晶片封裝以及被封裝於該模鑄化合物之中及結合於該重分佈層與該球型陣列之該等晶片，以獲得具有一三維扇出結構之複數個堆疊式封裝裝置。
根據上述之實施例，成型該重分佈層之步驟包括：成型一導電層於該模鑄化合物、該連接元件以及該第二連接元件之上；圖刻該導電層；成型一聚合物層於被圖刻之該導電層之上；圖刻該聚合物層；成型複數個凸塊底層金屬化元件於被圖刻之該導電層及被圖刻之聚合物層之上；以及安置該球型陣列之複數個導電球於該凸塊底層金屬化元件之上。
為使本發明之上述目的、特徵和優點能更明顯易懂，下文特舉較佳實施例並配合所附圖式做詳細說明。
10‧‧‧晶粒
11‧‧‧第二模鑄化合物
12‧‧‧晶片
14‧‧‧連結線
15、23‧‧‧導電墊
16‧‧‧通孔
17‧‧‧內連部
18‧‧‧底材
20‧‧‧嵌入式晶片
21‧‧‧連結層
22‧‧‧矽晶片
24‧‧‧鈍化保護層
25‧‧‧模鑄化合物
26‧‧‧連接器元件
27‧‧‧第一聚合物層
30‧‧‧重分佈層
31‧‧‧第二聚合物層
32‧‧‧導電層
33‧‧‧第三聚合物層
39‧‧‧聚合物層
40‧‧‧球型陣列
41‧‧‧凸塊底層金屬化元件
42‧‧‧導電元件
50‧‧‧載體
60‧‧‧黏著層
100‧‧‧堆疊式封裝裝置
第1圖係顯示根據本發明之一實施例之一堆疊式封裝裝置之剖面示意圖，其中，堆疊式封裝裝置具有一三維(3D)扇 出結構；第2a圖至第2h圖係顯示根據第1圖之成型堆疊式封裝裝置之一製程。
茲配合圖式說明本發明之較佳實施例。
有關本發明之前述及其他技術內容、特點與功效，在以下配合參考圖式之一較佳實施例的詳細說明中，將可清楚的呈現。以下實施例中所提到的方向用語，例如：上、下、左、右、前或後等，僅是參考附加圖式的方向。因此，使用的方向用語是用來說明並非用來限制本發明。
第1圖係顯示根據一實施例之一堆疊式封裝裝置(package-on-package，PoP)100之剖面示意圖，其中，堆疊式封裝裝置100具有一三維(3D)扇出結構。舉例來說，堆疊式封裝裝置100可以對應於一記憶裝置或元件，例如，一動態隨機存取記憶體(DRAM)裝置或元件。堆疊式封裝裝置100可以包括有一晶粒10(或其他的晶片封裝)、結合於晶粒10之一嵌入式晶片20、封裝晶粒10與嵌入式晶片20之一模鑄化合物、結合於被封裝之晶粒10與嵌入式晶片20之一重分佈層30、以及結合於重分佈層30之一球型陣列40。堆疊式封裝裝置100之元件或層可以是相對於彼此被定位及堆疊，如第1圖所示。
晶粒10可以利用任何適當之半導體製程被成型與獲得。晶粒10可以包括有複數個堆疊晶片12，其可以具有不同之尺寸。堆疊晶片12可以包括有一或多個半導體層(例如，矽及/或其他半導體材料)、一或多個導電層、一或多個介電層或 其結合。堆疊晶片12可以被一第二模鑄化合物11所封裝以及被定位於一底材18之上。舉例來說，晶粒10可以包括有不同尺寸之兩個矽晶片，在底材18上堆疊於彼此之頂部上，並且從頂部及側邊被第二模鑄化合物11所圍繞。兩個堆疊晶片12及第二模鑄化合物11是被底材18所支撐。舉例來說，底材18可以是一矽底材(例如，一矽晶片)、一矽或玻璃插入物、一印刷電路板(PCB)或一有機層壓底材等。
晶粒10還可以包括有複數個導電墊15。導電墊15可以是定位於底材18之兩側之上，並且是經由通孔16連接跨過底材18。位於底材18之一側上之導電墊15(位於堆疊晶片12之側邊之上)可以是透過連結線14連接於堆疊晶片12。位於底材18之另一側上之導電墊15(相對於堆疊晶片12)可以是連結於複數個內連部17，例如以錫球或凸塊之形式呈現。連結線14、導電墊15及通孔16係提供電性結合於堆疊晶片12與內連部17之間。
嵌入式晶片20可以是成型於晶粒10之一表面之上，並且嵌入式晶片20可以包括有一矽晶片22(或其他的半導體晶片)及一連結層21。連結層21係連結矽晶片22於晶粒10之底材18。在一實施例之中，連結層21可以是一黏著層，其是由一黏膠或一層壓層所構成。在另一實施例之中，一熱介面材料可以被使用做為連結層21，以將矽晶片22連結於底材18。熱介面材料可以使用通孔而與堆疊晶片12接觸，以提供一熱傳導連接於矽晶片22與堆疊晶片12之間。熱介面材料可以是一熱漿糊，例如，具有熱傳導填充物(例如，氧化鋁及/或氮化硼)之一 矽橡膠。
嵌入式晶片20亦可以包括有成型於矽晶片22與重分佈層30間之一或多個金屬介電層。這些層可以提供一適當之電性連接於矽晶片22與重分佈層30之間，並且具有複數個導電墊23(例如，鋁或其他適當之金屬墊)、一鈍化保護層24及一第一聚合物層27，其可以被配置如第1圖所示。鈍化保護層24及第一聚合物層27可以是被圖刻的結構(不連續跨過表面)，以允許適當之結合於導電墊15與重分佈層30之間。
重分佈層30可以包括有一第二聚合物層31及一導電層32。第二聚合物層31可以是被成型或沉積至第一聚合物層27之上。導電層32可以是一金屬層，例如，鋁、銅、鈦、多晶矽或金層。重分佈層30亦可以包括有一第三聚合物層33。第三聚合物層33是被成型或沉積至導電層32之上。如上所述，重分佈層30之功能是要去提供電性連接於嵌入式晶片20與球型陣列40之間，而無需通孔之形成。第二聚合物層31、導電層32及第三聚合物層33可以被圖刻去允許適當之結合於導電墊15與球型陣列40之間，亦即，透過內連部17與導電層32之接觸，其係提供電性連接於導電墊15與球型陣列40之間。在一實施例之中，複數個凸塊底層金屬化(Under-Bump Metallization，UBM)元件41可以被成型於重分佈層30之表面之上，以將球型陣列40連結於嵌入式晶片20。凸塊底層金屬化元件41可以是結合於第三聚合物層33之表面部分以及導電層32。球型陣列40包括有複數個導電元件42，例如，導電球或微凸塊，其是以陣列方式被配置與凸塊底層金屬化元件41接觸。
如上所述，重分佈層30是被使用去結合晶粒10及嵌入式晶片20於球型陣列40。因此，重分佈層30能取代一層壓內連接層，其典型地是被使用去電性結合一晶片封裝於一球型陣列。使用重分佈層30實質上可以降低堆疊式封裝裝置100之整體厚度(於第1圖之垂直或上下方向中)。舉例來說，封裝晶粒10及嵌入式晶片20之模鑄化合物25可以具有一厚度等於或接近於550微米，球型陣列40可以具有一厚度等於或接近於240微米，當一層壓內連接層之一典型厚度大約是500微米或更多時。因此，使用重分佈層30可以降低三維扇出結構之整體厚度從大約1400微米至大約800微米，亦即，超過40%之降低。結構之降低厚度能致使較好的封裝與整合對於較小的裝置，例如，智慧型行動電話、平板電腦、筆記型電腦或其他的消費性裝置。再者，重分佈層30係提供電性結合於三維扇出結構之元件之間，而無需通孔之成型，其可促進製造以及降低成本。
第2a圖至第2h圖係顯示根據一實施例之成型堆疊式封裝裝置100之一製程。第2a圖係繪示一黏著層塗佈步驟，其中，一黏著層60可以被設置於載體50之上。黏著層60可以是由一黏膠或一層壓層所構成。載體50可以是任何適當之底材，其可提供機械支撐對於攜載三維扇出結構之複數個堆疊層。舉例來說，載體50可以是一矽底材(例如，一矽晶片)、一矽或玻璃插入物、一印刷電路板(PCB)或一有機層壓底材等。
第2b圖係繪示一第一晶片安置步驟，其中，複數個晶粒10可以被安置於黏著層60之上。在其他實施例之中，其他形式之晶片封裝於可以被安置於黏著層60之上。晶粒10可以 被成型於黏著層60之上或使用任何適當之方法被安置於黏著層60之上。在一實施例之中，晶粒10(無內連部17)可以附著於一轉移層或底材(未顯示)。轉移層可以被利用去安置晶粒10於黏著層60之上，例如，使用覆晶製程。晶粒10之安置可以藉由翻轉轉移層及定位晶粒10於黏著層60之上而被執行。在晶粒10已被翻轉及被安置於黏著層60之上後，轉移層可以被移除掉，例如，使用一剝除或蝕刻製程去從晶粒10移除轉移層之材料。內連部17然後可以與導電墊15被安置於晶粒10之表面之上。
第2c圖係繪示一第二晶片安置步驟，其中，複數個嵌入式晶片20可以被校直與安置於晶粒10之上。嵌入式晶片20可以被校直於晶粒10。如第2c圖所示，每一個嵌入式晶片20可以被校直與定位繞著晶粒10之暴露表面之中心，位於內連部17(例如，兩個錫球)之間。類似於晶粒10之安置步驟，嵌入式晶片20可以被成型於晶粒10之上或利用任何適當之方法被安置於晶粒10之上。在一實施例之中，嵌入式晶片20(無連接器元件26)可以附著於一轉移層或底材(未顯示)。轉移層可以被利用去安置嵌入式晶片20於晶粒10之上，例如，使用一覆晶製程。嵌入式晶片20之安置可以藉由翻轉轉移層及定位嵌入式晶片20於晶粒10之上而被執行。在嵌入式晶片20已被翻轉及被安置於晶粒10之上後，轉移層可以被移除掉，例如，使用一剝除或蝕刻製程去從嵌入式晶片20移除轉移層之材料。連接器元件26然後可以被安置於嵌入式晶片20之表面之上。第2c圖中之連接器元件26可以對應於第1圖中之導電墊23或可以是任何其他適當之內連接結構，例如：凸塊等。
第2d圖係繪示一模鑄步驟，其中，模鑄化合物25可以被成型去封裝晶粒10以及位於黏著層60上之嵌入式晶片20。模鑄化合物25可以包括有一聚合物或一模鑄底部填充物。模鑄化合物25可以藉由晶圓程度模鑄被成型去封裝晶粒10以及位於黏著層60上之嵌入式晶片20(從頂部及側邊)。
第2e圖係繪示一研磨步驟，其中，模鑄化合物25可以被部分研磨或移除掉，以暴露位於嵌入式晶片20之上表面處之連接器元件26以及晶粒10之內連部17(例如，錫球)之至少頂部部分。舉例來說，模鑄化合物25之厚度可以藉由一研磨製程被降低，以暴露連接器元件26以及內連部17。
第2f圖係繪示一重分佈層之成型步驟，其中，重分佈層30可以被成型於研磨後之模鑄化合物25之頂部、連接器元件26以及內連部17之上。重分佈層30之導電層32可以被成型(例如，沉積)以及圖刻(例如，使用微影製程)去與連接器元件26之暴露的上表面部分以及內連部17接觸，如第2f圖所示。重分佈層30之一聚合物層39可以被成型去沿著模鑄化合物25之暴露的上表面部分、導電層32、連接器元件26及內連部17延伸。第2f圖中之聚合物層39可以對應於第1圖中之第二聚合物層31及第三聚合物層33。
第2g圖係繪示一球固定步驟，其中，球型陣列40可以連結於重分佈層30。球型陣列40之導電元件42可以被安置去與重分佈層30之導電層32接觸。在一實施例之中，球型陣列40可以利用一油印製程而結合於重分佈層30。球型陣列40之導電元件42可以結合於重分佈層30中之凸塊底層金屬化元件(未 顯示)，其乃是被成型於導電層32之上。導電元件42可以是C4凸塊或微凸塊，並且可以包括有錫、銀、無鉛錫或銅等材料。在另一實施例之中，球型陣列40可以藉由另一晶片連結製程而結合於重分佈層30，其不會利用於位重分佈層30中之凸塊底層金屬化元件。重分佈層30之導電層32係提供電性結合於球型陣列40之導電元件42(在一側之上)、嵌入式晶片20之連接器元件26與晶粒10之內連部17之間。此可移除使用一層壓內連接層去連結晶片/晶粒於球型陣列以獲得一三維扇出結構之需求，並且因此可降低整體結構厚度、免除成型通孔之需求以及降低成本。
第2h圖係繪示移除載體50與黏著層60以及獲得個別晶片/晶粒封裝。每一個晶片/晶粒封裝可以對應於具有一三維扇出結構之一堆疊式封裝裝置100，其可以是一記憶晶片元件。為了獲得複數個分別與類似之三維扇出結構，載體50可以被分離於剩餘的層/元件。在一實施例之中，載體50可以藉由溶解或蝕刻用於結合載體50於封裝元件/層之黏著層60而被移除掉。當載體50被移除掉時，剩餘的連結層會包括有封裝晶粒10與嵌入式晶片20之模鑄化合物25、重分佈層30以及球型陣列40。
為了獲得複數個晶片/晶粒封裝，一晶片鋸、圖案蝕刻、雷射等步驟可以接著被施行去垂直沿著晶粒10之間的線分離剩餘連結層。所產生之個別晶片/晶粒封裝可以被翻轉去獲得類似之堆疊式封裝裝置100，其具有三維扇出結構。所產生之堆疊式封裝裝置100可以被分別地販售、運送、使用及/或 整合於裝置或其他封裝之中。堆疊式封裝裝置100可以被整合於裝置或其他封裝之中，其中，位於底部之球型陣列40是被使用去電性結合晶粒10之元件與嵌入式晶片於其他的裝置或封裝之中。舉例來說，一堆疊式封裝裝置100(如第2h圖所示)可以被安置於另一晶片封裝或一印刷電路板之頂部之上，並且可以是透過球型陣列40之導電元件42而電性結合於複數個元件。
雖然本發明已以較佳實施例揭露於上，然其並非用以限定本發明，任何熟習此項技藝者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10‧‧‧晶粒
11‧‧‧第二模鑄化合物
12‧‧‧晶片
14‧‧‧連結線
15‧‧‧導電墊
16‧‧‧通孔
17‧‧‧內連部
18‧‧‧底材
20‧‧‧嵌入式晶片
21‧‧‧連結層
22‧‧‧矽晶片
23‧‧‧導電墊
24‧‧‧鈍化保護層
25‧‧‧模鑄化合物
27‧‧‧第一聚合物層
30‧‧‧重分佈層
31‧‧‧第二聚合物層
32‧‧‧導電層
33‧‧‧第三聚合物層
40‧‧‧球型陣列
41‧‧‧凸塊底層金屬化元件
42‧‧‧導電元件
100‧‧‧堆疊式封裝裝置

Claims (10)

  1. 一種堆疊式封裝裝置，包括：一晶片封裝；一嵌入式晶片，結合於該晶片封裝；一重分佈層，結合於該晶片封裝以及該嵌入式晶片，其中，該嵌入式晶片係定位於該重分佈層與該晶片封裝之間；以及一球型陣列，結合於該重分佈層，其中，該重分佈層係定位於該球型陣列與該嵌入式晶片之間。
  2. 如申請專利範圍第1項所述之堆疊式封裝裝置，更包括一模鑄化合物，係封裝該晶片封裝與該嵌入式晶片，其中，該模鑄化合物係位於該重分佈層之上，並且係圍繞該嵌入式晶片。
  3. 如申請專利範圍第1項所述之堆疊式封裝裝置，其中，該晶片封裝包括：一底材；複數個晶片，堆疊於該底材之上；一模鑄化合物，封裝該等晶片，其中，該模鑄化合物係位於底材之上；複數個導電墊，位於該底材之兩側之上；複數個通孔，位於該底材之中，並且係結合於該等導電墊之間；複數個連結線，係被封入該模鑄化合物之中，並且係分別連結該等晶片於該等導電墊；以及複數個錫球，結合於位於該底材之一側上之該等導電墊，相 對於被結合之該等晶片及該重分佈層。
  4. 如申請專利範圍第1項所述之堆疊式封裝裝置，其中，該嵌入式晶片包括：一晶片；一連結層，連結該晶片及該晶片封裝，其中，該連結層係為一黏著層或一熱介面材料；複數個導電墊，結合於相對於該連結層之該晶片之一表面；一鈍化保護層，結合於該晶片之該表面以及該等導電墊；以及一聚合物層，結合於相對於該晶片之該鈍化保護層之一表面。
  5. 如申請專利範圍第4項所述之堆疊式封裝裝置，其中，該重分佈層包括：一第二聚合物層，結合於相對於該嵌入式晶片之該聚合物層之一表面；一導電層，結合於該嵌入式晶片之該等導電墊以及相對於該嵌入式晶片之該第二聚合物層之一表面；以及一第三聚合物層，結合於相對於該第二聚合物層之該導電層之一表面。
  6. 如申請專利範圍第1項所述之堆疊式封裝裝置，其中，該球型陣列包括複數個導電球，該等導電球係結合於相對於該嵌入式晶片之該重分佈層之一表面，該等導電球係透過複數個凸塊底層金屬化元件結合於該重分佈層，以及該等凸塊底層金屬化元件係定位於該重分佈層與該球型陣列之間。
  7. 一種堆疊式封裝裝置，包括：一晶粒；一晶片，結合於該晶粒；一重分佈層，結合於該晶片，其中，該晶片係嵌入於該晶粒與該重分佈層之間；以及一球型陣列，結合於該重分佈層，其中，該重分佈層係無需使用通孔而提供電性耦合於該球型陣列、該晶粒與該晶片之間。
  8. 一種成型一堆疊式封裝裝置之方法，包括：安置一黏著層於一載體底材之上；結合複數個晶片封裝於位於該載體底材上之該黏著層；安置一連結層於該等晶片封裝之上；結合複數個晶片於位於該晶片封裝上之該連結層；以一模鑄化合物封裝該等晶片封裝及位於該載體底材上之該等晶片；研磨該模鑄化合物以暴露該等晶片之複數個連接元件以及該等晶片封裝之複數個第二連接元件；成型一重分佈層於該模鑄化合物、該等連接元件及該等第二連接元件之上；成型一球型陣列於該重分佈層之上；剝離該載體底材；移除該黏著層；以及鋸開該等晶片封裝以及被封裝於該模鑄化合物之中及結合於該重分佈層與該球型陣列之該等晶片，以獲得具有一三維 扇出結構之複數個堆疊式封裝裝置。
  9. 如申請專利範圍第8項所述之成型一堆疊式封裝裝置之方法，其中，該等晶片係被嵌入至位於該等晶片封裝之該等第二連接元件之中，該等晶片係利用一轉移層及一覆晶製程被轉移至及結合於該連結層，以及該等晶片封裝係利用一轉移層及一覆晶製程被轉移至及結合於該黏著層。
  10. 如申請專利範圍第8項所述之成型一堆疊式封裝裝置之方法，其中，成型該重分佈層之步驟包括：成型一導電層於該模鑄化合物、該連接元件以及該第二連接元件之上；圖刻該導電層；成型一聚合物層於被圖刻之該導電層之上；圖刻該聚合物層；成型複數個凸塊底層金屬化元件於被圖刻之該導電層及被圖刻之聚合物層之上；以及安置該球型陣列之複數個導電球於該凸塊底層金屬化元件之上。
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