TW201351565A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

Info

Publication number
TW201351565A
TW201351565A TW101133092A TW101133092A TW201351565A TW 201351565 A TW201351565 A TW 201351565A TW 101133092 A TW101133092 A TW 101133092A TW 101133092 A TW101133092 A TW 101133092A TW 201351565 A TW201351565 A TW 201351565A
Authority
TW
Taiwan
Prior art keywords
semiconductor substrate
interlayer dielectric
air gap
dielectric layer
semiconductor
Prior art date
Application number
TW101133092A
Other languages
English (en)
Other versions
TWI560805B (en
Inventor
Hong-Seng Shue
Tai-I Yang
Wei-Ding Wu
Ming-Tai Chung
Shao-Chi Yu
Original Assignee
Taiwan Semiconductor Mfg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg filed Critical Taiwan Semiconductor Mfg
Publication of TW201351565A publication Critical patent/TW201351565A/zh
Application granted granted Critical
Publication of TWI560805B publication Critical patent/TWI560805B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76289—Lateral isolation by air gap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/764—Air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H01L2221/1042—Formation and after-treatment of dielectrics the dielectric comprising air gaps
    • H01L2221/1047—Formation and after-treatment of dielectrics the dielectric comprising air gaps the air gaps being formed by pores in the dielectric

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

一種半導體裝置，包括：一半導體基板；一接觸插栓，位於該半導體基板上；以及一層間介電層，位於該半導體基板上，而該接觸插栓係設置於該層間介電層內，其中該層間介電層之一部與該半導體基板密封形成一氣隙，且其中該氣隙為環繞該半導體基板之一部之一完整氣隙環狀物。

Description

半導體裝置及其製造方法
本發明係關於積體電路技術，且特別是關於一種半導體裝置及其製造方法。
於積體電路製程中，係於半導體晶片之表面上形成例如電晶體之多個元件。此些元件之間係為一隔離區所相分隔。一般使用淺溝槽隔離區(STI)做為上述隔離區之用，以分隔出半導體基板之多個主動區。通常，淺溝槽隔離區係於形成於半導體基板內之溝槽內填入一或多個介電材料所形成。
採用淺溝槽隔離物之積體電路仍遭遇了許多問題，其包括了於p型區域與n型區域間接面(junction)處的漏電流。對於高壓元件(high-voltage devices)而言，如此之傳統積體電路更遭遇了低崩潰電壓(low breakdown voltages)以及閉鎖(latch ups)等問題。
依據一實施例，本發明提供了一種半導體裝置，包括：一半導體基板；一接觸插栓，位於該半導體基板上；以及一層間介電層，位於該半導體基板上，而該接觸插栓係設置於該層間介電層內，其中該層間介電層之一部與該半導體基板密封形成一氣隙，且其中該氣隙為環繞該半導體基板之一部之一完整氣隙環狀物。
依據另一實施例，本發明提供了一種半導體裝置，包括： 一半導體基板；一深溝槽，自該半導體基板之一頂面延伸進入該半導體基板內；一金氧半導體元件，位於該半導體基板之該頂面上，其中該金氧半導體元件包括：一閘電極，位於該半導體基板上；以及一源極/汲極區，鄰近該閘電極與該深溝槽；以及一層間介電層，位於該閘電極與該源極/汲極區上，其中該層間介電層延伸進入該深溝槽內，且其中該層間介電層於該深溝槽內密封形成一氣隙。
依據又一實施例，本發明提供了一種半導體裝置之製造方法，包括：形成一金氧半導體元件於一半導體基板之一頂面上；於形成該金氧半導體元件後，形成一深溝槽於該半導體基板內；以及形成一層間介電層於該金氧半導體元件上，其中該層間介電層延伸進入該深溝槽內，其中該層間介電層於該深溝槽內密封形成一氣隙。
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉一較佳實施例，並配合所附的圖式，作詳細說明如下：
本發明提供了包括氣隙於其內之一種深溝槽隔離結構及其製造方法之多個實施例。於圖式中繪示了形成深溝槽隔離物之中間階段，以及討論了此些實施例之變化情形。於此些圖式以及圖示之實施例中，相同標號係代表相同構件。
請參照第1圖，提供一晶圓10。晶圓10包括半導體基板20，其可包括矽，且可為一結晶矽基板。或者，半導 體基板20亦可包括例如碳、鍺、鎵、砷、氮、銦、磷及/或相似物等之其他常用材料。半導體基板20亦可包括III-V族半導體材料，例如氮化鎵(GaN)、砷化鎵(GaAs)或相似物。於部分實施例中，半導體基板20為一塊狀半導體基板(bulk semiconductor substrate)。於其他實施例中，半導體基板20為一絕緣層上覆矽基板(SOI substrate)，其包括了設置於一上方半導體層20A與下方半導體層20B之間之一埋設層(buried layer)24。埋設層24可為氧化矽層，且於下文中可稱為埋設氧化物層24。埋設層24亦可為一非氧化物阻障層，其可藉由如佈植方式而於基板20之一中間層內採用輕度摻雜元素而形成埋設層24。
半導體基板20包括一元件區100、一元件區200與一元件區300。於部分實施例中，此些元件區100、200、300為包括擇自由實質上包括一高壓元件區、一低壓元件區、一邏輯核心區、一記憶區(例如靜態隨機存取記憶區)、一邏輯區、一輸入/輸出區、一p型金氧半導體(PMOS)元件區、一n型金氧半導體(NMOS)元件區以及相似物所組成族群之一之不同區域。於部分實施例中，元件區300為一低壓元件區，而元件區100與元件區200分別為一高壓PMOS元件區以及一高壓NMOS元件區。
請繼續參照第1圖，於部分實施例中，於元件區300內形成數個淺溝槽隔離區22，而此些淺溝槽隔離區22係自半導體基板20之頂面延伸進入半導體基板20內。然而，於形成淺溝槽隔離區22之同時，於元件區100與元件區200之內則並不包括有用於隔離主動區之淺溝槽隔離區。 於其他實施例中，於元件區300內也沒有形成此些淺溝槽隔離區22。取而代之的是，將於元件區300內形成用於元件隔離之數個深溝槽148(請參照第3圖)與數個氣隙(air gap，請參照第5圖內之氣隙154)。於此些元件區100、200與300內分別形成有如一n型井區26、一p型井區28以及可為p型井區或n型井區之一井區30等範例井區。於半導體基板20為一絕緣層上覆矽基板之一實施例中，此些井區26、28與30可延伸至埋設氧化物層24之頂面。於其他實施例中，此些淺溝槽隔離區22可具有高於埋設氧化物層24之頂面之底部。於部分實施例中，n型井區26、p型井區28以及井區30具有介於約1014/立方公分-約1017/立方公分之摻質濃度。值得注意的是，上述描述中之數值僅做為範例之用，其可為其他之不同數值。
請參照第2圖，於此些元件區100、200與300內分別形成一金氧半導體(MOS)元件130、230與330。於部分實施例中，金氧半導體元件130可包括位於半導體基板20上之一閘介電層134、位於閘介電層134上之一閘電極136以及位於閘電極136數個側壁上之數個閘間隔物138。於閘電極136之相對側之上形成有源極區與汲極區(於下文中稱為源極/汲極區)140。再者，亦可形成源極與汲極延伸區142。金氧半導體元件230可包括一閘介電層234、一閘電極236、數個閘間隔物238、數個源極/汲極區240、數個源極/汲極延伸區242以及相似物。於金氧半導體元件130與230為高壓金氧半導體元件之一實施例中，分別於金氧半導體元件130與230之汲極側上可更形成有隔離區(未顯 示，例如為場氧化物(FOX)或淺溝槽隔離物(STI)區)。此些隔離區可延伸至閘電極136與236下方並分隔了汲極140/240與各閘電極136/236。金氧半導體元件130與230可於如高於約5伏特、高於50伏特或高於100伏特下之汲極電壓下操作，而不會造成金氧半導體元件130與230之崩潰(breakdown)。於部分實施例中，金氧半導體元件130與230分別為一NMOS元件與一PMOS元件。
金氧半導體元件330可包括一閘介電層334、一閘電極336、數個閘間隔物338、數個源極/汲極區340、數個源極/汲極延伸區342以及相似物。於部分實施例中，金氧半導體元件330具有不同於金氧半導體元件130與230結構之一結構。舉例來說，金氧半導體元件330可為一低壓金氧半導體元件，其於各汲極電壓之操作電壓範圍可低於如約5伏特下操作，而不會造成金氧半導體元件330的崩潰。然而，當施加於金氧半導體元件330之汲極的汲極電壓高於其操作電壓時，可能會造成金氧半導體元件330的崩潰。
於部分實施例中，此些閘介電層134、234、334包括二氧化矽。或者，此些閘介電層134、234、334包括高介電常數(high-k)介電材料、氮氧化矽、氮化矽或其組合。上述高介電常數介電材料可擇自於金屬氧化物(metal oxides)、金屬氮化物(metal nitrides)、金屬矽酸鹽(metal silicates)、過渡金屬氧化物(transition metal-oxides)、過渡金屬氮化物(transition metal-nitride)、過渡金屬矽酸鹽(transition metal-silicates)、金屬之氮氧化物(oxynitrides of metals)、金屬鋁酸鹽(metal alumniates)、矽酸鋯(zirconium silicate)、鋁酸鋯(zirconium aluminate)、氧化鉿(hafnium oxide)或其組合。此些閘介電層134、234、334可由化學氣相沉積(CVD)、原子層沉積(ALD)、熱氧化法、其他適當方法或其組合所形成。
此些閘電極136、236與336可包括多結晶矽(即多晶矽)。或者，此些閘電極136、236與336可包括一金屬或一金屬矽化物，例如鋁、銅、鉬、鎳、鎢、鈦、鉭、氮化鈦、氮化鉭、矽化鎳(NiSi)、鎳鉑矽化物(NiPtSi)、矽化鈷(CoSi)及其組合。此些閘電極136、236與336之形成方法包括化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)或相似方法。此些閘介電層134、234、334與閘電極136、236與336的形成可包括形成一坦覆介電層與一坦覆閘電極層，並接著施行一圖案化步驟。
此些源極/汲極區140、240及/或340可藉由多道佈植所形成，或可藉由凹陷半導體基板20以於其內形成數個凹陷區，並接著磊晶成長此些源極/汲極區140、240及/或340於各凹陷區之內所形成。此些源極/汲極區140、240及/或340可分別具有介於約1019/立方公分至約1021/立方公分之一n型或p型摻質濃度，其分別依照金氧半導體元件130、230、330之導電類型而定。
此些源極/汲極矽化物區144、244及344係分別形成於此些源極/汲極區140、240及或340上。於當閘電極136、236、336包括矽之實施例中，亦可形成數個閘矽化物區146、246與346。此些矽化物區144、244、344、146、246、346的形成可包括一自對準矽化製程(salicide process)。此 自對準矽化製程包括形成源極/汲極區140、240與340之後坦覆地沉積一金屬層(未顯示)，並接著施行一回火以造成金屬層與下方矽層的反應。因此便可形成此些矽化物區144、244、344、146、246、346。上述金屬層可包括鎳、鈷或相似物。未反應之金屬部分則接著被移除。
第3圖顯示了數個深溝槽148的形成，其藉由蝕刻半導體基板20而形成。於當半導體基板20為一塊狀基板時之一實施例中，此些深溝槽148可具有大體等於、或大於p型井區26與n型井區28之深度之一深度D1。此深度D1可為淺溝槽隔離區22之深度D2的2-10倍，或為淺溝槽隔離區22之深度D2的2-5倍，其可視金氧半導體元件130與230之個別操作電壓而定。於當半導體基板20為一絕緣層上覆矽基板時之一實施例中，此些深溝槽148可延伸至埋設氧化物24處，因此埋設氧化物24將為深溝槽148所露出。此些深溝槽148之一(標號為148A)可形成於p型井區26與n型井區28之介面區處。如此，於形成此些深溝槽148之後，p型井區26與n型井區28的側壁可皆為深溝槽148A所露出。因此，深溝槽148A可做為p型井區26與n型井區28間之一隔離結構。
此些深溝槽148可鄰近於源極/汲極區140與240以及源極/汲極矽化物區144與244。於部分實施例中，源極/汲極區140與240以及源極/汲極矽化物區144與244係為此些深溝槽148所露出的。如此，源極/汲極區140與240以及源極/汲極矽化物區144與244的側壁可為深溝槽148所露出。於其他實施例中，此些深溝槽148可藉由如各p 型井區26與n型井區28之部分而與源極/汲極區140與240以及源極/汲極矽化物區144與244相分隔。
此些深溝槽148可藉由反應性離子蝕刻(RIE)、深反應性離子蝕刻(DRIE)或相似方法所形成。此些深溝槽148的形成包括了複數個蝕刻/沉積循環，其即為傳統之深反應性離子蝕刻。於部分實施例中，形成此些深溝槽148之蝕刻包括使用一電漿源，其為一電感耦合電漿源(ICP source)。或者，用於蝕刻之電漿亦可藉由一變壓器耦合電漿(TCP)所形成。此些深溝槽148之側壁148B與位於同一深溝槽148內之各底面148C形成了一角度α。而此角度α為小於90度之一銳角，例如介於70-90度。此角度α亦可包括等於或稍微大於90度之一角度。此角度α可例如介於約90-95度。
第4圖顯示了一介電層或數個介電層的形成。依據本發明之部分實施例，此些介電層包括層間介電層(ILD layer)150與152，其覆蓋了金氧半導體元件130、230與330的頂部與側壁。於下文中，雖然所形成之數個介電層係採用了層間介電層150與152做為描述，但是此些介電能內亦可包括數個金屬層間介電層(IMD layer)，而此些金屬層間介電層其係用於形成金屬導線於其內。於部分實施例中，於形成接觸開口時，層間介電層150亦可做為一接觸蝕刻停止層之用，以停止上方層間介電層152的蝕刻。於圖示實施例中，此些層間介電層150與152於結合後可稱為一複合層間介電層。層間介電層150與152亦可採用不同材料。舉例來說，層間介電層150可由如氧化矽、氮化 矽或其組合之介電材料所形成。層間介電層152可由氧化物所形成，例如為磷矽玻璃(PSG)、硼矽玻璃(BSG)、硼摻雜之磷矽玻璃(BPSG)、四乙氧基矽烷氧化物(TEOS oxide)或相似物。層間介電層152之頂面可高於閘金屬矽化區146、246、與346之頂面。於部分實施例中，層間介電層150與152係使用一化學氣相沉積(CVD)所形成，例如為一電漿加強型化學氣相沉積(PECVD)、次大氣壓化學氣相沉積法(SACVD)或相似方法。
於此些深溝槽148內形成層間介電層150與152之後，於深溝槽148內將形成了氣隙(air gap)154。此些氣隙154之體積可介於各深溝槽148之體積的0.3-0.9倍，其中氣隙154之體積影響了各金氧半導體元件130與230之絕緣特性。於部分實施例中，層間介電層150與152包括了形成於深溝槽148數個側壁上之部分。層間介電層150與152之此些部分可能覆蓋或可能不覆蓋深溝槽148之側壁。如此，於部分實施例中，半導體基板20之側壁之部分將為氣隙154所露出的。於其他實施例中，層間介電層150完全密封了氣隙154，且因此層間介電層150並不具有大體部分延伸進入深溝槽148之部分。於另一實施例中，層間介電層150與152皆包括形成於此些深溝槽154內之側壁與底部上之部分，而於深溝槽154之中心部分形成了氣隙154。氣隙154可為真空的或為氣體所填入，其可包括於層間介電層沉積時環境中的部分之化學元素。層間介電層152可自深溝槽148之外側連續地或不連續地延伸進入溝槽148內。於部分實施例中，氣隙154之高度H1係大 於深溝槽148之深度D1的50%、80%或90%。垂直或倒梯形(reversed trapezoid)之深溝槽148的形成有助於提早地密封深溝槽148，並可增加氣隙154的體積。
於部分實施例中，氣隙154的剖面形狀可相似於水滴(或亦稱為眼淚形)。氣隙154之頂端可高於半導體基板之頂面且相差約20-50奈米。依照層間介電層150與152之厚度以及用於形成層間介電層150與152之沉積方法，此相差情形亦可大於約150奈米。或者，氣隙154之頂端亦可低於半導體基板之頂面且相差約20-150奈米。依照層間介電層150與152之厚度以及用於形成層間介電層150與152沉積方法，此相差情形亦可約為250奈米。
第5圖顯示了於層間介電層150與152內數個接觸插栓56的形成。於部分實施例中，接觸插栓56包括鎢、鋁、銅、鈦、或其合金。形成製程包括煮了蝕刻層間介電層150與152以形成數個接觸開口，以及接著於此些接觸開口內填入導電材料。接著施行一化學機械研磨(CMP)以移除高於層間介電層152之導電材料之過量部分。導電材料之剩餘部分形成了此些接觸插栓56。
第6圖為一上視圖，顯示了如第5圖內所示裝置之數個部分，其中在此顯示金氧半導體元件130與230。值得注意的是，此些深溝槽148與此些氣隙156可形成環繞半導體元件130與230之完整環狀物(full ring)。再者，深溝槽148A(以及其內之氣隙154)可位於金氧半導體元件130與230之間並分隔了p型井區26與n型井區28。如此，此氣隙154可避免了於p型井區26與n型井區之間形成一 接面(junction)，因此具有降低漏電流之效果。再者，當金氧半導體元件130與230為高壓元件時，由於氣隙154具有一高崩潰電壓，而因此施加於於氣隙154內任何電路構件之高電壓可與氣隙154外部之電路構件隔離。
第7A圖與第7B圖分別顯示了一半導體裝置之一上視圖與一剖面圖，其中一深溝槽148係為另一深溝槽148所環繞。請參照第7A圖，每一金氧半導體元件130與230係為此些深溝槽148之一所環繞。再者，另一深溝槽148形成並環繞此些金氧半導體元件130與230並環繞此些對應深溝槽148。如第7B圖所示，於部分實施例中，於金氧半導體元件130與230之間之存在有兩個深溝槽148或一單一深溝槽148。
請再次參照第5圖，依據本發明之部分實施例，於同一晶圓10上，淺溝槽隔離區22與氣隙154係做為隔離區之用。淺溝槽隔離區22可做為低壓元件之隔離區，而氣隙154可用於隔離高壓元件。於其他實施例中，於晶圓10內並未形成有淺溝槽隔離區。取而代之的是，於淺溝槽隔離區22之區域處形成有氣隙154。
雖然第5圖顯示了氣隙154做為鄰近或環繞金氧半導體元件之隔離結構。值得注意的是，氣隙154可做為包括電容、電阻或相似物之其他元件之隔離區，但並不以上述元件為限。
氣隙154具有高於淺溝槽隔離區之崩潰電壓。實驗結果顯示了氣隙之崩潰電壓可較位於金屬層內之於金屬導線的崩潰電壓約高出了470伏特，如此顯示了氣隙之崩潰電 壓夠高，故其不會成為積體電路之可靠度改善中的瓶頸。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此項技藝者，在不脫離本發明之精神和範圍內，當可作更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10‧‧‧晶圓
20‧‧‧半導體基板
20A‧‧‧上方半導體層
20B‧‧‧下方半導體層
22‧‧‧淺溝槽隔離區
24‧‧‧埋設層/埋設氧化物層
26‧‧‧n型井區
28‧‧‧p型井區
30‧‧‧井區
56‧‧‧接觸插栓
100、200、300‧‧‧元件區
130、230、330‧‧‧金氧半導體元件
134、234、334‧‧‧閘介電層
136、236、336‧‧‧閘電極
138、238、338‧‧‧閘間隔物
140、240、340‧‧‧源極/汲極區
142、242、342‧‧‧源極與汲極延伸區
144、244、344‧‧‧源極/汲極矽化物區
146、246、346‧‧‧閘矽化物區
148、148A‧‧‧深溝槽
148B‧‧‧側壁
148C‧‧‧底面
150、152‧‧‧層間介電層
154‧‧‧氣隙
W1‧‧‧寬度
D1、D2‧‧‧深度
H1‧‧‧高度
第1-5圖為一系列剖面圖，顯示了依據本發明之一實施例之一種金氧半導體元件以及隔離區之製造方法，其中隔離區具有氣隙；第6圖為一上視圖，顯示了第5圖所示結構之一部；以及第7A圖與第7B圖分別顯示了一元件之一上視圖與一剖面圖，其中一深溝槽形成並環繞另一深溝槽。
10‧‧‧晶圓
20‧‧‧半導體基板
22‧‧‧淺溝槽隔離區
24‧‧‧埋設層
26‧‧‧n型井區
28‧‧‧p型井區
30‧‧‧井區
100、200、300‧‧‧元件區
130、230、330‧‧‧金氧半導體元件
134、234、334‧‧‧閘介電層
136、236、336‧‧‧閘電極
138、238、338‧‧‧閘間隔物
140、240、340‧‧‧源極/汲極區
144、244、344‧‧‧源極/汲極矽化物區
146、246、346‧‧‧閘矽化物區
150、152‧‧‧層間介電層
154‧‧‧氣隙
D1‧‧‧深度
H1‧‧‧高度

Claims (10)

  1. 一種半導體裝置，包括：一半導體基板；一接觸插栓，位於該半導體基板上；以及一層間介電層，位於該半導體基板上，而該接觸插栓係設置於該層間介電層內，其中該層間介電層之一部與該半導體基板密封形成一氣隙，且其中該氣隙為環繞該半導體基板之一部之一完整氣隙環狀物。
  2. 如申請專利範圍第1項所述之半導體裝置，更包括：一金氧半導體元件，位於該半導體基板之一頂面上，其中該金氧半導體元件包括：一閘電極，位於該半導體基板上；以及一源極/汲極區，鄰近該閘電極，其中該層間介電層包括延伸於該閘電極與該源極/汲極區上之一第一部，以及延伸進入該半導體基板內之一第二部，且其中該氣隙與該源極/汲極區係位於該層間介電層之該第二部之對稱側。
  3. 如申請專利範圍第2項所述之半導體裝置，其中該層間介電層之該第一部與該第二部係連續地連接位於該半導體基板內之該層間介電層以及位於該氣隙之下方之一部，以形成連續之一層間介電層區域。
  4. 如申請專利範圍第1項所述之半導體裝置，更包括另一氣隙，位於該半導體基板內且形成了環繞該半導體基板之一部之另一完整氣隙環狀物，其中該完整氣隙環狀物之一部連接該另一完整氣隙環狀物之一側。
  5. 一種半導體裝置，包括： 一半導體基板；一深溝槽，自該半導體基板之一頂面延伸進入該半導體基板內；一金氣半導體元件，位於該半導體基板之該頂面上，其中該金氧半導體元件包括：一閘電極，位於該半導體基板上；一源極/汲極區，鄰近該閘電極與該深溝槽；以及一層間介電層，位於該閘電極與該源極/汲極區上，其中該層間介電層延伸進入該深溝槽內，且其中該層間介電層於該深溝槽內密封形成一氣隙。
  6. 如申請專利範圍第5項所述之半導體裝置，其中該深溝槽之一側壁與該深溝槽之一底部形成了小於90度之一銳角。
  7. 如申請專利範圍第5項所述之半導體裝置，其中該金氧半導體元件之一上視圖中，該氣隙形成了環繞該金氧半導體元件之一完整環狀物。
  8. 一種半導體裝置之製造方法，包括：形成一金氧半導體元件於一半導體基板之一頂面上；於形成該金氧半導體元件後，形成一深溝槽於該半導體基板內；以及形成一層間介電層於該金氧半導體元件上，其中該層間介電層延伸進入該深溝槽內，其中該層間介電層於該深溝槽內密封形成一氣隙。
  9. 如申請專利範圍第8項所述之半導體裝置之製造方法，於形成該金氧半導體元件之前，更包括形成一淺溝槽 隔離區，延伸進入該半導體基板內。
  10. 如申請專利範圍第8項所述之半導體裝置之製造方法，其中形成該深溝槽係施行採用擇自包括深反應性離子蝕刻與反應性離子蝕刻所組成族群之一方法。
TW101133092A 2012-06-01 2012-09-11 Semiconductor device and method for fabricating the same TWI560805B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/486,265 US9269609B2 (en) 2012-06-01 2012-06-01 Semiconductor isolation structure with air gaps in deep trenches

Publications (2)

Publication Number Publication Date
TW201351565A true TW201351565A (zh) 2013-12-16
TWI560805B TWI560805B (en) 2016-12-01

Family

ID=49669192

Family Applications (1)

Application Number Title Priority Date Filing Date
TW101133092A TWI560805B (en) 2012-06-01 2012-09-11 Semiconductor device and method for fabricating the same

Country Status (4)

Country Link
US (2) US9269609B2 (zh)
KR (1) KR101410147B1 (zh)
CN (1) CN103456768B (zh)
TW (1) TWI560805B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10224396B1 (en) 2017-11-20 2019-03-05 Globalfoundries Inc. Deep trench isolation structures

Families Citing this family (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015037166A1 (ja) * 2013-09-11 2015-03-19 パナソニックＩｐマネジメント株式会社 半導体装置
US9653477B2 (en) * 2014-01-03 2017-05-16 International Business Machines Corporation Single-chip field effect transistor (FET) switch with silicon germanium (SiGe) power amplifier and methods of forming
US9406559B2 (en) 2014-07-03 2016-08-02 Taiwan Semiconductor Manufacturing Co., Ltd Semiconductor structure and method for forming the same
KR102317651B1 (ko) * 2015-04-14 2021-10-27 삼성전자주식회사 반도체 소자 및 이의 제조 방법
US9711390B2 (en) * 2015-05-21 2017-07-18 Sandisk Technologies Llc Shallow trench isolation trenches and methods for NAND memory
US9607943B2 (en) 2015-06-11 2017-03-28 International Business Machines Corporation Capacitors
TWI721026B (zh) * 2015-10-30 2021-03-11 日商半導體能源研究所股份有限公司 電容器、半導體裝置、模組以及電子裝置的製造方法
US10164029B2 (en) * 2015-12-18 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and manufacturing method thereof
US9972633B2 (en) * 2016-01-27 2018-05-15 United Microelectronics Corp. Semiconductor device and method for fabricating the same
US11211305B2 (en) * 2016-04-01 2021-12-28 Texas Instruments Incorporated Apparatus and method to support thermal management of semiconductor-based components
US10861796B2 (en) 2016-05-10 2020-12-08 Texas Instruments Incorporated Floating die package
TWI624003B (zh) * 2016-08-17 2018-05-11 世界先進積體電路股份有限公司 半導體結構與其形成方法
US10243047B2 (en) * 2016-12-08 2019-03-26 Globalfoundries Inc. Active and passive components with deep trench isolation structures
US10043824B2 (en) * 2016-12-15 2018-08-07 Vanguard International Semiconductor Corporation Semiconductor device including a vacuum gap and method for manufacturing the same
US10074639B2 (en) 2016-12-30 2018-09-11 Texas Instruments Incorporated Isolator integrated circuits with package structure cavity and fabrication methods
US10256298B2 (en) * 2017-02-02 2019-04-09 Vanguard International Semiconductor Corporation Semiconductor structure and method for forming the same
US20180226292A1 (en) * 2017-02-06 2018-08-09 Globalfoundries Inc. Trench isolation formation from the substrate back side using layer transfer
US10056289B1 (en) 2017-04-20 2018-08-21 International Business Machines Corporation Fabrication of vertical transport fin field effect transistors with a self-aligned separator and an isolation region with an air gap
US9922973B1 (en) * 2017-06-01 2018-03-20 Globalfoundries Inc. Switches with deep trench depletion and isolation structures
US10461152B2 (en) 2017-07-10 2019-10-29 Globalfoundries Inc. Radio frequency switches with air gap structures
US10833153B2 (en) * 2017-09-13 2020-11-10 Globalfoundries Inc. Switch with local silicon on insulator (SOI) and deep trench isolation
US10483153B2 (en) * 2017-11-14 2019-11-19 Taiwan Semiconductor Manufacturing Co., Ltd. Deep trench isolation structure in semiconductor device
US10910313B2 (en) * 2017-11-16 2021-02-02 Samsung Electronics Co., Ltd. Integrated circuit including field effect transistors having a contact on active gate compatible with a small cell area having a small contacted poly pitch
US10546937B2 (en) 2017-11-21 2020-01-28 Taiwan Semiconductor Manufacturing Co., Ltd. Structures and methods for noise isolation in semiconductor devices
CN115332153A (zh) * 2017-12-29 2022-11-11 联华电子股份有限公司 半导体元件及其制作方法
US10720494B2 (en) * 2018-01-22 2020-07-21 Globalfoundries Inc. Field-effect transistors with airgaps
US10446643B2 (en) 2018-01-22 2019-10-15 Globalfoundries Inc. Sealed cavity structures with a planar surface
US11056382B2 (en) * 2018-03-19 2021-07-06 Globalfoundries U.S. Inc. Cavity formation within and under semiconductor devices
US11404536B2 (en) * 2018-03-30 2022-08-02 Intel Corporation Thin-film transistor structures with gas spacer
US10522390B1 (en) 2018-06-21 2019-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. Shallow trench isolation for integrated circuits
US10672795B2 (en) * 2018-06-27 2020-06-02 Taiwan Semiconductor Manufacturing Co., Ltd. Bulk semiconductor substrate configured to exhibit semiconductor-on-insulator behavior
US10438843B1 (en) * 2018-08-31 2019-10-08 United Microelectronics Corp. Semiconductor device and method for fabricating the same
US10825721B2 (en) * 2018-10-23 2020-11-03 Taiwan Semiconductor Manufacturing Co., Ltd. Insulating cap on contact structure and method for forming the same
US11410872B2 (en) 2018-11-30 2022-08-09 Globalfoundries U.S. Inc. Oxidized cavity structures within and under semiconductor devices
US10923577B2 (en) 2019-01-07 2021-02-16 Globalfoundries U.S. Inc. Cavity structures under shallow trench isolation regions
TWI685085B (zh) * 2019-02-26 2020-02-11 華邦電子股份有限公司 記憶元件及其製造方法
US10971632B2 (en) * 2019-06-24 2021-04-06 Semiconductor Components Industries, Llc High voltage diode on SOI substrate with trench-modified current path
US11450601B2 (en) * 2019-09-18 2022-09-20 Micron Technology, Inc. Assemblies comprising memory cells and select gates
FR3101480B1 (fr) * 2019-09-30 2021-10-29 St Microelectronics Tours Sas Tranchées isolantes pour les circuits ESD
US11127816B2 (en) 2020-02-14 2021-09-21 Globalfoundries U.S. Inc. Heterojunction bipolar transistors with one or more sealed airgap
US11164793B2 (en) * 2020-03-23 2021-11-02 International Business Machines Corporation Reduced source/drain coupling for CFET
CN113644048B (zh) * 2020-04-27 2023-12-22 联华电子股份有限公司 半导体元件及其制造方法
US11183452B1 (en) * 2020-08-12 2021-11-23 Infineon Technologies Austria Ag Transfering informations across a high voltage gap using capacitive coupling with DTI integrated in silicon technology
US11114488B1 (en) * 2020-09-25 2021-09-07 Shenzhen Adaps Photonics Technology Co. LTD. Image sensing devices with reflector arrays
US11764258B2 (en) * 2020-12-01 2023-09-19 Globalfoundries U.S. Inc. Airgap isolation structures
US11798836B2 (en) * 2021-06-17 2023-10-24 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor isolation structure and method of making the same
US11881506B2 (en) 2021-07-27 2024-01-23 Globalfoundries U.S. Inc. Gate structures with air gap isolation features
TWI814545B (zh) * 2022-08-22 2023-09-01 華邦電子股份有限公司 半導體元件及其製造方法

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6104054A (en) * 1998-05-13 2000-08-15 Texas Instruments Incorporated Space-efficient layout method to reduce the effect of substrate capacitance in dielectrically isolated process technologies
US6406975B1 (en) 2000-11-27 2002-06-18 Chartered Semiconductor Manufacturing Inc. Method for fabricating an air gap shallow trench isolation (STI) structure
FR2826179A1 (fr) 2001-06-14 2002-12-20 St Microelectronics Sa Tranchee d'isolement profonde et procede de realisation
JP2003158180A (ja) 2001-11-26 2003-05-30 Mitsubishi Electric Corp トレンチ分離を有する半導体装置およびその製造方法
ITMI20021099A1 (it) * 2002-05-22 2003-11-24 St Microelectronics Srl Struttura d'isolamento a dielettrico per l'integrazione di dispositivi elettronico a semiconduttore e relativo processo di realizzazione
US7141086B2 (en) 2002-06-03 2006-11-28 Ricoh Company, Ltd. Abrasive grain and method for producing it, polishing tool and method for producing it, grinding wheel and method for producing it, and polishing apparatus
US6791155B1 (en) * 2002-09-20 2004-09-14 Integrated Device Technology, Inc. Stress-relieved shallow trench isolation (STI) structure and method for forming the same
KR100532727B1 (ko) 2003-07-23 2005-11-30 동부아남반도체 주식회사 셀로우 트렌치 소자 분리막 제조 방법
KR100559990B1 (ko) 2003-12-30 2006-03-13 동부아남반도체 주식회사 반도체 장치의 소자 분리체 및 그 형성방법
EP1589572B1 (fr) * 2004-04-21 2020-03-11 Nxp B.V. Procédé de fabrication d'un circuit intégré comprenant l'élaboration de tranchées d'isolation creuses
US7396732B2 (en) 2004-12-17 2008-07-08 Interuniversitair Microelektronica Centrum Vzw (Imec) Formation of deep trench airgaps and related applications
US7723803B2 (en) * 2005-03-07 2010-05-25 Taiwan Semiconductor Manufacturing Co., Ltd. Bipolar device compatible with CMOS process technology
DE102007020268B3 (de) * 2007-04-30 2008-11-06 Advanced Micro Devices, Inc., Sunnyvale Halbleiterbauelement und Verfahren zum Verhindern der Ausbildung von elektrischen Kurzschlüssen aufgrund von Hohlräumen in der Kontaktzwischenschicht
JP4594973B2 (ja) * 2007-09-26 2010-12-08 株式会社東芝 不揮発性半導体記憶装置
KR100903470B1 (ko) 2007-11-27 2009-06-18 주식회사 동부하이텍 반도체 소자 및 그의 제조 방법
JP4560100B2 (ja) * 2008-03-24 2010-10-13 株式会社東芝 半導体装置
US7842577B2 (en) * 2008-05-27 2010-11-30 Taiwan Semiconductor Manufacturing Company, Ltd. Two-step STI formation process
JP4956500B2 (ja) * 2008-07-22 2012-06-20 株式会社東芝 半導体記憶装置及びその製造方法
KR20100025107A (ko) 2008-08-27 2010-03-09 크로스텍 캐피탈, 엘엘씨 에어갭을 구비한 샐로우 트렌치 소자분리구조, 이를 이용한시모스 이미지 센서 및 그 제조방법
KR20100102982A (ko) 2009-03-12 2010-09-27 삼성전자주식회사 반도체 장치
JP5729745B2 (ja) * 2009-09-15 2015-06-03 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP5669251B2 (ja) 2010-01-20 2015-02-12 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
KR20110117326A (ko) * 2010-04-21 2011-10-27 매그나칩 반도체 유한회사 반도체 장치 및 그 제조방법
KR101559345B1 (ko) * 2010-08-26 2015-10-15 삼성전자주식회사 비휘발성 메모리 소자 및 그 제조 방법
US8609508B2 (en) * 2010-12-08 2013-12-17 Stmicroelectronics, Inc. Method of fabricating an integrated circuit having a strain inducing hollow trench isolation region
KR20130015167A (ko) * 2011-08-02 2013-02-13 삼성전자주식회사 에어 갭을 갖는 반도체 소자 및 그 제조 방법

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10224396B1 (en) 2017-11-20 2019-03-05 Globalfoundries Inc. Deep trench isolation structures
TWI663688B (zh) * 2017-11-20 2019-06-21 美商格芯（美國）集成電路科技有限公司 深溝槽隔離結構

Also Published As

Publication number Publication date
TWI560805B (en) 2016-12-01
US20160172250A1 (en) 2016-06-16
US10049941B2 (en) 2018-08-14
KR20130135709A (ko) 2013-12-11
KR101410147B1 (ko) 2014-06-19
US20130320459A1 (en) 2013-12-05
US9269609B2 (en) 2016-02-23
CN103456768B (zh) 2016-05-04
CN103456768A (zh) 2013-12-18

Similar Documents

Publication Publication Date Title
TW201351565A (zh) 半導體裝置及其製造方法
TWI701830B (zh) 半導體裝置及其形成方法
US10818549B2 (en) Semiconductor devices including contact plugs
KR102472133B1 (ko) 집적회로 소자
TWI613811B (zh) 半導體結構及形成半導體的方法
CN104377200B (zh) 半导体器件及其制造方法
CN107170825B (zh) 半导体器件、鳍式场效晶体管器件及其形成方法
CN105280591A (zh) 具有保护层的自对准互连件
CN104576370B (zh) 形成晶体管的方法
US9159802B2 (en) MOS devices with mask layers and methods for forming the same
TWI697985B (zh) 半導體裝置及其製造方法
CN103000572A (zh) 高k金属栅极器件的接触件
JP2011044659A (ja) 半導体装置及びその製造方法
US20170162574A1 (en) Semiconductor devices and methods of manufacturing the same
CN104241135A (zh) 在硅化物形成之前在触点蚀刻之后添加的电介质衬里
US10832983B2 (en) Semiconductor device having a trench type device isolation film and method for fabricating the same
CN106549061A (zh) 半导体器件及其制造方法
TW201909282A (zh) 半導體裝置及其製程
CN105762134A (zh) 集成电路设备和形成集成电路设备的方法
US9466694B2 (en) Metal-oxide-semiconductor transistor device and manufacturing method thereof
CN103390648B (zh) 半导体结构及其形成方法
KR100853799B1 (ko) 트렌치 게이트 반도체 소자 및 그의 제조 방법
CN104143530B (zh) 晶体管及其制作方法
KR102249695B1 (ko) 커패시터를 구비한 반도체 디바이스 및 그 제조 방법
KR102396533B1 (ko) 반도체 장치 및 그 제조 방법