TW201349417A - 半導體積體電路裝置 - Google Patents

半導體積體電路裝置 Download PDF

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TW201349417A
TW201349417A TW102108673A TW102108673A TW201349417A TW 201349417 A TW201349417 A TW 201349417A TW 102108673 A TW102108673 A TW 102108673A TW 102108673 A TW102108673 A TW 102108673A TW 201349417 A TW201349417 A TW 201349417A
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integrated circuit
semiconductor integrated
terminal
semiconductor substrate
type
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TW102108673A
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TWI576975B (zh
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Hirofumi Harada
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Seiko Instr Inc
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    • H01L23/492—Bases or plates or solder therefor
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Abstract

本發明的課題是在於提供一種可彈性地決定針腳配置構成的半導體積體電路裝置。其解決手段是以絕緣膏來將晶片焊墊(die pad)接著於半導體積體電路，晶片焊墊是從半導體積體電路表面的Al焊墊以接合線來電位固定。此時，若半導體基板為P型，則晶片焊墊成為半導體積體電路動作上的最低電位的端子以外的端子。

Description

半導體積體電路裝置
本發明是有關半導體積體電路的安裝形態。
使用在製作半導體積體電路的半導體基板是按照用途而有各式各樣者，大多是含以磷為首的N型雜質的N型半導體基板或含硼等的P型雜質的P型半導體基板。
製作含CMOS電路的半導體積體電路時，在使用N型半導體基板時是設為圖4(1)那樣的構成。亦即在N型半導體基板2設置P型阱區域6，在此P型區域內集聚N通道型MOS電晶體(以下稱為NMOS)102，在除此以外的N型半導體基板上集聚P通道型MOS電晶體(以下稱為PMOS)101，以金屬配線來將該等結線而構成電路。此時為了確實地分離．絕緣此P型阱區域及N型半導體基板，而將P型阱區域設為半導體積體電路內的最低電位(以下稱為VSS電位)，將N型半導體基板成為半導體積體電路內的最高電位(以下稱為VDD電位)的方式電位固定，防止在N型半導體基板及P型阱區域中流動 順方向電流。
具體而言，在N型半導體基板上設置用以使電位導通的N型高濃度擴散區域13，以PMOS的源極端子4為首，在電路內與成為VDD電位的全部端子連接。同樣，在P型阱區域設置P型高濃度擴散區域12，以NMOS的源極端子5為首，在電路內與成為VSS電位的全部端子連接。
另一方面，在P型半導體基板上集聚半導體元件時，如圖4(2)般，設置用以使與P型半導體基板1電位導通的P型高濃度擴散區域12，以NMOS的源極端子5為首，在電路內與成為VSS電位的全部端子連接。同樣，在N型阱區域7設置N型高濃度擴散區域13，以PMOS的源極端子4為首，在電路內與成為VDD電位的全部端子連接。
上述那樣構成時，使用N型半導體基板的半導體積體電路是除了半導體基板表面的元件形成區域以外的半導體基板內部．底面．側面的N型區域全體會成為VDD電位，使用P型半導體基板的半導體積體電路是除了半導體基板表面的元件形成區域以外的半導體基板內部．底面．側面的P型區域全體會成為VSS電位。因此經由切割工程等來進行晶片小片化時，在半導體基板表面以外的部分，成為VDD電位或VSS電位那樣的半導體基板會露出。
此N型半導體基板/P型半導體基板是基於各種的理由被分開使用，例如搭載的電晶體等的元件的性能或電路 的要求，甚至搭載半導體積體電路裝置的模組基板，模組電路的構成上的情況等。
其一例，可假想在電路動作的制約上，控制半導體積體電路內的特定的MOS電晶體的反餽偏壓的情況。例如電路控制NMOS的反餽偏壓的情況，在圖4(1)中解開特定的NMOS102的P型阱區域6內的P型高濃度擴散區域12與NMOS的源極端子5的結線，將通至P型高濃度擴散區域的配線連接至反餽偏壓控制用的電路之下可實現。如此N型半導體基板的情況，可獨立分割形成搭載NMOS的P型阱區域，使特定的P型阱區域的電位變化，可控制NMOS的反餽偏壓。
可是，如圖4(2)般，使用P型半導體基板時，因為搭載NMOS的P型區域全部連結成為同一電位，所以不可能控制特定的NMOS的反餽偏壓。若有如此的電路的要求，則選擇N型半導體基板。
圖2是表示經由切割工程等來將使用如此的N型半導體基板的半導體積體電路小片化，封裝的情況。在圖2(1)是以接著用膏8來將小片化後的半導體積體電路晶片接著於被成形的金屬製的導線架內的晶片焊墊9，經由之後形成的接合線10來使形成於半導體積體電路上的金屬的焊墊與晶片焊墊電性連接。如圖2(2)所例示般，半導體積體電路晶片通常是具有複數的電性連接用焊墊，導線架側也分別準備對應該焊墊的導線(端子)，分別以接合線連接。
此時通常接著用膏為了取得半導體積體電路晶片下的晶片焊墊與形成露出的半導體基板的電性連接而使用銀膏。就此例而言，由於半導體積體電路晶片是使用N型半導體基板，因此經由銀膏來與N型半導體基板接著的晶片焊墊是照原樣作為VDD端子，如圖2(2)般經由接合線來與形成於半導體積體電路晶片表面的VDD焊墊103連接之構成。
將半導體積體電路晶片接著於晶片焊墊，以接合線來使導通的方法，例如揭示於專利文獻1。
〔先行技術文獻〕 〔專利文獻〕
〔專利文獻1〕日本特開平5-160333號公報
然而，改變半導體基板的極性時，以往的安裝方法有以下那樣的課題。
在增加半導體積體電路裝置的布陣多樣化(lineup variety)時，有不變更被安裝既存半導體積體電路裝置的模組，僅半導體積體電路裝置換成新的性能者的限制的情況，產生必須使既存模組的端子與連接至半導體積體電路裝置的晶片焊墊的端子的屬性一致(針腳相容化(pin compatible))。該情況，阻礙針腳相容化的最主要原因是半導體基板的極性不同。
例如在使用N型半導體基板的例子之圖2(2)所使用的晶片焊墊是無法搭載使用P型半導體基板來製作之持同樣機能的半導體積體電路晶片。原因是因為如圖3所示般P型半導體基板的電位是設定成VSS電位，所以經由銀膏來連接的晶片焊墊也就那樣成為VSS端子，圖2(2)的VDD端子在圖3(2)的例子是不得不改變成VSS端子。因此為了使用同一晶片焊墊，需要進行預定N型半導體基板的電路設計，但基於電路的要求，有時不可能，明顯阻礙設計彈性。
最確實的方法是可舉不對半導體積體電路裝置施加設計變更，按搭載的各模組基板來設計．製造配合既存模組的針腳配置構成之新的晶片焊墊，但這會有需要新晶片焊墊製作用的成本及設立確認期間或量產效果面也會有成本增加的缺點。
因此，最好是可與既存模組基板的針腳屬性無關來設計半導體積體電路晶片，且可容易在安裝工程實現針腳相容化的方法。
為了解決上述課題，本發明使用以下的手段。
首先，為一種半導體積體電路裝置，其特徵係由：具有P型的半導體基板之半導體積體電路、及搭載前述半導體積體電路之金屬的晶片焊墊、及接著前述半導體積體電路與前述晶片焊墊之具有1×1012Ω．cm以上的體積電阻率 之絕緣性膏所構成，前述晶片焊墊係成為半導體積體電路動作上的最低電位的端子以外的端子。
並且，成為前述半導體積體電路動作上的最低電位的端子以外的端子係成為半導體積體電路動作上的最高電位的端子。
而且，為一種半導體積體電路裝置，其特徵係由：具有N型的半導體基板之半導體積體電路、及搭載前述半導體積體電路之金屬的晶片焊墊、及接著前述半導體積體電路與前述晶片焊墊之具有1×1012Ω．cm以上的體積電阻率之絕緣性膏所構成，前述晶片焊墊係成為半導體積體電路動作上的最高電位的端子以外的端子。
並且，成為前述半導體積體電路動作上的最高電位的端子以外的端子係成為半導體積體電路動作上的最低電位的端子。
若根據本發明，則可提供一種不管半導體基板的P，N極性，可採用同一晶片焊墊之半導體積體電路裝置的安裝方法。
1‧‧‧P型半導體基板
2‧‧‧N型半導體基板
4‧‧‧PMOS源極端子
5‧‧‧NMOS源極端子
6‧‧‧P型阱區域
7‧‧‧N型阱區域
8‧‧‧接著用膏
9‧‧‧晶片焊墊
10‧‧‧接合線
11‧‧‧模製樹脂
12‧‧‧P型高濃度擴散區域
13‧‧‧N型高濃度擴散區域
101‧‧‧P通道型MOS電晶體
102‧‧‧N通道型MOS電晶體
103‧‧‧VDD端子
104‧‧‧VSS端子
圖1(1)是包含本發明的第1實施例的半導體積體電路裝置的模式剖面圖，(2)是包含本發明的第1實施例的半導體積體電路裝置的平面圖。
圖2(1)是包含以往的半導體積體電路裝置的模式剖面圖，(2)是以往的半導體積體電路裝置的平面圖。
圖3(1)是包含以往別的半導體積體電路裝置的模式剖面圖，(2)是以往別的半導體積體電路裝置的平面圖。
圖4(1)是包含P半導體基板上所構成的CMOS電路的模式剖面圖，(2)是包含N半導體基板上所構成的CMOS電路的模式剖面圖。
以下根據圖面來說明本發明的實施形態。圖1(1)、(2)是採用本發明的安裝方法的半導體積體電路裝置的剖面圖及平面圖。
在圖1中，經由接著用膏8來將使用P型半導體基板1的半導體積體電路晶片接著於晶片焊墊9。在此，接著用膏是使用具有1×1012Ω．cm以上的電阻率的絕緣膏。因此P半導體基板及其下的晶片焊墊是被電性絕緣，即使各個的電位不同，也不會有電流流動的情形。
並且，在接著此P型半導體基板的晶片焊墊9是取經由接合線10來與半導體積體電路的最大電位之VDD端子103導通的構成。此VDD端子雖未圖示，但實際是與金屬配線經由N型高濃度擴散區域來連接至N型阱區域7(圖4(2))。另一方面，VSS端子104是取經由接合線來導通至別的端子之構成，與成為電路上的最低電位的 P型阱區域6或成為最低電位的其他元件端子連接。
此半導體積體電路晶片及接合線是被模製樹脂11包圍，自外界的環境加以保護。另一方面，複數的導線的一端是如圖1(2)般，從模製樹脂露出至外面，可取其他的電路基板連接。
此端子構成是形成與使用圖2的N型半導體基板的半導體積體電路裝置同樣的端子構成，可知針腳相容化被確保。其理由是如上述般，因為不管使用P型半導體基板，以絕緣性膏來接著於晶片焊墊，所以可不拘上面的半導體積體電路晶片的基板，可自由地設定此晶片焊墊的電位，可將以往的例子中應成為VSS端子者設為VDD端子。
在圖1、圖2的例子是敘述有關VDD端子、VSS端子的使用的自由度，但由本發明可獨立設定載置半導體積體電路晶片的晶片焊墊的電位之事可知，當然可對應於VDD端子、VSS端子以外的端子，例如輸出電壓端子、ON/OFF開關端子等所有的端子，可實現廣泛的針腳相容。
並且，到此為止是根據圖1，以搭載於P型半導體基板的半導體積體電路為例進行說明，但當然此技術也可同樣適用於N型半導體基板。亦即，在經由絕緣膏來將搭載半導體積體電路的N型半導體基板接著於晶片焊墊時，可將此N型半導體基板下晶片焊墊的電位以往必定成為VDD者設定於任意的端子。因此，對於使用既存的P型半導體基板的半導體積體電路裝置，可在使用N型半導體 基板的半導體積體電路裝置容易達成針腳相容化。
而且，使用N型半導體基板的半導體積體電路裝置的優點是可舉藉由使接著N型半導體基板的晶片焊墊的電位形成低電位，不必考慮金屬遷移現象。
可是，在本發明成為必須的絕緣性膏是一般熱傳導率比金屬膏低，因此在半導體積體電路晶片使用大量的電流時，有難放掉該大電流所引起的發熱之特徵。這會牽連使安裝封裝的容許損失降低，所以不適於高溫環境下、大電流動作。因此，本發明對於持有收在熱傳導率不在意程度的發熱之100μA以下的消費電流之半導體積體電路而言為理想的技術。
1‧‧‧P型半導體基板
6‧‧‧P型阱區域
7‧‧‧N型阱區域
8‧‧‧接著用膏
9‧‧‧晶片焊墊
10‧‧‧接合線
11‧‧‧模製樹脂
103‧‧‧VDD端子
104‧‧‧VSS端子

Claims (5)

  1. 一種半導體積體電路裝置，其特徵係由：具有P型的半導體基板之半導體積體電路、及搭載前述半導體積體電路之金屬的晶片焊墊、及接著前述半導體積體電路與前述晶片焊墊之具有1×1012Ω．cm以上的體積電阻率之絕緣性膏所構成，前述晶片焊墊係成為半導體積體電路動作上的最低電位的端子以外的端子。
  2. 如申請專利範圍第1項之半導體積體電路裝置，其中，成為前述半導體積體電路動作上的最低電位的端子以外的端子係成為半導體積體電路動作上的最高電位的端子。
  3. 一種半導體積體電路裝置，其特徵係由：具有N型的半導體基板之半導體積體電路、及搭載前述半導體積體電路之金屬的晶片焊墊、及接著前述半導體積體電路與前述晶片焊墊之具有1×1012Ω．cm以上的體積電阻率之絕緣性膏所構成，前述晶片焊墊係成為半導體積體電路動作上的最高電位的端子以外的端子。
  4. 如申請專利範圍第3項之半導體積體電路裝置，其中，成為前述半導體積體電路動作上的最高電位的端子以外的端子係成為半導體積體電路動作上的最低電位的端子。
  5. 如申請專利範圍第1~4項中的任一項所記載之半導 體積體電路裝置，其中，前述半導體積體電路的消費電流為100μA以下。
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