TW201349364A - 超薄埋入式晶粒模組及其製造方法 - Google Patents

超薄埋入式晶粒模組及其製造方法 Download PDF

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TW201349364A
TW201349364A TW102109110A TW102109110A TW201349364A TW 201349364 A TW201349364 A TW 201349364A TW 102109110 A TW102109110 A TW 102109110A TW 102109110 A TW102109110 A TW 102109110A TW 201349364 A TW201349364 A TW 201349364A
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layer
uncut
laminate
flex
die
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TW102109110A
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TWI593030B (zh
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Paul Alan Mcconnelee
Elizabeth Ann Burke
Scott Smith
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Gen Electric
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Abstract

本發明係關於一種形成一埋入式晶粒模組之方法，其包括提供一初始層壓撓曲層及形成通過該初始層壓撓曲層之一晶粒開口。藉由一黏著材料將一第一未切層壓撓曲層緊固至該初始層壓撓曲層之第一表面且在該初始層壓撓曲層之該晶粒開口內定位一晶粒且將該晶粒定位至該黏著材料上。藉由一黏著材料將一第二未切層壓撓曲層緊固至該初始層壓撓曲層之第二表面，且固化該第一未切層壓撓曲層與該初始層壓撓曲層之間及該第二未切層壓撓曲層與該初始層壓撓曲層之間之該黏著材料。在該等第一及第二未切層壓撓曲層中及該等第一及第二未切層壓撓曲層上形成複數個通孔金屬互連，其中該等金屬互連中之各者延伸通過一各自通孔且直接金屬化至該初始層壓撓曲層上之一金屬互連或該晶粒上之一晶粒墊。

Description

超薄埋入式晶粒模組及其製造方法
本發明之實施例大體上係關於積體電路封裝，且更特定而言，係關於使用直接至晶片接合墊或電組件連接墊之低電阻金屬互連從而容許較高裝置速度、較低功率消耗及較小尺寸之一埋入式晶粒堆積。可將埋入式晶粒模組製造為在其中具有一或多個晶粒或電子組件。該複數個晶粒或電子組件藉由通過複數個層壓撓曲層路由之金屬互連電連接至一輸入/輸出系統。
隨著積體電路變得越來越小且產生更好之操作性能，用於積體電路(IC)封裝之封裝技術各自地自引線封裝演進至基於層壓之球柵格陣列(BGA)封裝、演進至晶片級封裝(CSP)、接著演進至覆晶封裝且現在演進至埋入式晶粒/嵌入式晶片堆積封裝。日益增長之實現較好性能、較大小型化及較高可靠性之需要驅使IC晶片封裝技術之進步。出於大規模製造藉此容許規模經濟之目的，新封裝技術必須進一步提供批量式生產之可能性。
IC晶片封裝要求之進步對現有埋入式晶粒堆積程序提出挑戰。即，在許多當前埋入式晶粒模組中需要具有一增加數目之重分佈層，其中八個或八個以上重分佈層係常見的。標準埋入式晶粒堆積程序(其中初始地將一或多個晶粒放置在IC基板上且隨後以一逐層方式施加重分佈層)，可導致重新佈線及互連系統中之翹曲，從而需要使用 一模製環氧樹脂應力平衡層或金屬加強板。
對現有埋入式晶粒堆積程序之另一挑戰為製造/堆積週期之時間。對堆積時間之一主要貢獻者為經執行以用於固化包括在埋入式晶粒模組中之複數個黏著層之多個固化步驟，諸如多重烘烤步驟。
因此，需要用於埋入式晶粒製造之一方法，該方法提供一較短製造週期時間且容許施加多個層壓層同時在不適用一加強板之情況下最小化模組之翹曲。
本發明之實施例藉由提供一埋入式晶粒模組堆積程序來克服上述缺陷，在該程序中以提供一完全平衡模組之構造之一雙面方式在一晶粒周圍施加複數個層壓撓曲層。執行一單個固化步驟以固化模組中之多個黏著層，藉此減少堆積時間。
根據本發明之一個態樣，形成一埋入式晶粒模組之一方法包括提供一初始層壓撓曲層及在該初始層壓撓曲層中及在該初始層壓撓曲層上形成複數個通孔及複數個金屬互連，該複數個金屬互連延伸通過各自通孔以在該初始層壓撓曲層之相對第一及第二表面中之各者上形成互連，形成通過該初始層壓撓曲層之一晶粒開口。該方法亦包括藉由一黏著材料將一第一未切層壓撓曲層緊固至初始層壓撓曲層之第一表面，在初始層壓撓曲層之晶粒開口內定位一晶粒且將該晶粒定位至該黏著材料上，藉由一黏著材料將一第二未切層壓撓曲層緊固至該初始層壓撓曲層之第二表面，固化第一未切層壓撓曲層與初始層壓撓曲層之間及第二未切層壓撓曲層與初始層壓撓曲層之間之黏著材料，及在第一及第二未切層壓撓曲層中及在第一及第二未切層壓撓曲層上形成複數個通孔及複數個金屬互連，該複數個金屬互連中之各者延伸通過一各自通孔且直接金屬化至初始層壓撓曲層上之一金屬互連及晶粒上之一晶粒墊中之一者。
根據本發明之另一態樣，形成一嵌入式晶片封裝之一方法包括在一中心層壓層中形成複數個通孔，形成延伸通過該複數個通孔之複數個金屬互連以在該中心層壓層之相對第一及第二表面中之各者上形成互連，形成通過該中心層壓層之一晶片開口，藉由一黏著材料將一第一未切層壓層施加至中心層壓層之第一表面，及在中心層壓層之晶片開口內定位一晶片且將該晶片定位至該黏著材料上，該晶片具有等於該中心層壓層之一厚度之一厚度。該方法亦包括藉由一黏著材料將一第二未切層壓層施加至中心層壓層之第二表面，固化第一未切層壓層與中心層壓層之間及第二未切層壓層與中心層壓層之間之黏著材料，及圖案化第一及第二未切層壓層以形成複數個通孔及複數個金屬互連，使得該複數個金屬互連中之各者延伸通過一各自通孔且直接金屬化至中心層壓層上之一金屬互連及晶片上之一晶片墊中之一者。
根據本發明之另一態樣，藉由包括以下步驟之一程序來製造一嵌入式晶片封裝：預圖案化一中心層壓層以形成複數個通孔及延伸通過該複數個通孔之複數個金屬互連，其中該複數個金屬互連在該中心層壓層之相對第一及第二表面之各者上形成互連。該程序亦包括形成通過中心層壓層之一晶粒開口，藉由一黏著材料將一第一未切層壓層施加至中心層壓層之第一表面，在中心層壓層之晶粒開口內定位一晶粒且將該晶粒定位至黏著材料上，該晶粒具有等於該中心層壓層之一厚度之一厚度，藉由一黏著材料將第二未切層壓層施加至中心層壓層之第二表面，在同一時間一起固化第一未切層壓撓曲層與基層壓撓曲層之間及第二未切層壓撓曲層與基層壓撓曲層之間之黏著材料，及執行一雙面圖案化於第一及第二未切層壓撓曲層以形成複數個通孔及複數個金屬互連，其中自一第一方向形成第一未切層壓撓曲層之該複數個通孔及該複數個金屬互連，且自與該第一方向相反之一第二方向形成第二未切層壓撓曲層之該複數個通孔及該複數個金屬互連。
將根據結合附圖提供之本發明之較佳實施例之以下詳細描述來更容易地理解此等及其他優勢及特徵。
10‧‧‧埋入式晶粒模組
12‧‧‧晶片
14‧‧‧層壓撓曲層/層壓層
16‧‧‧框架
18‧‧‧未切初始或「中心」層壓撓曲層
20‧‧‧額外通孔/通孔
22‧‧‧金屬互連
24‧‧‧初始層壓撓曲層之第一表面
26‧‧‧初始層壓撓曲層之第二表面
28‧‧‧晶粒開口/開口
30‧‧‧晶粒
32‧‧‧未切層壓撓曲層
34‧‧‧黏著劑/黏著材料/層
36‧‧‧圍溝區域
38‧‧‧未切層壓撓曲層
40‧‧‧晶粒上之墊/晶粒墊
42‧‧‧外表面
44‧‧‧第一方向
46‧‧‧第二方向
48‧‧‧額外未切層壓撓曲層/額外層壓撓曲層
50‧‧‧額外未切層壓撓曲層/額外層壓撓曲層
51‧‧‧黏著材料
52‧‧‧焊接遮罩層/焊接遮罩
54‧‧‧球柵格陣列(BGA)封裝
56‧‧‧埋入式晶粒模組
58‧‧‧球柵格陣列
60‧‧‧埋入式晶粒模組
62‧‧‧第一晶粒
64‧‧‧第二晶粒
66‧‧‧初始層壓撓曲層/層壓撓曲層
68‧‧‧晶粒開口
70‧‧‧晶粒開口
72‧‧‧未切層壓撓曲層
74‧‧‧未切層壓撓曲層
76‧‧‧第一及第二晶粒中之各者上之墊
圖式繪示當前預期用於實施本發明之實施例。
在圖式中：圖1為根據本發明之一實施例之複數個埋入式晶粒模組之一俯視圖。
圖2至圖10為根據本發明之一實施例之在一製造/堆積程序之各個階段期間之一埋入式晶粒模組之示意性橫截面側視圖。
圖11為根據本發明之一實施例之耦合至一球柵格陣列(BGA)封裝之一埋入式晶粒模組之一示意性橫截面側視圖。
圖12為根據本發明之一實施例之埋入式晶粒模組之堆疊配置之一示意性橫截面側視圖。
圖13為根據本發明之一實施例之一埋入式晶粒模組之一示意性橫截面側視圖。
本發明提供形成一埋入式晶粒模組(即，嵌入式晶片封裝)之一方法。使用層壓撓曲層及晶片或電組件相對於層壓層之放置來製造該埋入式晶粒模組。藉由由形成在經圖案化層壓層中之金屬互連提供之一直接金屬連接來將埋入式晶粒模組中之(若干)晶粒/電組件連接至一輸入/輸出(I/O)系統。
本發明之實施例涉及包括嵌入在複數個經圖案化之層壓撓曲層(即，重分佈層)內之一或多個晶粒(即，晶片)之一埋入式晶粒模組之堆積。雖然下文在圖1至圖12之實施例中將嵌入在埋入式晶粒模組中之晶片特定稱為一晶粒或晶片，但應理解，其他電組件可在埋入式晶粒模組中替代該晶粒，且因此本發明之實施例不僅僅限於在一埋入式 晶粒模組中嵌入晶片/晶粒。即，亦應將在下文描述之埋入式晶粒模組實施例中使用晶粒/晶片理解為涵蓋可在埋入式晶粒模組中提供之其他電組件，諸如電阻器、電容器、電感器或其他類似裝置。
參考圖1，根據本發明之一例示性實施例展示複數個製成之埋入式晶粒模組10或嵌入式晶片封裝。每一埋入式晶粒模組10包括與複數個層壓撓曲層14(即，重分佈層)連接且嵌入在該複數層壓撓曲層14(即，重分佈層)中之個一或多個晶片12(即，晶粒)。每一晶片12由一半導電材料(諸如，矽或GaAs)形成且經處理使得在其表面上形成一積體電路(IC)佈局。該複數個層壓層14中之各者呈可相對於(若干)晶片12放置之一預形成層壓薄片或薄膜之形式。層壓層14可由Kapton®、Ultem®、聚四氟乙烯(PTFE)或另一聚合物薄膜(諸如一液晶聚合物(LCP)，或一聚醯亞胺材料)形成。如圖1中所展示，藉由在鄰近埋入式晶粒模組10之間之一區域中對層壓層14進行切塊來形成每一埋入式晶粒模組10，其中在一框架16上執行埋入式晶粒模組堆積程序。
參考圖2至圖10，根據本發明之一實施例，闡述用於製造複數個埋入式晶粒模組10中之各者之一技術。為易於將堆積程序形象化，在圖2至圖10中之各者中展示一單個埋入式晶粒模組堆積程序之一橫截面。
根據本發明之一實施例，該埋入式晶粒模組堆積程序以提供及圖案化一未切初始或「中心」層壓撓曲層18開始。根據一個實施例，初始層壓撓曲層18呈一Kapton®層壓撓曲之形式，儘管如上文引用，亦可使用其他合適材料，諸如Ultem®、聚四氟乙烯(PTFE)或另一聚合物薄膜(諸如，一液晶聚合物(LCP)或一聚醯亞胺材料)。初始層壓撓曲層18具有約50微米之一厚度以便容納一超薄晶粒在形成在初始層壓撓曲層18中之一開口中之定位，如下文將詳細解釋。
在圖案化圖2中之初始層壓撓曲層18時，通過層壓層形成複數個通孔20。根據一例示性實施例，藉由一雷射燒蝕或雷射鑽孔程序來形成通孔20。或者，亦應理解，可藉由其他方法來形成通孔20，包括：電漿蝕刻、光形成或機械鑽孔程序。在形成通孔20之後，接著藉由(舉例而言)一濺鍍、電鍍及/或無電子塗覆程序將一金屬層/材料(諸如，一種子金屬及/或銅)施加至層壓撓曲層18上，且接著將該金屬層/材料(諸如，一種子金屬及/或銅)形成至金屬互連22中。根據本發明之一個實施例，該金屬層/材料經圖案化及蝕刻使得形成延伸通過通孔20且在初始層壓撓曲層18之一第一表面24及初始層壓撓曲層18之一第二表面26中之各者上形成互連22之金屬互連22。根據另一實施例，應理解，可作為具有已形成在其上/其中之複數個通孔20及複數個金屬互連22之一「預圖案化」層來提供初始層壓撓曲層18。
在埋入式晶粒模組堆積程序之一下一個步驟中，且如圖3中所展示，在一初始層壓撓曲層18中形成一晶粒開口28。晶粒開口28具有實質上與待放置在晶粒開口28中之一晶粒(即，圖6中之晶粒30)之一尺寸及形狀匹配之一尺寸及形狀，其中開口28係略微過大的以容納該晶粒在開口28中之接納。如圖3中所展示，初始層壓撓曲層18之所得形狀為一「窗框」構造之形狀。根據本發明之實施例，可藉由一雷射切割及一衝模衝孔操作中之一者來形成開口28。
現參考圖4至圖5，埋入式晶粒模組堆積程序以提供一未切層壓撓曲層32繼續，該未切層壓撓曲層32在待接合至初始層壓撓曲層18之一側上具有塗敷或塗覆至其之一黏著材料/層34。未切層壓撓曲層32為一空白或未圖案化層壓撓曲。將未切層壓撓曲層32定位在初始層壓撓曲層18之第一表面24上(即，將未切層壓撓曲層32層壓至初始層壓撓曲層18之第一表面24上)且藉由黏著劑34將該未切層壓撓曲層32緊固至該第一表面24，如圖5中所展示，其中未切層壓撓曲層32覆蓋形 成在初始層壓撓曲層18中之晶粒開口28之一側。根據一個實施例，藉由一真空層壓將未切層壓撓曲層32施加至初始層壓撓曲層18，其中在防止黏著材料34之固化之一溫度下執行該真空層壓。
在將未切層壓撓曲層32放置至初始層壓撓曲層18上之後，在形成在初始層壓撓曲層18中之晶粒開口28內定位一晶粒30，如圖6中所展示。藉由塗覆至未切層壓撓曲層32之黏著材料34在開口28內緊固晶粒30。根據本發明之一例示性實施例，且如圖6中所展示，晶粒30呈具有與初始層壓撓曲層18之一厚度相等或匹配之一厚度之一「超薄晶粒」之形式。因此，舉例而言，初始層壓撓曲層18及晶粒30中之各者可經構造以具有約50微米之一匹配厚度。
如圖6中所展示，在將晶粒30放置於開口28中之後，一開放/空隙圍溝區域36仍維持存在於晶粒30與初始層壓撓曲層18之間。經執行以將未切層壓撓曲層32緊固至初始層壓撓曲層18之真空層壓步驟亦用於消除(至少部分地)在圍溝區域36中存在之空隙。即，在執行真空層壓時，黏著材料34被拉入至圍溝區域36中以至少部分地消除/填充該圍溝區域。
埋入式晶粒模組堆積程序繼而提供另一未切層壓撓曲層38施加至初始層壓撓曲層18之第二表面26上且施加至仍然曝露之晶粒30之表面，如圖7中所展示。未切層壓撓曲層38係空白的或稱為未經圖案化層壓撓曲的層，且將其定位在初始層壓撓曲層18上(即，將其壓至初始層壓撓曲層18)且藉由一黏著材料/層34將其緊固至初始層壓撓曲層18。在將未切層壓撓曲層38放置至初始層壓撓曲層18上時，執行一真空層壓(即，真空烘烤)步驟以將未切層壓撓曲層38緊固至初始層壓撓曲層18。該真空層壓亦用於藉由將黏著材料34拖入至圍溝區域36中以至少部分地消除圍溝區域36中之空隙且填充該圍溝區域，來(至少部分地)消除/填充圍溝區域36中在晶粒30與初始層壓撓曲層18之間存在 之空隙。如先前指示，在防止黏著材料34之固化之一溫度下執行此真空層壓。
在將晶粒30放置在初始層壓撓曲層18中之開口28內且將未切層壓撓曲層38、38層壓至初始層壓撓曲層18及晶粒30之後，執行黏著層34之一固化。根據一個實施例，藉由一壓力烘烤操作(pressure baking operation)來完成該固化，儘管應理解，可使用其他合適固化程序。有利的是，根據本發明之實施例，僅執行一單一烘烤/固化步驟來固化兩個黏著層34，因此減少與埋入式晶粒模組之堆積相關聯之處理時間及成本。
現參考圖8，在堆積技術之下一個步驟中，未切層壓撓曲層32、38經圖案化以形成複數個通孔20，其中該等通孔係經鑽孔通過層壓撓曲層32、38。在對應於在初始重分佈層18上形成之金屬互連22之位置處形成通孔20，以使金屬互連22曝露。將額外通孔20向下鑽孔至晶粒30上之墊40，以使此等墊曝露。根據一例示性實施例，藉由一雷射燒蝕或雷射鑽孔程序來形成通孔20。或者，亦應理解，可藉由其他方法來形成通孔20：包括電漿蝕刻、光界定或機械鑽孔程序。接著，藉由(舉例而言)一濺鍍或電鍍程序來將一金屬層/材料(諸如，一種子金屬及/或銅)施加至未切層壓撓曲層32、38上，且接著將該金屬層/材料(諸如，一種子金屬及/或銅)形成至金屬互連22中。該金屬層/材料經圖案化及蝕刻使得自層壓撓曲層32、38之面向外表面42延伸且通過通孔20向下延伸之金屬互連22形成。層壓撓曲層32、38上之金屬互連22因此形成與初始層壓撓曲層18上之互連22之一電連接及至晶粒墊40之一直接金屬及電連接。
如圖8中所展示，對於施加至初始層壓撓曲層18之第一表面24之未切層壓撓曲層32而言，自一第一方向44形成(即，鑽孔、雷射燒蝕)通孔20。即，自上而下形成未切層壓撓曲層32中之通孔20。相反地， 對於施加至初始層壓撓曲層18之第二表面26之未切層壓撓曲層38而言，自與第一方向44相反之一第二方向46鑽孔通孔20。即，由下而上鑽孔未切層壓撓曲層38中之通孔20。
現在參考圖9，在製造技術之一下一個步驟中，將額外未切層壓撓曲層48、50層壓至未切層壓撓曲層32、38上且隨後將該等額外未切層壓撓曲層48、50圖案化。額外層壓撓曲層48、50呈藉由一黏著材料51施加至埋入式晶粒模組之相對表面之未切層壓撓曲層之形式，以便形成具有相等數目之自初始層壓撓曲層18向外延伸之層壓撓曲層之一平衡埋入式晶粒模組。即，初始層壓撓曲層18形成一「中央」層壓撓曲層，且將額外層壓撓曲層48、50施加在初始層壓撓曲層18之相對側上(即，施加在初始層壓撓曲層18之第一及第二表面24、26上)。此一雙面層壓程序用於減少給予初始層壓撓曲層18之應力且防止初始層壓撓曲層18之翹曲。
如圖9中所展示，在額外層壓撓曲層48、50中之各者中形成複數個通孔20。金屬互連22亦經形成/圖案化以通過通孔20且通過額外層壓撓曲層48、50向下延伸，以將額外層壓撓曲層48、50中之各者電連接至鄰近未切層壓撓曲層32、38。與層壓撓曲層32、38之圖案化類似，根據一雙面圖案化程序來執行額外層壓撓曲層48、50之圖案化。即，自一第一方向44(即，自上而下)鑽孔/雷射燒蝕形成在層壓撓曲層48中之通孔20，同時自第二方向46(即，自下而上)鑽孔/雷射燒蝕層壓撓曲層50中之通孔20。
根據本發明之實施例，應理解，可在埋入式晶粒模組之一進一步堆積期間施加除層48、50之外之額外層壓撓曲層，其中所施加之額外層壓撓曲層之數目取決於埋入式晶粒模組之設計考慮。
現在參考圖10，在施加所有額外層壓撓曲層48、50之後，將一焊接遮罩層52施加至埋入式晶粒模組之相對表面上之最外層壓撓曲層 48、50。焊接遮罩52提供一單獨封裝/模組至埋入式晶粒模組之連接。舉例而言，根據一個實施例，且如圖11中所展示，將一球柵格陣列(BGA)封裝54組裝至一埋入式晶粒模組10上或在一埋入式晶粒模組10上堆疊一球柵格陣列(BGA)封裝54。根據另一實例，且如圖12中所展示，將一分離埋入式晶粒模組56堆疊至埋入式晶粒模組10上。根據一個實施例，藉由一球柵格陣列58將經堆疊之埋入式晶粒模組10、56耦合在一起，儘管應理解，舉例而言，亦可使用一平台柵格陣列或導電環氧樹脂來將該等模組耦合在一起。雖然圖12展示兩個埋入式晶粒模組10、56以一垂直配置之一堆疊，但應理解，可將一較大數目之埋入式晶粒模組堆疊在彼此之上。
現在參考圖13，根據本發明之另一實施例，展示包括在一共用水平平面中配置/施加之一第一晶粒62及一第二晶粒64之一埋入式晶粒模組60。根據圖13之實施例，第一及第二晶粒62、64中之各者具有與初始層壓撓曲層66之一厚度匹配之一厚度。將第一及第二晶粒62、64中之各者放置在形成在初始層壓撓曲層66中之分離晶粒開口68、70中，以在同一水平平面中配置。在鄰近未切層壓撓曲層72、74中圖案化複數個通孔20及通過通孔20向下延伸之金屬互連22，使得金屬互連延伸至第一及第二晶粒62、64中之各者上之墊76。即，金屬互連22向下延伸至墊76以形成至第一及第二晶粒62、64之晶粒墊76之一直接金屬及電連接。第一及第二晶粒62、64在同一平面(即，層壓撓曲層66)上之並排嵌入容許埋入式晶粒模組60中之層壓撓曲層之數目之一減少，從而幫助減小埋入式晶粒模組60之總厚度且降低相關聯生產成本。
有益的是，本發明之實施例因此提供具有一較短製造週期時間一埋入式晶粒模組堆積程序，該堆積程序容許施加多個層壓層同時在不使用一加強板之情況下最小化模組之翹曲。該堆積程序將多個黏著 層之固化(經由多個固化步驟)組合至一單個固化步驟中，以減少與固化步驟相關聯之處理時間及成本，且使用真空層壓步驟來完全移除晶粒周圍之所有空隙，其中該晶粒周圍之圍溝區域被完全填充。此外，該堆積程序基於雙面層壓及包括在該雙面層壓中之通孔形成程序且基於在埋入式晶粒之兩個側上使用一相同黏著劑來提供完全平衡之一模組。由該堆積程序產生之完成埋入式晶粒模組係非常薄的且與額外埋入式晶粒模組相容，以提供堆疊晶粒模組之形成。基於本發明之埋入式晶粒模組堆積技術，可因此將埋入式晶粒模組構造為與其他現有埋入式晶粒模組堆積技術相比具有一減小厚度、受控之平坦度、提高之設計密度、增加之解析度及提高之電性能。
因此，根據本發明之一個實施例，形成一埋入式晶粒模組之一方法包括提供一初始層壓撓曲層及在該初始層壓撓曲層中及在該初始層壓撓曲層上形成複數個通孔及複數個金屬互連，該複數個金屬互連延伸通過各自通孔以在初始層壓撓曲層之相對第一及第二表面中之各者上形成互連，形成通過初始層壓撓曲層之一晶粒開口。該方法亦包括藉由一黏著材料將一第一未切層壓翹曲層緊固至初始層壓撓曲層之第一表面，在初始層壓撓曲層之晶粒開口內定位一晶粒且將該晶粒定位至該黏著材料，藉由一黏著材料將一第二未切層壓撓曲層緊固至初始層壓撓曲層之第二表面，固化第一未切層壓撓曲層與初始層壓撓曲層之間及第二未切層壓撓曲層與初始層壓撓曲層之間之黏著材料，及在第一及第二未切層壓撓曲層之中及在第一及第二未切層壓撓曲層之上形成複數個通孔及複數個金屬互連，該複數個金屬互連中之各者延伸通過一各自通孔且直接金屬化至初始層壓撓曲層上之一金屬互連及晶粒上之一晶粒墊中之一者。
根據本發明之另一實施例，形成一嵌入式晶片封裝之一方法包括在一中心層壓層中形成複數個通孔，形成延伸通過該複數個通孔之 複數個金屬互連以在中心層壓層之相對第一及第二表面中之各者上形成互連，形成通過中心層壓層之一晶片開口，藉由一黏著材料將一第一未切層壓層施加至中心層壓層之第一表面，及在中心層壓層之一晶片開口中定位一晶片且將該晶片定位至該黏著材料上，該晶片具有與中心層壓層之一厚度相等之一厚度。該方法亦包括藉由一黏著材料將一第二未切層壓層施加至中心層壓層之第二表面，固化第一未切層壓層與中心層壓層之間及第二未切層壓層與中心層壓層之間之黏著材料，及圖案化第一及第二未切層壓層以形成複數個通孔及複數個金屬互連，使得該複數個金屬互連中之各者延伸通過一各自通孔且直接金屬化至中心層壓層上之一金屬互連及晶片上之一晶片墊中之一者。
根據本發明之另一實施例，藉由包括以下步驟之一程序來製造一嵌入式晶片封裝：預圖案化一中心層壓層以形成複數個通孔及延伸通過該複數個通孔之複數個金屬互連，其中該複數個金屬互連在該中心層壓層之相對第一及第二表面中之各者上形成互連。該程序亦包括形成通過中心層壓層之一晶粒開口，藉由一黏著材料將一第一未切層壓層施加至該中心層壓層之該第一表面，在該中心層壓層之該晶粒開口內定位一晶粒且將該晶粒定位至該黏著材料上，該晶粒具有與該中心層壓層之一厚度相等之一厚度，藉由一黏著材料將一第二未切層壓層施加至該中心層壓層之該第二表面，在同一時間一起固化該第一未切層壓撓曲層與該基層壓撓曲層之間及該第二未切層壓撓曲層與該基層壓撓曲層之間之該黏著材料，及執行一雙面圖案化於該等第一及第二未切層壓撓曲層以形成複數個通孔及複數個金屬互連，其中自一第一方向形成該第一未切層壓撓曲層之該複數個通孔及該複數個金屬互連且自與該第一方向相反之一第二方向形成該第二未切層壓撓曲層之該複數個通孔及該複數個金屬互連。
雖然僅結合一有限數目之實施例描述本發明，但應容易地理 解，本發明不限於此等所揭示之實施例。相反地，本發明可經修改以併入在此之前未描述但與本發明之精神及範圍相稱之任何數目之變化型式、變更、替代或等效配置。此外，雖然已描述本發明之各種實施例，但應理解本發明之態樣可僅包括所描述之實施例中之一些。因此，不將本發明視為由以上描述限制，而將本發明視為僅由隨附申請專利範圍之範圍限制。
10‧‧‧埋入式晶粒模組
18‧‧‧未切初始或「中心」層壓撓曲層
22‧‧‧金屬互連
30‧‧‧晶粒
32‧‧‧未切層壓撓曲層
34‧‧‧黏著劑/黏著材料/層
38‧‧‧未切層壓撓曲層
40‧‧‧晶粒上之墊/晶粒墊
48‧‧‧額外未切層壓撓曲層/額外層壓撓曲層
50‧‧‧額外未切層壓撓曲層/額外層壓撓曲層
51‧‧‧黏著材料
52‧‧‧焊接遮罩層/焊接遮罩

Claims (20)

  1. 一種形成一埋入式晶粒模組之方法，其包含：提供一初始層壓撓曲層；在該初始層壓撓曲層中及該初始層壓撓曲層上形成複數個通孔及複數個金屬互連，該複數個金屬互連延伸通過各自通孔以在該初始層壓撓曲層之相對第一及第二表面中之各者上形成互連；形成通過該初始層壓撓曲層之一晶粒開口；藉由一黏著材料將一第一未切層壓撓曲層緊固至該初始層壓撓曲層之該第一表面；在該初始層壓撓曲層之該晶粒開口內定位一晶粒且將該晶粒定位至該黏著材料上；藉由一黏著材料將一第二未切層壓撓曲層緊固至該初始層壓撓曲層之該第二表面；固化該第一未切層壓撓曲層與該初始層壓撓曲層之間及該第二未切層壓撓曲層與該初始層壓撓曲層之間之該黏著材料；及在該等第一及第二未切層壓撓曲層中及在該等第一及第二未切層壓撓曲層上形成複數個通孔及複數個金屬互連，該複數個金屬互連中之各者延伸通過一各自通孔且直接金屬化至該初始層壓撓曲層上之一金屬互連及該晶粒上之一晶粒墊中之一者。
  2. 如請求項1之方法，其進一步包含：藉由一黏著材料將一額外未切層壓撓曲層緊固至該等第一及第二未切層壓撓曲層中之各者；選擇性地圖案化該等額外未切層壓撓曲層中之各者以形成複數個通孔及複數個金屬互連，其中該複數個金屬互連中之各者 延伸通過一各自通孔且直接金屬化至該等第一及第二未切層壓撓曲層之一各自一者上之一金屬互連。
  3. 如請求項1之方法，其進一步包含：將該第一未切層壓撓曲層真空層壓至該初始層壓撓曲層；及將該第二未切層壓撓曲層真空層壓至該初始層壓撓曲層。
  4. 如請求項3之方法，其中形成該晶粒開口包含形成具有大於該晶粒之一面積之一面積之一開口，使得當將該晶粒定位在該開口內時在該晶粒周圍存在一圍溝區域；且其中由於該等第一及第二未切層壓撓曲層至該初始層壓撓曲層之該真空層壓因此該圍溝區域被黏著材料完全填充，使得在該晶粒周圍不存在空隙。
  5. 如請求項1之方法，其中該晶粒具有等於該初始層壓撓曲層之一厚度之一厚度。
  6. 如請求項1之方法，其中將該第一未切層壓撓曲層緊固至該初始層壓撓曲層之該第一表面包含：以該黏著材料塗敷該第一未切層壓撓曲層；及藉由該黏著材料將該第一未切層壓撓曲層層壓至該初始層壓撓曲層。
  7. 如請求項6之方法，其中在防止該黏著材料之固化之一溫度下將該等第一及第二未切層壓撓曲層層壓至該初始層壓撓曲層。
  8. 如請求項1之方法，其中具有定位在形成在該初始層壓撓曲層中之該晶粒開口內之該晶粒之該初始層壓撓曲層包含該埋入式晶粒模組中之一中心層壓撓曲層，其中一相等數目之未切層壓撓曲層分別添加至該中心層壓撓曲層之該等第一及第二表面。
  9. 如請求項1之方法，其中形成該複數個金屬互連包含：在該層壓撓曲層上沈積一金屬材料；及 圖案化及蝕刻該金屬材料以形成該等金屬互連。
  10. 如請求項1之方法，其進一步包含：形成通過該初始層壓撓曲層之一第二晶粒開口；在該初始層壓撓曲層之該第二晶粒開口內定位一第二晶粒且將該第二晶粒定位至該第一未切層壓撓曲層上之該黏著材料。
  11. 一種形成嵌入式晶片封裝之方法，其包含：在一中心層壓層中形成複數個通孔；形成延伸通過該複數個通孔之複數個金屬互連以在該中心層壓層之相對第一及第二表面之各者上形成互連；形成通過該中心層壓層之一晶片開口；藉由一黏著材料將一第一未切層壓層施加至該中心層壓層之該第一表面；在該中心層壓層之該晶片開口內定位一晶片且將該晶片定位至該黏著材料上，該晶片具有等於該中心層壓層之一厚度之一厚度；藉由一黏著材料將一第二未切層壓層施加至該中心層壓層之該第二表面；固化該第一未切層壓層與該中心層壓層之間及該第二未切層壓層與該中心層壓層之間之該黏著材料；及圖案化該等第一及第二未切層壓層以形成複數個通孔及複數個金屬互連，使得該複數個金屬互連中之各者延伸通過一各自通孔且直接金屬化至該中心層壓層上之一金屬互連及該晶片上之一晶片墊中之一者。
  12. 如請求項11之方法，其進一步包含：將該第一未切層壓層真空層壓至該中心層壓層；及將該第二未切層壓層真空層壓至該中心層壓層。
  13. 如請求項12方法，其進一步包含：藉由一黏著材料將一額外層壓層緊固至該等第一及第二未切層壓層之各者；圖案化該等額外層壓層中之各者以形成複數個通孔及複數個金屬互連，其中該複數個金屬互連中之各者延伸通過一各自通孔且直接金屬化至該等第一及第二未切層壓層之一各自一者上之一金屬互連。
  14. 如請求項11方法，其中形成該晶片開口包含形成具有大於該晶片之一面積之一面積之一開口，使得當該晶片定位在該開口中時在該晶片周圍存在一圍溝區域；且其中由於該等第一及第二未切層壓層至該中心層壓層之該真空層壓因此該圍溝區域被黏著材料完全填充，使得在該晶片周圍不存在空隙。
  15. 如請求項11方法，其中在防止該黏著材料之固化之一溫度下將該等第一及第二未切層壓層施加至該中心層壓層。
  16. 如請求項11方法，其中圖案化該等第一及第二未切層壓層包含：自一第一方向形成該第一未切層壓層中之複數個通孔；及自一第二方向形成該第二未切層壓層中之複數個通孔。
  17. 一種藉由包含以下步驟之一程序製造之嵌入式晶片封裝：預圖案化一中心層壓層以形成複數個通孔及延伸通過該複數個通孔之複數個金屬互連，其中該複數個金屬互連在該中心層壓層之相對第一及第二表面之各者上形成互連；形成通過該中心層壓層之一晶粒開口；藉由一黏著材料將一第一未切層壓層施加至該中心層壓層之該第一表面；在該中心層壓層之該晶粒開口內定位一晶粒且將該晶粒定位 至該黏著材料上，該晶粒具有等於該中心層壓層之一厚度之一厚度；藉由一黏著材料將一第二未切層壓層施加至該中心層壓層之該第二表面；在同一時間一起固化該第一未切層壓撓曲層與基層壓撓曲層之間及該第二未切層壓撓曲層與該基層壓撓曲層之間之該黏著材料；及執行一雙面圖案化於該等第一及第二未切層壓撓曲層以形成複數個通孔及複數個金屬互連，其中自一第一方向形成該第一未切層壓撓曲層之該複數個通孔及該複數個金屬互連，且自與該第一方向相反之一第二方向形成該第二未切層壓撓曲層之該複數個通孔及該複數個金屬互連。
  18. 如請求項17之嵌入式晶片封裝，其中該程序進一步包含將該等第一及第二未切層壓撓曲層真空層壓至該初始層壓撓曲層，以便以該黏著材料填充在圍繞該晶粒之一圍溝區域中存在之任何空隙。
  19. 如請求項17之嵌入式晶片封裝，其中該晶粒具有等於該初始層壓撓曲層之一厚度之一厚度。
  20. 如請求項17之嵌入式晶片封裝，其中該嵌入式晶片結構基於在該中心層壓層上雙面層壓該等第一及第二未切層壓層及在該第一未切層壓層與該中心層壓層之間及在該第二未切層壓層與該中心層壓層之間施加一相同黏著材料而包含一完全平衡之結構。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI619413B (zh) * 2015-08-03 2018-03-21 Jx Nippon Mining & Metals Corp 印刷配線板之製造方法、表面處理銅箔、積層體、印刷配線板、半導體封裝及電子機器
TWI648854B (zh) * 2017-06-14 2019-01-21 穩懋半導體股份有限公司 用以減少化合物半導體晶圓變形之改良結構
CN110050332A (zh) * 2016-12-31 2019-07-23 英特尔公司 电子器件封装
TWI771273B (zh) * 2015-07-03 2022-07-21 日商安靠科技日本公司 半導體裝置及其製造方法

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8658473B2 (en) * 2012-03-27 2014-02-25 General Electric Company Ultrathin buried die module and method of manufacturing thereof
KR20150074785A (ko) * 2013-12-24 2015-07-02 삼성전기주식회사 빌드업 절연필름, 그를 이용한 전자부품 내장형 인쇄회로기판 및 그 제조방법
US9806051B2 (en) * 2014-03-04 2017-10-31 General Electric Company Ultra-thin embedded semiconductor device package and method of manufacturing thereof
US9930793B2 (en) * 2014-03-27 2018-03-27 Intel Corporation Electric circuit on flexible substrate
US9601353B2 (en) * 2014-07-30 2017-03-21 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with molding structures and methods of forming the same
US9653438B2 (en) 2014-08-21 2017-05-16 General Electric Company Electrical interconnect structure for an embedded semiconductor device package and method of manufacturing thereof
US10553557B2 (en) 2014-11-05 2020-02-04 Infineon Technologies Austria Ag Electronic component, system and method
US10064287B2 (en) * 2014-11-05 2018-08-28 Infineon Technologies Austria Ag System and method of providing a semiconductor carrier and redistribution structure
US10192846B2 (en) 2014-11-05 2019-01-29 Infineon Technologies Austria Ag Method of inserting an electronic component into a slot in a circuit board
JP2016219477A (ja) * 2015-05-15 2016-12-22 イビデン株式会社 電子部品内蔵配線板及びその製造方法
WO2017022807A1 (ja) * 2015-08-03 2017-02-09 Ｊｘ金属株式会社 プリント配線板の製造方法、表面処理銅箔、積層体、プリント配線板、半導体パッケージ及び電子機器
KR102384863B1 (ko) * 2015-09-09 2022-04-08 삼성전자주식회사 반도체 칩 패키지 및 이의 제조 방법
EP3206229B1 (en) * 2016-02-09 2020-10-07 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Methods of manufacturing flexible electronic devices
CN107295746B (zh) * 2016-03-31 2021-06-15 奥特斯(中国)有限公司 器件载体及其制造方法
US20170373011A1 (en) * 2016-06-28 2017-12-28 General Electric Company Semiconductor die backside devices and methods of fabrication thereof
KR102566996B1 (ko) * 2016-09-09 2023-08-14 삼성전자주식회사 FOWLP 형태의 반도체 패키지 및 이를 가지는 PoP 형태의 반도체 패키지
KR101994748B1 (ko) * 2016-09-12 2019-07-01 삼성전기주식회사 팬-아웃 반도체 패키지
CN106876291B (zh) * 2016-12-30 2020-04-10 清华大学 一种薄芯片柔性扇出封装方法及所制备的封装结构
CN106711053B (zh) * 2016-12-30 2019-09-17 清华大学 薄芯片柔性封装方法及所制备的封装结构
EP3557608A1 (en) * 2018-04-19 2019-10-23 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Packaged integrated circuit with interposing functionality and method for manufacturing such a packaged integrated circuit
US11227841B2 (en) * 2018-06-28 2022-01-18 Intel Corporation Stiffener build-up layer package
DE102019117844A1 (de) * 2018-09-27 2020-04-02 Taiwan Semiconductor Manufacturing Co., Ltd. Integrierte-schaltung-package und verfahren
US20200161206A1 (en) * 2018-11-20 2020-05-21 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and semiconductor manufacturing process
CN110957269A (zh) * 2019-11-08 2020-04-03 广东佛智芯微电子技术研究有限公司 一种改善埋入式扇出型封装结构电镀性能的制作方法

Family Cites Families (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5353498A (en) 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
US5567657A (en) 1995-12-04 1996-10-22 General Electric Company Fabrication and structures of two-sided molded circuit modules with flexible interconnect layers
US5841193A (en) * 1996-05-20 1998-11-24 Epic Technologies, Inc. Single chip modules, repairable multichip modules, and methods of fabrication thereof
JP3051700B2 (ja) 1997-07-28 2000-06-12 京セラ株式会社 素子内蔵多層配線基板の製造方法
JP3798597B2 (ja) 1999-11-30 2006-07-19 富士通株式会社 半導体装置
US20020020898A1 (en) 2000-08-16 2002-02-21 Vu Quat T. Microelectronic substrates with integrated devices
JP2002164475A (ja) * 2000-11-24 2002-06-07 Nitto Denko Corp 半導体装置
JP4694007B2 (ja) 2001-02-14 2011-06-01 イビデン株式会社 三次元実装パッケージの製造方法
JP2002246745A (ja) 2001-02-14 2002-08-30 Ibiden Co Ltd 三次元実装パッケージ及びその製造方法、三次元実装パッケージ製造用接着材
JP2002270712A (ja) * 2001-03-14 2002-09-20 Sony Corp 半導体素子内蔵多層配線基板と半導体素子内蔵装置、およびそれらの製造方法
US6706553B2 (en) * 2001-03-26 2004-03-16 Intel Corporation Dispensing process for fabrication of microelectronic packages
US7332819B2 (en) 2002-01-09 2008-02-19 Micron Technology, Inc. Stacked die in die BGA package
US20030116860A1 (en) 2001-12-21 2003-06-26 Biju Chandran Semiconductor package with low resistance package-to-die interconnect scheme for reduced die stresses
JP2003234432A (ja) 2002-02-08 2003-08-22 Ibiden Co Ltd 半導体チップ実装回路基板および多層化回路基板
EP2866258B1 (en) 2002-05-31 2019-04-17 Socionext Inc. Semiconductor device and manufacturing method thereof
TWI251916B (en) 2003-08-28 2006-03-21 Phoenix Prec Technology Corp Semiconductor assembled heat sink structure for embedding electronic components
JP2005317903A (ja) 2004-03-31 2005-11-10 Alps Electric Co Ltd 回路部品モジュール、回路部品モジュールスタック、記録媒体およびこれらの製造方法
DE102004041889B4 (de) 2004-08-30 2006-06-29 Infineon Technologies Ag Halbleitervorrichtung mit gestapelten Halbleiterbauelementen und Verfahren zu deren Herstellung
KR100688768B1 (ko) * 2004-12-30 2007-03-02 삼성전기주식회사 칩 내장형 인쇄회로기판 및 그 제조 방법
KR100716815B1 (ko) * 2005-02-28 2007-05-09 삼성전기주식회사 칩 내장형 인쇄회로기판 및 그 제조방법
TWI261329B (en) 2005-03-09 2006-09-01 Phoenix Prec Technology Corp Conductive bump structure of circuit board and method for fabricating the same
US7640655B2 (en) 2005-09-13 2010-01-05 Shinko Electric Industries Co., Ltd. Electronic component embedded board and its manufacturing method
KR100700922B1 (ko) * 2005-10-17 2007-03-28 삼성전기주식회사 수동 소자를 내장한 기판 및 그 제조 방법
KR100796523B1 (ko) * 2006-08-17 2008-01-21 삼성전기주식회사 전자부품 내장형 다층 인쇄배선기판 및 그 제조방법
JP2008085310A (ja) * 2006-08-28 2008-04-10 Clover Denshi Kogyo Kk 多層プリント配線基板
US7504283B2 (en) * 2006-12-18 2009-03-17 Texas Instruments Incorporated Stacked-flip-assembled semiconductor chips embedded in thin hybrid substrate
TWI330401B (en) * 2006-12-25 2010-09-11 Unimicron Technology Corp Circuit board structure having embedded semiconductor component and fabrication method thereof
US20080318413A1 (en) 2007-06-21 2008-12-25 General Electric Company Method for making an interconnect structure and interconnect component recovery process
US7868445B2 (en) * 2007-06-25 2011-01-11 Epic Technologies, Inc. Integrated structures and methods of fabrication thereof with fan-out metallization on a chips-first chip layer
SG148901A1 (en) 2007-07-09 2009-01-29 Micron Technology Inc Packaged semiconductor assemblies and methods for manufacturing such assemblies
KR100885924B1 (ko) 2007-08-10 2009-02-26 삼성전자주식회사 묻혀진 도전성 포스트를 포함하는 반도체 패키지 및 그제조방법
US8039303B2 (en) * 2008-06-11 2011-10-18 Stats Chippac, Ltd. Method of forming stress relief layer between die and interconnect structure
US8114708B2 (en) * 2008-09-30 2012-02-14 General Electric Company System and method for pre-patterned embedded chip build-up
US8008125B2 (en) * 2009-03-06 2011-08-30 General Electric Company System and method for stacked die embedded chip build-up
TWI399140B (zh) * 2009-06-12 2013-06-11 Unimicron Technology Corp 內埋式封裝結構的製作方法
JP2011014728A (ja) * 2009-07-02 2011-01-20 Casio Computer Co Ltd 半導体装置及び半導体装置の製造方法
JP5280309B2 (ja) * 2009-07-17 2013-09-04 新光電気工業株式会社 半導体装置及びその製造方法
JP5617846B2 (ja) * 2009-11-12 2014-11-05 日本電気株式会社 機能素子内蔵基板、機能素子内蔵基板の製造方法、及び、配線基板
US8742561B2 (en) * 2009-12-29 2014-06-03 Intel Corporation Recessed and embedded die coreless package
JP5001395B2 (ja) * 2010-03-31 2012-08-15 イビデン株式会社 配線板及び配線板の製造方法
US9262015B2 (en) 2010-06-28 2016-02-16 Intel Corporation System for portable tangible interaction
US8653670B2 (en) * 2010-06-29 2014-02-18 General Electric Company Electrical interconnect for an integrated circuit package and method of making same
US8623699B2 (en) * 2010-07-26 2014-01-07 General Electric Company Method of chip package build-up
US8304913B2 (en) * 2010-09-24 2012-11-06 Intel Corporation Methods of forming fully embedded bumpless build-up layer packages and structures formed thereby
US8384227B2 (en) * 2010-11-16 2013-02-26 Stats Chippac, Ltd. Semiconductor device and method of forming interposer frame electrically connected to embedded semiconductor die
US8658473B2 (en) * 2012-03-27 2014-02-25 General Electric Company Ultrathin buried die module and method of manufacturing thereof

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI771273B (zh) * 2015-07-03 2022-07-21 日商安靠科技日本公司 半導體裝置及其製造方法
TWI619413B (zh) * 2015-08-03 2018-03-21 Jx Nippon Mining & Metals Corp 印刷配線板之製造方法、表面處理銅箔、積層體、印刷配線板、半導體封裝及電子機器
CN110050332A (zh) * 2016-12-31 2019-07-23 英特尔公司 电子器件封装
US11830848B2 (en) 2016-12-31 2023-11-28 Intel Corporation Electronic device package
TWI648854B (zh) * 2017-06-14 2019-01-21 穩懋半導體股份有限公司 用以減少化合物半導體晶圓變形之改良結構

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