TW201138027A - Semiconductor device - Google Patents

Abstract

An object is to provide a semiconductor device that can realize a function of a thyristor without complication of the process. A semiconductor device including a memory circuit that stores a predetermined potential by reset operation and initialization operation is provided with a circuit that rewrite data in the memory circuit in accordance with supply of a trigger signal. The semiconductor device has a structure in which a current flowing through the semiconductor device is supplied to a load by rewriting data in the memory circuit, and thus can function as a thyristor.

Description

201138027 VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device and a method for driving the same. In this specification and the like, the term "semiconductor device" means all devices that can be operated by utilizing semiconductor characteristics. For example, display devices and integrated circuits are included in the category of semiconductor devices. [Prior Art] It is known that a thyristor system as a power device is formed in a single crystal germanium substrate and held in a conducting state by a trigger signal such as a current (for example, see Patent Document 1). The thyristor includes a pnp layer in which a p-type semiconductor layer and an n-type semiconductor layer are alternately arranged. An equivalent circuit of the thyristor is composed of an npn bipolar transistor (hereinafter referred to as an npn transistor) and a pnp bipolar transistor. Figure 12 depicts a particular circuit configuration. FIG. 12 illustrates a thyristor 1 1 包括 including an npn transistor 1101 and a pnp transistor 11〇2. In the thyristor 1 1 , the emitter terminal of the npn transistor 1 1〇1 is connected to the wiring 1 103 to which the high power supply potential VDD is supplied; the collector terminal of the npn transistor 1101 is connected to the pnp transistor 11〇2 a base terminal and a supply terminal to which the trigger signal is supplied: a base terminal of the npn transistor 1101 is connected to the collector terminal of the pnp transistor 1102; and an emitter terminal of the pnp transistor 1 1 02 is connected to the supply low power source The wiring VSS to which the potential VSS is connected. 201138027 The operation of the thyristor in Figure 12 will be described. When the trigger signal is an L signal (also referred to as a low level signal or a low level signal), electrical continuity is not established between the collector terminal and the emitter terminal of the pnp transistor 1 1 02 (ie, a pnp transistor) 1 1 02 is off), and almost no current flowing through the collector terminal of the pnp transistor 1102 (hereinafter referred to as collector current) is detected. Therefore, almost no current flowing through the base terminal of the npn transistor 1 1 0 1 (hereinafter referred to as base current) is detected, so the npn transistor 1 101 is also turned off and almost no current flows through the wiring 1 1 〇 3 Between wiring 1 1 04. When the trigger signal is a chirp signal, also referred to as a high level signal or a high level signal, electrical continuity is established between the collector terminal and the emitter terminal of the pnp transistor 1 1 02 (ie, the pnp transistor 1 102 is Kaitong). Therefore, the base current of the npn transistor 1 101 flows, and the npn transistor 1 101 is brought into conduction. When the npn transistor 1 1 0 1 is brought into conduction, the set of npn transistors 1 1 0 1 is detected. The pole current is maintained and the pnp transistor 1102 is maintained in an on state. The thyristor 1 100 has a feature such that a large current obtained by applying a collector current of the pnp transistor 1 102 to the collector current of the npn transistor 1 1 01 flows to the wiring 1 1 〇 3 and the wiring 1 1 04 between. [Reference] Patent Document 1: Japanese Laid-Open Patent Application No. H1 1 - 3 54774 SUMMARY OF THE INVENTION The thyristor shown in Fig. 12 is formed by a combination of pn junctions in a single crystal semiconductor substrate. In view of this, the thyristor is formed when combined with a procedure for forming an insulating gate transistor (also known as an insulated gate field effect transistor (IGFET) or a metal insulator half 201138027 conductor field effect transistor (MIS FET)). Become complicated. Further, when a thin film transistor (which is an insulating gate transistor including a semiconductor layer) is used to form a thyristor, such as withstanding a voltage, a desired function cannot be obtained. In view of the above, it is an object of the present invention to provide a semiconductor device which can be realized without complicating the program. An embodiment of the present invention is a semiconductor device comprising nine insulated gate transistors, a capacitor, a first high power supply, a first wiring, a second high power supply potential supplied thereto, and a low The power supply potential is supplied to one of the third wirings. One of the gates of the edge gate transistor is electrically connected to an input terminal. A first terminal of the gate transistor is electrically connected to the third wiring. A second terminal of the edge gate transistor is electrically coupled to the first terminal of the second insulator. One of the second insulating gate transistors is gated to a first terminal of the seventh insulating gate transistor and a first terminal of the eighth transistor. The second insulating gate transistor is electrically connected to one of the first terminal of the third insulating gate transistor, the first terminal of the insulating gate transistor, and the gate of the sixth insulating gate. One of the gates of the third insulated gate transistor is electrically connected to a wiring. One of the second terminals of the third insulated gate transistor is electrically connected to the second wiring. One of the fourth insulated gate transistors electrically connects one of the first terminals of the five insulated gate transistors, the first terminal of the sixth insulating gate, the first electrode of the capacitor, and the eighth transistor When one of the gates and one of the ninth insulated gate transistors is used, the program includes a ruthenium film, which generates a first to a first supply of the current brake fluid to a second cloth. The first first insulation is the first insulation. The galvanic electrode is electrically connected to the second end of the insulating gate, and the fourth transistor is connected to the first gate to the gate of the first transistor. The second terminal of the 201138027 fourth insulating gate transistor is electrically connected to one of the fifth insulating gate transistors, and the second terminal of the fifth insulating gate transistor is electrically connected to the second terminal of the fifth insulating gate transistor One of the second terminals of the sixth insulated gate transistor is electrically connected to. A gate of the seventh insulating gate transistor is electrically connected to a second terminal of the seventh insulating gate transistor electrically connected to . One of the eighth insulated gate transistors is electrically connected to the second terminal. One of the first terminals of the ninth insulating gate transistor is electrically connected to the terminal. One of the second terminals of the ninth insulating gate transistor is electrically wired. A second electrode of the capacitor is electrically coupled to the semiconductor device according to an embodiment of the present invention. The nine insulated gate transistors may each comprise an oxide semiconductor conductor layer. In accordance with an embodiment of the present invention, a semiconductor device can include a first terminal of the resistor electrically connectable to the gate of the first insulation. The second terminal of one of the resistors may be electrically connected to 0. In the semiconductor device according to an embodiment of the present invention, the mass spectrum detects that the concentration of hydrogen in the oxide semiconductor may be or less. In a semiconductor device according to an embodiment of the present invention, the carrier concentration of the semiconductor may be less than lxio14 / cm3. In accordance with an embodiment of the present invention, a semiconductor device circuit. The gate and the third wiring of the fourth insulating gate transistor. A wiring. The second wiring. The third wiring first wiring. The first wiring to the third wiring to an output is connected to the first wiring. , the first to the first half of the formed resistor. The third wiring of the gate transistor is made of a secondary ion IxlO16 /cm3, and the oxide may include the first terminal of the fifth insulating -8-201138027 gate transistor, the sixth insulating gate transistor a potential of the first terminal, the first electrode of the capacitor, and a node of the gate electrical connection of the eighth insulating gate transistor can be supplied to the ninth insulating gate transistor via the buffer circuit The gate. In a semiconductor device according to an embodiment of the present invention, the buffer circuit may include tenth to thirteenth insulating gate transistors. A gate of the tenth insulating gate transistor is electrically connectable to the first wiring. A first terminal of the tenth insulating gate transistor is electrically connectable to the second wiring. A second terminal of the tenth insulating gate transistor is electrically coupled to a first terminal of the eleventh insulating gate transistor and a gate of the thirteenth insulating gate transistor. a gate of the eleventh insulating gate transistor is electrically connected to the gate of the fourth insulating gate transistor, the first terminal of the fifth insulating gate transistor, and the sixth insulating gate The first terminal of the transistor, the first electrode of the capacitor, and the gate of the eighth insulating gate transistor. A second terminal of the eleventh insulating gate transistor is electrically connectable to the third wiring. A gate of the twelfth insulating gate transistor is electrically connectable to the first wiring. A first terminal of the twelfth insulating gate transistor is electrically connectable to the second wiring. A second terminal of the twelfth insulating gate transistor is electrically connectable to a first terminal of the thirteenth insulating gate transistor and the gate of the ninth insulating gate transistor. A second terminal of the thirteenth insulating gate transistor is electrically connectable to the third wiring. In a semiconductor device according to an embodiment of the present invention, the buffer circuit includes tenth to thirteenth insulating gate transistors. a gate of the tenth insulating gate transistor can be electrically connected to the gate -9 - 201138027 pole of the second insulating gate transistor, the first terminal of the seventh insulating gate transistor, and the first The first terminal of the eight insulated gate transistor. A first terminal of the tenth insulating gate transistor is electrically connectable to the second wiring. A second terminal of the tenth insulating gate transistor is electrically connectable to a first terminal of the eleventh insulating gate transistor and a gate of the thirteenth insulating gate transistor. a gate of the eleventh insulating gate transistor is electrically connected to the gate of the fourth insulating gate transistor, the first terminal of the fifth insulating gate transistor, and the sixth insulating gate The first terminal of the transistor, the first electrode of the capacitor, the gate of the eighth insulating gate transistor, and the gate of the twelfth insulating gate transistor" the eleventh insulating gate A second terminal of the polar transistor can be electrically connected to the third wiring. A first terminal of the twelfth insulating gate transistor can be electrically connected to the second wiring. A second terminal of the twelfth insulating gate transistor is electrically connectable to a first terminal of the thirteenth insulating gate transistor and the gate of the ninth insulating gate transistor. A second terminal of the thirteenth insulating gate transistor is electrically connectable to the third wiring. In the semiconductor device according to an embodiment of the present invention, the first high power supply potential and the second high power supply potential are the same. According to an embodiment of the present invention, a high withstand voltage can be provided and a thyristor can be realized. A semiconductor device that functions without complicating the program. [Embodiment] Embodiments will be described in detail with reference to the drawings. It is noted that the invention may be embodied in a number of different modes, and those skilled in the art will readily appreciate that the modes and details of the invention can be modified in various ways without departing from the spirit of the invention and the scope of the invention. Therefore, the invention should not be construed as being limited to the description in the following examples. It is noted that in the detailed description of the invention, the same reference It is noted that the dimensions, thicknesses, and regions of the various structures shown in the figures or the like in the embodiments are exaggerated in some cases for clarity. Therefore, the embodiments of the present invention are not limited to such cases. It is noted that terms such as first, second, third to # (iV are natural numbers) employed in this specification are used to avoid confusion between components and are not limited in number. (Embodiment 1) In this embodiment, first, referring to Figs. 1, 2A and 2B, 3A to 3C, and 4A to 4C, the circuit configuration of the semiconductor device will be described, and then the semiconductor device will be explained. Operation. In Fig. 1, a semiconductor device shown in this embodiment and having a function equivalent to a thyristor includes a first insulating gate transistor 110, a second insulating gate transistor 102, and a third insulating gate. Polar crystal 101, fourth insulated gate transistor 104, fifth insulated gate transistor 051, sixth insulated gate transistor 1 〇6, seventh insulated gate transistor 1 〇7, eighth Insulated gate transistor 1 〇8, ninth insulated gate transistor 1 〇9, capacitor 1 1 〇, and resistor 11 〗. Each element included in the semiconductor device is controlled to be supplied with a trigger signal to the input terminal IN, a first high power supply potential VGG supplied to the first wiring i2, a second high power supply potential VDD supplied to the second wiring 113, Supplying a low power supply potential VSS (also referred to as a low power supply potential of -11 - 201138027) to the third wiring 1 14 to control flow between the first terminal and the second terminal of the ninth insulating gate transistor 109 Current. It is noted that the first to ninth insulating gate transistors included in the semiconductor device are n-channel insulating gate electric crystals. The gate of the first insulating gate transistor 1 〇 1 is connected to the input terminal IN. The first terminal of the first insulating gate transistor 1 〇 1 is connected to the third wiring 1 14 . A second terminal of the first insulating gate transistor 110 is coupled to a first terminal of the second insulating gate transistor 102. The gate of the second insulating gate transistor 102 is connected to the first terminal of the seventh insulating gate transistor 107 and the first terminal of the eighth insulating gate transistor 108. The second terminal of the second insulating gate transistor 102 is connected to the first terminal of the third insulating gate transistor · 03, the first terminal of the fourth insulating gate transistor 104, and the sixth insulating gate The gate of the crystal 106. The gate of the third insulating gate transistor 103 is connected to the first wiring 1 1 2 . The second terminal of the third insulating gate transistor 103 is connected to the second wiring 1 1 3 . The gate of the fourth insulating gate transistor 104 is connected to the first terminal of the fifth insulating gate transistor 105, the first terminal of the sixth insulating gate transistor 106, the first electrode of the capacitor 110, and the eighth A gate of the insulating gate transistor 1 〇8 and a gate of the ninth insulating gate transistor 1 〇9. The second terminal of the fourth insulating gate transistor 连接04 is connected to the third wiring 114. The gate of the fifth insulating gate transistor 105 is connected to the first wiring 1 1 2 . The second terminal of the fifth insulating gate transistor 105 is connected to the second wiring 113. The second terminal of the sixth insulating gate transistor 106 is connected to the third wiring 1 14 . The gate of the seventh insulating gate transistor 107 is connected to the first wiring 1 1 2 . The second terminal of the seventh insulated gate transistor 107 is connected to the first -12-201138027 two wiring 1 1 3 . The second terminal of the eighth insulating gate transistor 108 is connected to the third wiring 1 1 4 . The first terminal of the ninth insulating gate transistor 109 is connected to the output terminal OUT. The second terminal of the ninth insulating gate transistor 109 is connected to a terminal to which the second low power supply potential VSS2 is supplied. The second electrode of the capacitor 110 is connected to the third wiring 114. The inverter circuit is constituted by a third insulating gate transistor 103 and a fourth insulating gate transistor 104, and a fifth insulating gate transistor 1 〇5 and a sixth insulating gate transistor 106. The static memory circuit 1 15 is constituted by a combination of the inverter circuits. Further, the inverter circuit 1 16 is constituted by the seventh insulating gate transistor 107 and the eighth insulating gate transistor 108. Therefore, the third insulating gate transistor 103, the fifth insulating gate transistor 105, and the seventh insulating gate transistor 107 included in the inverter circuit each function as a resistor, and the current is from The second wiring 1 13 flows through it (also referred to as a constant current source for supplying a constant current). The second low power supply potential VSS2 supplied to the second terminal of the ninth insulating gate transistor 109 has a potential at which the potential is supplied to the ninth insulating gate transistor according to the potential of the second high power supply potential VDD. At the gate, the ninth insulating gate transistor 109 is brought into conduction. The second low power supply potential VSS2 may be a low power supply potential VSS. In other words, the semiconductor device shown in FIG. 1 may have a structure in which the first wiring 112 to which the first high power supply potential VGG is supplied and/or the second low power supply potential VSS2 is supplied to one of the terminals to be connected to A low power supply potential VSS is supplied to the third wiring 114 thereof as shown in FIG. 2A.

As shown in FIG. 2B, the load 117 can be connected to the output terminal OUT-13-201138027, which is connected to the first terminal of the ninth insulating gate transistor 109. When electrical continuity is established between the first terminal and the second terminal of the ninth insulating gate transistor 109, current flows through the load. Further, a resistor 1 1 1 is provided between the input terminal IN and the third wiring 114. The first terminal of the resistor 111 is connected to the input terminal IN, and the second terminal of the resistor 111 is connected to the third wiring 114. The placement of the resistor 111 prevents the first insulating gate transistor 101 from failing when a signal other than the trigger signal (e.g., noise) is input to the input terminal IN. The resistor 11 1 can be formed by guiding in a meandering shape (snake form). The capacitor 1 1 设置 is disposed such that the capacitance of a node on the first terminal side of the third insulating gate transistor 103 is different from the capacitance of a node on the first terminal side of the fifth insulating gate transistor 105 . The capacitor 110 has a structure in which an insulating layer is sandwiched between conductors. Further, the third insulating gate transistor 103 and the fifth insulating gate transistor 506 preferably have the same size. It is noted that an oxide semiconductor is used for a semiconductor layer included in each of the insulating gate electric crystals in the semiconductor device. By using an oxide semiconductor as the semiconductor layer of the insulating gate transistor, the field effect mobility can be made higher than that in the case where a germanium-based semiconductor material such as amorphous germanium is used. Unlike a thyristor formed by a combination of pn junctions in a single crystal semiconductor substrate, an insulating gate transistor in which an oxide semiconductor is used as a semiconductor layer is formed by stacking a material over a substrate. In view of this, limitations such as the size of the substrate can be relaxed and the complexity of the procedure for forming the semiconductor device can be reduced. Note that examples of the oxide semiconductor are oxidized (ZnO) and tin oxide (Sn02). In addition, you can add In, Ga, or the like -14- 201138027 to Ζ η Ο. Next, an oxide semiconductor layer using a semiconductor layer in each of the gate transistors in the structure of this embodiment will be explained. The hydrogen or ruthenium group contained in the oxide semiconductor used in this embodiment is removed from the oxide semiconductor so that the concentration of hydrogen in the oxide semiconductor is 1 x 10 16 /cm 3 or less. An insulating gate transistor is formed in which an oxide semiconductor layer having a carrier concentration of less than 5 x 1 014 /cm 3 ; preferably less than 1 x 10 12 /cm 3 ; more preferably less than 1 x 10 1 /cm 3 is formed. It is noted that the concentration of hydrogen in the oxide semiconductor layer is measured by secondary ion mass spectrometry (SIMS). The energy gap is 2 eV or more; preferably 2.5 eV or more; more preferably 3 eV or more. The carrier concentration is set to be less than lxl 〇 14 /cm 3 ; preferably less than lxlO12 /cm3; more preferably less than lxlO11 /cm3 or less by reducing the impurity (such as hydrogen) which will become a donor as much as possible. That is, the carrier concentration of the oxide semiconductor layer is made zero as much as possible. The insulating gate electrode in which the oxide semiconductor layer (which is highly purified by greatly reducing the hydrogen contained therein) as the channel formation region may have a shutdown current of 1x1 〇 16 A or less. In other words, the circuit can be designed to have an oxide semiconductor layer that can be considered an insulator when the insulating gate transistor is not conducting. Further, when the insulating gate transistor is turned on, it is expected that the current supply capability of the oxide semiconductor layer is higher than that of the semiconductor layer formed of amorphous germanium. It is noted that the off-state current in this specification means that when the insulating gate transistor is non-conducting (ie, the insulating gate transistor is off), it flows between the source and the -15-201138027 drain, that is, in the insulation. a current between the first terminal and the second terminal of the gate transistor. In the case of an n-channel insulated gate transistor, the off-state current means a flow between the source and the drain when the voltage applied between the gate and the source is equal to or lower than the threshold voltage (Vth). Current. Note that as the oxide semiconductor film, the following oxide semiconductor film can be used, for example, a four-component metal oxide film such as an In-Sn-Ga-Zn-iridium film; such as an In-Ga-Zn-O film, In-Sn a three-component metal oxide film of a -Zn-Ο film, an In-Al-Zn-Ο film, a Sn-Ga-Zn-Ο film, an Al-Ga-Ζη-Ο film, or a Sn-Al-Zn-Ο film; a two-component metal oxide film of an In-Zn-O film, a Sn-Zn-yttrium film, an Al-Zn-0 film, a Zn-Mg-yttrium film, a Sn-Mg-yttrium film, or an In-Mg-yttrium film; In-Ο film, Sn-Ο film, or Ζη-0 film. Further, the oxide semiconductor film may contain SiO 2 . As the oxide semiconductor film, a film represented by InMOHZnCOdmX)) can be used. Here, Μ represents one or more metal elements selected from the group consisting of Ga, A1, Μη, and Co. For example, Μ may be Ga, Ga and Al, Ga and Μη, Ga and Cο, or the like. The composition formula is an oxide semiconductor represented by InMCMZnO)TM (/«>0) (which includes at least Ga as yttrium), and is called an In-Ga-Zn-O oxide semiconductor, and a film of in-Ga_Zn_0 oxide semiconductor It is called an In-Ga-Zn-O film. Note that the first high power supply potential VGG and the second high power supply potential VDD are signals having a potential higher than the reference potential, and the low power supply potential VSS and the second low power supply potential VSS2 are at a potential lower than or equal to the reference potential. signal. Preferably, the first high power supply potential VGG, the second high power supply potential VDD, the low power supply potential VSS, and the second low power supply potential VSS2 are such that the insulating gate transistor is ideal when a high power supply potential is applied to the gate. (The threshold voltage is 〇V) is turned on and the ideal insulating gate transistor is turned off when a low power supply potential is applied to the gate. Note that in many cases the voltage is the potential difference between a given potential and a reference potential (eg ground potential). Therefore, the voltage, potential, and potential difference can also be referred to as potential or voltage. It is noted that the insulated gate transistor can have various structures and is not limited to a certain structure. For example, a multi-gate structure having two or more gate electrodes can be used. Further, a structure can be employed in which gate electrodes are disposed above and below the channel region. It is noted that when the gate electrode is formed above and below the channel region, a structure may be employed in which a plurality of insulating gate transistors are connected in parallel. It is noted that when "A and B are connected" are explicitly described, the case where A and B are electrically connected, the case where A and B are functional connections, and the case where A and B are directly connected are included herein. Here, each of A and B is an object (e.g., device, component, circuit, wiring, electrode, terminal, conductive film, or layer). Therefore, another element may be provided between the elements having the connection relationship shown in the drawings and the text, and is not limited to the predetermined connection relationship '', for example, the connection relationship shown in the figure and the text. Next, the operation of the semiconductor device shown in Fig. 1 will be explained with reference to Figs. 3A to 3C and Figs. 4A to 4C and have a function equivalent to that of the thyristor. Note that in the descriptions of FIGS. 3A to 3C and FIGS. 4A to 4C, 'node A (A in the figure) represents the second -17-201138027 terminal of the second insulating gate transistor 102, and the third insulating gate is electrically The first terminal of the crystal 103, the first terminal of the fourth insulating gate transistor 104, and the gate of the sixth insulating gate transistor 106 are at the nodes to which they are connected. In addition, in the descriptions of FIGS. 3A to 3C and FIGS. 4A to 4C, the node B (B in the figure) represents the gate of the fourth insulating gate transistor 104, and the fifth insulating gate transistor 105. a first terminal, a first terminal of the sixth insulating gate transistor 106, a first electrode of the capacitor 110, a gate of the eighth insulating gate transistor 108, and a ninth insulating gate transistor 109 The gate is at the node where it is connected. First, an operation will be described in which the power supply potential is supplied to the first to third wirings 1 1 2 to 1 1 4 to set the node A and the node B to a predetermined potential. Note This operation is also called reset operation (or first operation). First, the first high power supply potential VGG, the second high power supply potential VDD, and the low power supply potential VSS are respectively supplied to the first wiring 112, the second wiring 1 1 3, and the third wiring 1 1 4 so that the current is from the first The second wiring 1 1 3 flows through the third insulating gate transistor 103, the fifth insulating gate transistor 1 〇5, and the seventh insulating gate transistor 107 (see the dotted arrow in Fig. 3A). Next, the potential of the node A is raised by the current flowing through the third insulating gate transistor 1 〇 3 . Further, the potential of the node B is raised by the current flowing through the fifth insulating gate transistor. Also, the potential of the gate of the second insulating gate transistor 102 is raised by the current flowing through the seventh insulating gate transistor 107. Note that this operation corresponds to the first period T 1 in Figure 3C. Figure 3C shows the change in potential over time; the solid line represents the potential of node a and the dashed line represents the potential of node B. Note that in the 3rd C picture, 'Η' represents the potential of the second high power supply potential VDD supplied to the second wiring -18-201138027 1 1 3, and "L" represents the supply to the second wiring 1 1 3 The potential of the low power supply potential VSS.

As shown in Fig. 3C, the flow of current in the first period T1 will be due to the slope of the potential rise of the node A due to the passage of the third insulating gate transistor 103 and the flow through the fifth insulating gate. The difference between the slopes of the rise in the potential of the node B due to the polar transistor 1 〇5. When the third insulating gate transistor 103 and the fifth insulating gate transistor 105 have the same size as described above, the slope of the supplied current amount is the same but the potential of the node B rises higher than the potential of the node A. It is more moderate because the capacitor 11 is connected to the node B. In addition, in the first period T1, the gate of the second insulating gate transistor 102 is raised by the current flowing through the seventh insulating gate transistor 107. The potential is turned on and the second insulating gate transistor 102 is brought into conduction. It is noted that the trigger signal for turning on the first insulating gate transistor 1 〇 1 is not input to the input terminal IN, so the first insulating gate transistor 110 is brought out. Further, in the first period T1, the potentials of the node A and the node B are raised, and the fourth, sixth, eighth, and ninth insulating gate transistors are brought out. For the explanation, the intersection (X) is set on the insulating gate transistor in the non-conduction state in the 3A '3B, 4A, and 4B diagrams. Next, an operation will be explained in which the potentials of the node A and the node B are raised to change the conduction state and the non-conduction state of the insulating gate transistor. Note that this operation is also referred to as an initialization operation (or a second operation). In the description of the first period T 1 , a difference occurs between the slope at which the potential of the node A rises and the slope at which the potential of the node B rises, whereby the node -19-201138027 A is first set to the potential "Η". Therefore, the sixth insulating gate transistor 106 is brought into conduction and the potential of the node β is lowered to the potential "L" (see the dotted arrow in Fig. 3). Since the node ? is set to the potential "L", the fourth insulating gate transistor 104, the eighth insulating gate transistor 108, and the ninth insulating gate transistor 109 remain in the non-conducting state. Note that this operation corresponds to the second period Τ2 in Figure 3C. The flow of the current in the second period Τ2 determines the conduction state or the non-conduction state of the fourth insulating gate transistor 104 and the sixth insulating gate transistor 1 〇6 (which controls the potential of the node Β and the node )). In detail, the potential "Η" is held at node A and the potential "L" is maintained at node B. That is, the potential is maintained in the second period T2 as long as the first high power supply potential VGG, the second high power supply potential VDD, and the second high power supply potential VDD are supplied from the first wiring 112, the second wiring 1 13, and the third wiring 1 1 4, respectively. And low power supply potential VSS. Therefore, the ninth insulating gate transistor 109 is maintained in a non-conducting state. In the case where an oxide semiconductor is used as the semiconductor layer of the insulating gate transistor, when the insulating gate transistor is not turned on, the oxide semiconductor layer can be regarded as an insulator, and current flowing from the output terminal out can be maintained small. In the second period T2, as in the first period T1, the potential of the gate of the second insulating gate transistor 102 is raised by the current flowing through the seventh insulating gate transistor 107, and will be The two insulated gate transistors 102 are brought into conduction. It is noted that the trigger signal for turning on the first insulating gate transistor 1 〇 1 is not input to the input terminal IN, so that the first insulating gate transistor 101 is brought out. Next, an operation will be explained in which the conduction state and the non-conduction state of the insulating gate transistor are changed by the change of the potentials of the node A and the node B when the -20-201138027 trigger signal is input from the input terminal IN. Note that this operation is also referred to as a trigger input operation (or a third operation). It is noted that the trigger signal is a pulse signal for turning on the first insulating gate transistor 110. In detail, the Η signal is input as a trigger signal to cause current to flow to the output terminal OUT of the semiconductor device as the thyristor, i.e., to the ninth insulating gate transistor 1 〇9. After the current flows to the output terminal OUT of the semiconductor device, the output terminal OUT maintains the current flow as in the thyristor, even if the trigger signal is switched to the L signal. As in the description of the second period T2, the potential "H" is held at node A and the potential "L" is held at node B by the initialization operation. When the trigger signal is input from the input terminal IN in this state, the first insulating gate transistor 110 and the second insulating gate transistor 102 are brought into conduction and current flows from the node A toward the third wiring 1 1 4 (See the dotted arrow in Figure 4A). That is, the potential of the node A is lowered, and when the node A falls to the potential "L", the sixth insulating gate transistor 1 〇 6 is brought out. Note that this operation corresponds to the third period T3 in Fig. 4C. Next, an operation will be explained in which the on-state and non-conduction states of the insulating gate transistor are changed in the case where the trigger signal input from the input terminal IN is the L signal. Note that this operation is also referred to as a hold operation (or a fourth operation). As in the description of the third period T3, the potential of the node A is lowered to the potential "L" by the trigger input operation and the sixth insulating gate transistor 106 is brought out of conduction. When the sixth insulating gate transistor 1〇6 is turned on -21 - 201138027, the potential of the node B is increased from the potential "L" to the potential "Η". Then 'when the node Β is set to the potential “Η”, the fourth insulating gate transistor 104 is brought into conduction, and the fourth insulating gate transistor 1〇4 and the sixth insulating gate transistor 106 are determined. A conducting state or a non-conducting state (which controls the potential of the node Β and the node )) (see the dotted arrow in Fig. 4). Therefore, the fourth insulating gate transistor 104 and the eighth insulating gate transistor 1 are 〇8, the ninth insulating gate transistor 109 is brought into conduction. Note that this operation corresponds to the fourth period T4 in Figure 4C. It is noted that in the fourth period T4, the trigger signal is the L signal and the first insulating gate transistor 1 〇 1 is brought out. In addition, in the fourth period T4, the eighth insulating gate transistor 108 is brought into conduction, so the potential of the gate of the second insulating gate transistor 102 is lowered and the second insulating gate transistor 102 is removed. Bring out the conduction. By the above operation, the ninth insulating gate transistor 109 is maintained in the on state. It is noted that although depending on the amount of current flowing from the output terminal OUT, it is preferable to design the semiconductor layer in the ninth insulating gate transistor 109 to have a larger width than the semiconductor layer in the first to eighth insulating gate transistors. To increase the amount of current flowing through the ninth insulating gate transistor 109. The oxide semiconductor layer is preferably used because the current supply capability when the insulating gate transistor is turned on is expected to be higher than that of the semiconductor layer formed by the polysilicon. In order to bring the ninth insulating gate transistor 109 into conduction and then bring out the conduction again, the supply of the power source potential to the first to third wirings 1 1 2 to 114 is stopped. This operation is called a stop operation. In order to operate the semiconductor device again, a series of the above operations can be performed again as a reset operation. -22- 201138027 It is noted that those described in the embodiments of the present invention can be freely combined or replaced with those described in the embodiments. (Embodiment 2) In this embodiment, the circuit configuration illustrated in Figs. 5A and 5B will be referred to. This embodiment shows a configuration in which the snubber circuit is disposed in the first terminal of the gate of the crystal 109 and the fourth insulating gate transistor 104 of the insulating gate transistor 1 〇 5 in the following manner. Description of the first terminal of the sixth insulator 106, the first electrode of the capacitor 110, the gate of the polar transistor 108, and the portion of the electrical connection between the nodes of the electrical connection are similar to those of the embodiment 1. . The apparatus shown in Fig. 5A and having the equivalent of the thyristor and the semiconductor device of Fig. 1 of the first embodiment do not include the snubber circuit 200. The mitigation shown in Fig. 5A includes a tenth insulating gate transistor 2 1 0, an eleventh insulating film 21, a twelfth insulating gate transistor 2 1 2, and a thirteenth body 2 1 3 . The gate of the tenth insulated gate transistor 2 1 0 is connected to 1 1 2 . The first terminal line 1 1 3 of the tenth insulating gate transistor 2 10 . The second end of the tenth insulating gate transistor 2 10 is the first terminal of the eleven insulating gate transistor 2 1 1 and the gate of the tenth crystal 2 1 3 . The gates of the eleventh insulating gate transistor 2 to the fourth insulating gate transistor 104, and the fifth structure which is suitably obtained with other semiconductor devices: nine insulated gate electrodes and a fifth edge gate Polar crystal and eighth insulating gate. It is noted that a semiconductor that does not emphasize the function of, for example, a semiconductor package is similar in that its punch circuit 200 is gate-gated, and the gate is electrically connected to the first wiring to the second wiring to the third insulating gate. The gate is connected to the gate transistor -23-201138027 105, the first terminal, the first terminal of the sixth insulating gate transistor 106, the first electrode of the capacitor 1 10, and the eighth insulating gate transistor 1 The gate of 08. The second terminal of the eleventh insulating gate transistor 211 is connected to the third wiring 1 14 . The gate of the twelfth insulating gate transistor 2 1 2 is connected to the first wiring 112. The first terminal of the twelfth insulating gate transistor 212 is connected to the second wiring 1 13 . The second terminal of the twelfth insulating gate transistor 2 1 2 is connected to the first terminal of the thirteenth insulating gate transistor 2 1 3 and the gate of the ninth insulating gate transistor 109. The second terminal of the thirteenth insulating gate transistor 2 1 3 is connected to the third wiring 114. The buffer circuit has a structure in which an even number of inverter circuits (such as inverter circuit 116) (two inverter circuits in FIG. 5A) are combined as shown in FIG. 5A, whereby it is expected to be insulated by a gate The sequential increase of the size of the polar crystal improves the current supply capability, and the amount of current flowing to the output terminal OUT can be increased by the increase of the size of the ninth insulating gate transistor 109. FIG. 5B is a diagram showing The structure of the semiconductor device of the buffer circuit 201 of a different structure in FIG. 5A. The buffer circuit 201 shown in FIG. 5B includes a tenth insulating gate transistor 220, an eleventh insulating gate transistor 22 1 , a twelfth insulating gate transistor 222, and a thirteenth insulating gate electrode. Crystal 223. A gate of the tenth insulating gate transistor 220 is connected to the gate of the second insulating gate transistor 102, the first terminal of the seventh insulating gate transistor 107, and the eighth insulating gate transistor 108. The first terminal. The first terminal of the tenth insulating gate transistor 220 is connected to the second wiring 113. The second terminal of the tenth insulating gate transistor 220 is connected to the first terminal of the eleventh -24-201138027 insulating gate transistor 22 1 and the gate of the thirteenth insulating gate transistor 2 23 . The gate of the eleventh insulating gate transistor 22 1 is connected to the gate of the fourth insulating gate transistor 1 〇 4, the first terminal of the fifth insulating gate transistor 105, and the sixth insulating gate transistor The first terminal of 106, the first electrode of capacitor 1 10 0, the gate of eighth insulating gate transistor 1 〇 8 and the gate of twelfth insulating gate transistor 222. The second terminal of the eleventh insulating gate transistor 221 is connected to the third wiring 114. The first terminal of the twelfth insulating gate transistor 222 is connected to the second wiring 1 13 . The second terminal of the twelfth insulating gate transistor 222 is connected to the first terminal of the thirteenth insulating gate transistor 223 and the gate of the ninth insulating gate transistor 109. The second terminal of the thirteenth insulating gate transistor 223 is connected to the third wiring 1 14 . Unlike in the inverter circuit such as the inverter circuit 116, in the buffer circuit 201 in FIG. 5B, both the tenth insulating gate transistor 220 and the eleventh insulating gate transistor 221 can be shortened. The period of conduction and the twelfth insulating gate transistor 222 and the thirteenth insulating gate transistor 223 are both in a period of conduction, and can be reduced from the second wiring 1 13 to the first in the holding operation. Three wiring 1 1 4 current. It is to be noted that those described with reference to the figures in this embodiment can be freely combined with or substituted for those described in the other embodiments. (Embodiment 3) In this embodiment, the structure of the insulating gate transistors used in Embodiments 1 and 2 will be described with reference to Figs. 6A and 6B. Figure 6A is a top plan view of an insulated gate transistor 645. Figure 6B is a cross-sectional view taken along line A _ B in Figure 6A from -25 to 201138027. As shown in Fig. 6B, the first electrode 605, the oxide semiconductor film 607, and the second electrode 609 are stacked over the insulating film 603 formed over the substrate 601. A gate insulating film 61 1 is provided to cover the first electrode 605, the oxide semiconductor film 607, and the second electrode 609. A third electrode 613 is disposed above the gate insulating film 611. An insulating film 611 serving as a interlayer insulating film is provided over the gate insulating film 611 and the third electrode 613. An opening portion is formed in the insulating film 611 to form a wiring 631 (see FIG. 6A) and a wiring 629 which are respectively connected to the first electrode 605, the second electrode 609, and the third electrode 613 via the respective opening portions. Wiring 625. The first electrode 605 serves as one of the drain electrode and the source electrode of the insulating gate transistor 645. The second electrode 609 serves as the other of the drain electrode and the source electrode of the insulating gate transistor 645. The third electrode 613 functions as a gate electrode of the insulating gate transistor 645. In this embodiment, the third electrode 613 serving as a gate electrode is annular. When the third electrode 613 serving as the gate electrode has a ring shape, the channel width of the insulating gate transistor can be increased. Therefore, the amount of current flowing through the insulated gate transistor can be increased. The substrate 60 1 is required to have at least a sufficiently high heat resistance to withstand subsequent heat treatment. As the substrate 601, a bismuth borate glass, an aluminoborosilicate glass, or the like can be used. When the temperature of the subsequent heat treatment is high, it is preferred to use a glass substrate having a strain point greater than or equal to 730 °C. As the glass substrate, for example, aluminum silicate glass, aluminum borosilicate glass, or bismuth borate glass -26-201138027 glass is used. In general, when the glass substrate contains a larger amount of barium oxide (BaO) than boron oxide (?2?3), a more practical glass having heat resistance can be obtained. Therefore, it is preferred to use a glass substrate in which the amount of BaO is larger than B2〇3. It is noted that a substrate (such as a ceramic substrate, a quartz substrate, or a sapphire substrate) formed of an insulator may be used instead of the glass substrate. Alternatively, crystallized glass or the like can be used. The insulating film 603 is formed using an oxide insulating film such as a hafnium oxide film or a hafnium oxynitride film or a nitride insulating film such as a tantalum nitride film, a hafnium oxynitride film, an aluminum nitride film, or an aluminum nitride oxide film. . The insulating film 603 may have a layered structure, and may have, for example, a layered structure in which one or more of the above-described nitride insulating films and one or more of the above oxide insulating films are stacked in this order from the substrate 610 side. . The first electrode 6〇5 and the second electrode 609 are formed using a metal material selected from the group consisting of Al, Cu, Cr, Ta, Ti, Mo, or W, an alloy containing any of these metal materials, or the like. Further, the first electrode 605 and the second electrode 609 may have a structure in which Cr, Ta, Ti, Mo, W are stacked on one or both of the top or bottom surface of the metal layer of Al, Cu, or the like. An annealed metal layer, or the like. Further, an aluminum material added with an element (for example, Si, Ti, Ta, W, Mo, Cr, Nd, Se, or Y) which prevents generation of hillocks or whiskers in the A1 film may be used to increase heat resistance. In addition, the first electrode 605 may have a single layer structure or a layered structure including two or more layers. For example, the first electrode 605 may have a single layer structure of a ruthenium-containing aluminum film, a two-layer structure in which a titanium film is stacked on an aluminum film, a two-layer structure in which a titanium film is stacked on a tungsten film, or a titanium film or aluminum therein. The film and the titanium film are stacked in this order in a three-layer structure of -27-201138027. Alternatively, the first electrode 605 may be formed using a film, an alloy film, or a nitride film containing aluminum and one or a plurality of elements selected from the group consisting of titanium, molybdenum, tungsten, molybdenum, chromium, niobium, and tantalum. The first electrode 605 and the second electrode 609 may be formed using a conductive metal oxide. As the conductive metal oxide, an alloy of indium oxide (in2〇3), tin oxide (Sn02), zinc oxide (ZnO), indium oxide, and tin oxide (In203-Sn02, abbreviated as ITO), indium oxide, and zinc oxide can be used. The alloy (Ιη203-Ζη0), or a metal oxide material to which ruthenium or iridium oxide is added. As the oxide semiconductor film 607, the following oxide semiconductor film can be used, for example, a four-component metal oxide film such as an In-Sn-Ga-Zn-yttrium film; such as an In-Ga-Zn-Ο film, In-Sn- Zn-Ο film, In-Al-Zn-Ο film, Sn-Ga-Zn-O film, Al-Ga-Ζη-Ο film, or three-component metal oxide film of Sn-Al-Zn-Ο film; - two-component metal oxide film of Ζη-0 film, Sn-Zn-Ο film, Al-Ζη-Ο film, Zn-Mg-Ο film, Sn-Mg-Ο film, or In-Mg-Ο film; In - ruthenium film, Sn-iridium film, or Ζη-0 film. Further, the oxide semiconductor film may contain SiO 2 . As the oxide semiconductor film 607, a film represented by InM03(Zn0)m (> gt; 〇) can be used. Here, Μ represents one or more metal elements selected from the group consisting of Ga, Al' Μη, and Co. For example, Μ may be Ga, Ga and Α1, Ga and Μη, Ga and Co, or the like. The compositional formula is an oxide semiconductor represented by InMO3(ZnO)m(m>(0) (including at least Ga as M), and is called an In-Ga-Zn-antimony oxide semiconductor, and In-Ga-Zn-0 is oxidized. The thin film of the semiconductor is called an In-Ga-Zn-antimony film. The concentration of hydrogen-28-201138027 contained in the oxide semiconductor film 607 used in this embodiment is 5xl019/cm3 or less; preferably 5xl018/cm3 or less; more preferably 5 X 1 0 17 / c m3 or less; that is, reducing hydrogen contained in the oxide semiconductor. In other words, the oxide semiconductor film 607 is highly purified to contain impurities of a main component of the non-oxide semiconductor as little as possible. Further, the carrier concentration of the oxide semiconductor film 6〇7 is 5×l014 /cm 3 or less; preferably lxl 〇 14 /cm3 or less; more preferably 5x1012 /cm3 or less; still more preferably lxl 〇 12 /cm3 or less. That is, the carrier concentration of the oxide semiconductor film is as close as possible to zero. The energy gap is 2 eV or more; preferably 2.5 eV or more; more preferably 3 eV or more. It is noted that the concentration of hydrogen in the oxide semiconductor film can be measured by SIMS. In addition, the carrier concentration can be measured by a Hall effect measurement. The oxide semiconductor film 607 preferably has a thickness of 30 nm to 3000 nm. When the thickness of the oxide semiconductor film 607 is reduced, the channel length of the insulating gate transistor can be shortened, and an insulating gate transistor having a large on-state current and a high field effect mobility can be manufactured. On the other hand, when the oxide semiconductor film 607 has a large thickness, typically a thickness of 100 nm to 300 nm, a semiconductor device for high power applications can be manufactured. The drain insulating film 611 may be a single layer structure or a stacked structure formed using a hafnium oxide film, a tantalum nitride film, a hafnium oxynitride film, a hafnium oxynitride film, and/or an aluminum oxide film. The portion of the gate insulating film 611 which is in contact with the oxide semiconductor film 607 is preferably oxygen-containing, and it is particularly preferable to use a yttrium oxide film to form the gate insulating film 611. Oxygen can be supplied to the oxide semiconductor film 607 by using a hafnium oxide film, so that the properties of the oxide semiconductor film 607 can be made satisfactory. -29 - 201138027 When a high-k material is used to form the gate insulating film 611, the gate leakage current can be reduced, and the high-k material can be, for example, citric acid (HfSiOx), and nitrogen added thereto to HfSiOxNy aluminum ( HfA10x), oxidized, or cerium oxide. Further, the gate insulating film 611 may have a layered structure including at least one of a high-k material film and a hafnium oxide film, a tantalum nitride film, a hafnium oxynitride film, a hafnium oxynitride film, and an aluminum oxide film. The gate insulating film 611 preferably has a thickness of 50 nm to 500 nm. When the thickness of the gate insulating film 611 is small, an insulating gate transistor having high field effect mobility can be manufactured; therefore, a driver circuit can be formed over the substrate on which the insulating gate transistor is formed. On the other hand, when the thickness of the gate insulating film 611 is large, the gate leakage current can be reduced. Any element selected from the group consisting of yttrium, lanthanum, molybdenum, niobium, molybdenum, and tin can be used, and any of these elements can be used. An alloy as a component, an alloy containing a combination of any of these elements, and the like form a third electrode 613 serving as a gate electrode. One or more materials selected from the group consisting of manganese, magnesium, chromium, and cerium may be used. The third electrode 613 may have a single layer structure or a layered structure having two or more layers. For example, the third electrode 613 may have a single layer structure of a tantalum-containing aluminum film, a two-layer structure in which a titanium film is stacked on an aluminum film, or a three-layer structure in which a titanium film, an aluminum film, and a titanium film are stacked in this order. . Alternatively, the third electrode 613 may be formed using a film, an alloy film, or a nitride film containing aluminum and one or a plurality of elements selected from the group consisting of titanium, group, tungsten, molybdenum, chromium, sharp, and tantalum. Next, the operation of the insulating gate transistor including the oxide semiconductor film 607 will be described with reference to Figs. 7, 8A and 8B, 9A to 9C, and 1st. -30-201138027 Fig. 7 is a cross-sectional view showing an insulating gate transistor including an oxide semiconductor film in this embodiment. An oxide semiconductor film (OS) and a source electrode (S) are stacked over the drain electrode (D). A gate insulating film (GI) is disposed over the gate electrode, the oxide semiconductor film, and the source electrode, and the respective gate electrodes (GE1) are disposed above the gate electrode. Figures 8A and 8B are energy band diagrams (schematic diagrams) of section A-A' of Figure 7. Fig. 8A shows the case where the voltage of the source is the same as that of the drain (VD = 0 V). Fig. 8B shows the case where the positive potential (VD > 0) of the voltage associated with the source is supplied to the drain. Figures 9A and 9B are energy band diagrams (schematic diagrams) of section B-B' of Fig. 7. Fig. 9A shows a case where a positive potential (+ VG) is supplied to the gate, that is, a state in which the gate (GE1) flows between the source and the drain (on state). Fig. 9B shows a case where a negative voltage (-VG) is supplied to the gate (GE1), that is, a closed state (a non-conducting state, a state in which a minority carrier does not flow). Fig. 10 is a graph showing the relationship between the vacuum level, the metal working function (Φμ), and the electron affinity (Ζ) of the oxide semiconductor film. The metal is degraded and the Fermi level is in the conduction band. On the other hand, a conventional oxide semiconductor film is generally an n-type semiconductor device film. In that case, the Fermi level (Ef) is separated from the essential Fermi level (Ei) at the center of the band gap by a distance and is located near the conduction band. It is noted that a portion of hydrogen in the oxide semiconductor film is known to serve as a donor, which is one of the factors for making the oxide semiconductor have n-type conductivity. In contrast, the oxide semiconductor film according to this embodiment is an intrinsic (i-type) oxide semiconductor obtained by the following means: for high purification - 31 - 201138027 Removal of hydrogen as an n-type impurity from the oxide semiconductor film The oxide semiconductor film contains as little impurity element as possible as a main component. In other words, the oxide semiconductor film according to this embodiment is a highly purified i-type (essential) semiconductor which is obtained by removing impurities (such as hydrogen 'water, hydroxyl, or hydride) without adding impurities as much as possible. A film or a substantially intrinsic oxide semiconductor film. Therefore, the Fermi level (Ef) can be the same as the essential Fermi level (Ε〇). In the case where the band gap (Eg) is 3.15 eV, the electron affinity (X) of the oxide semiconductor film is referred to as 4.3 eV. The work function of titanium (Ti) included in the source electrode and the drain electrode is substantially equal to the electron affinity (Z) of the oxide semiconductor. In this case, the electron Kentucker barrier is not formed in the metal and oxide. The interface between the semiconductor films. That is, in the case where the work function (φΜ) of the metal is equal to the electron affinity (X) of the oxide semiconductor film and the metal and the oxide semiconductor film are in contact with each other, the image shown in Fig. 8 is obtained. The energy band diagram (schematic diagram). In the eighth diagram, the black dot (·) represents electrons. When a positive potential is supplied to the drain, electrons cross the energy barrier (h) and are implanted into the oxide semiconductor film, and The pole flow. In this case, the height of the energy barrier (h) varies with the gate voltage and the drain voltage. When the positive drain voltage is supplied, the height of the energy barrier is smaller than the energy barrier without the supply voltage in Figure 8A. The height, that is, is less than 1/2 of the band gap (Eg). At this time, as shown in Fig. 9A, electrons move along the lowest portion of the oxide semiconductor film side at the interface between the gate insulating film and the highly purified oxide semiconductor film, which is energy stable. In the case of supplying a negative potential to the gate electrode (GE1), there is no hole as a minority carrier in the real-32-201138027, so the current 値 is substantially close to zero. For example, even with a channel width of 1χ104 μηι In an insulated gate transistor with W and 3μπΐ channel length, the current at room temperature can be lx 10'13 Α or less, which is extremely low, and the secondary threshold swing (S値) can be 0.1. V/dec (the gate insulating layer p having a thickness of 1 〇〇 nm is highly purified as described above to contain impurities (such as hydrogen, water, hydroxyl groups, or hydrides) which are not essential components as much as possible. In order to operate the insulated gate transistor in a desirable manner. In particular, the off current can be reduced. In a laterally insulated gate transistor in which a channel is formed substantially parallel to the substrate, a source and a drain are required in addition to the channel. In view of this The area of the substrate occupied by the laterally insulated gate transistor is increased, which prevents microfabrication. Conversely, in the vertical insulated gate transistor, the source, the channel, and the germanium are extremely stacked, so that the surface of the substrate can be reduced. The area can be minimized. In addition, the channel length of the vertical insulating gate transistor can be controlled by the thickness of the oxide semiconductor film; therefore, the insulating gate transistor can be reduced by reducing the oxide semiconductor film. The thickness of 607 has a small channel length. The series resistance of the source, the channel, and the drain can be reduced by reducing the length of the channel, thereby increasing the on-state current and field-effect mobility of the insulated gate transistor. In addition, the gate electrode of the insulating gate transistor in this embodiment is annular and can increase the channel width, so that the on-state current can be increased. Also, the insulating-33-201138027 gate transistor including a highly purified oxide semiconductor film having a reduced hydrogen concentration has an extremely low off-state current and is thus set in an insulating state in which the insulating gate transistor is turned off. There is almost no current flowing. Accordingly, even when the thickness of the oxide semiconductor film is reduced to reduce the channel length of the vertical insulating gate transistor, the insulating gate transistor has almost no off-state current in the non-conducting state. By using a highly purified oxide semiconductor film with a reduced hydrogen concentration, an insulating gate transistor can be fabricated which operates at high speed, can flow a large amount of current when the transistor is turned on, and has almost no flowing current when the transistor is turned off. . It is to be noted that those described with reference to the figures in this embodiment can be freely combined with or substituted for those described in the other embodiments. (Embodiment 4) In this embodiment, an application of a semiconductor device which is explained in any of the above embodiments and functions as a thyristor will be explained. The semiconductor device described in the above embodiments may be, for example, a battery power conditioner in an electronic device (such as a display capable of displaying an image such as a computer); and a power conditioner provided for an induction cooker or a carrier (such as a bicycle) It is driven by the power of a fixed power source. It is noted that the power conditioner means a device that supplies current to the load with a predetermined trigger signal. An application example of a power conditioner including a semiconductor device will be described with reference to Figs. 11A to 11C. Fig. 11A is a view showing an induction cooker 1 0 0 as an example of a power conditioner including a semiconductor device. The induction cooker 1000 heats the cooking device and the like by using an electromagnetic induction generated by a current flowing through the coil unit 1001. Further, the induction cooker 1 000 includes a battery 1 002 and a power conditioner 1 003 for supplying a current flowing through the coil unit 1 00 1 , and a solar battery 1 004 for charging the battery 1 〇〇 2 . It is noted that Fig. 11 shows the solar battery 1 004 as a mechanism for charging the battery 1002; alternatively, the battery 1 002 can be charged by another mechanism. Since the power conditioner 100 including the semiconductor device functioning as the thyristor includes an insulating gate transistor (which includes an oxide semiconductor layer), the off-state current can be reduced, and power consumption can be realized when the induction cooker 1 does not perform heating. Reduction. Fig. 11 is a diagram showing an electric bicycle 1 0 1 0 as an application example of a power conditioner including a semiconductor device. The electric bicycle 1 0 1 0 obtains electric power when current flows through the motor unit 1011. Further, the electric bicycle 1010 includes a battery 1 0 1 2 and a power conditioner 1013 for supplying a current flowing through the motor unit 1 ο 1 1 . It is noted that the mechanism for charging the battery 1012 is not shown in Fig. 11; the battery 1012 can be charged by an additionally provided generator or the like. Since the power conditioner 1013 including the semiconductor device functioning as the thyristor includes an insulating gate transistor (which includes an oxide semiconductor layer), the off-state current can be reduced, and power consumption can be realized when the electric bicycle 1 0 10 does not operate. The amount is reduced. Note that a pedal is shown in Figure 1; however, it is not necessary to set the pedal. Fig. 11C is a diagram showing an electric vehicle 1 020 as an application example of a power conditioner including a semiconductor device. The electric vehicle 1 020 receives electric power when current flows through the motor unit 1021. In addition, the electric vehicle 1 020 includes a battery 1022 and a power conditioner 1023 for supplying a current flowing through the motor unit 1021 of -35-201138027. It is noted that the mechanism for charging the battery 1 022 is not shown in Fig. 11C; the battery 1 022 can be charged by an additional generator or the like. Since the power conditioner 1 023 including the semiconductor device functioning as the thyristor includes an insulating gate transistor (which includes an oxide semiconductor layer), the off-state current can be reduced, and power consumption can be realized when the electric vehicle 1 020 is not operating. Reduction. It is to be noted that those described with reference to the figures in this embodiment can be freely combined with or substituted for those described in the other embodiments. The application is based on Japanese Patent Application No. 2009-259900, filed on Jan. BRIEF DESCRIPTION OF THE DRAWINGS In the drawings: FIG. 1 illustrates a semiconductor device according to an embodiment of the present invention; FIGS. 2A and 2B each illustrate a semiconductor device according to an embodiment of the present invention; FIGS. 3A to 3C The semiconductor device according to the embodiment of the present invention: FIGS. 4A to 4C illustrate a semiconductor device according to an embodiment of the present invention; FIGS. 5A and 5B each illustrate a semiconductor device according to an embodiment of the present invention. 6A and 6B are diagrams showing a semiconductor device not according to the present invention - 36 - 201138027; FIG. 7 is a view showing a semiconductor device according to an embodiment of the present invention; and FIGS. 8A and 8B are diagrams according to the present invention; a semiconductor device according to an embodiment; FIGS. 9A and 9B are diagrams showing a semiconductor device according to an embodiment of the present invention; and FIG. 10 is a view showing a semiconductor device according to an embodiment of the present invention; FIGS. 11A to 11C are diagrams An application example of a semiconductor device; and FIG. 2 depicts a thyristor. [Main component symbol description] 1 〇1: Insulated gate transistor 102: Insulated gate transistor 1〇3: Insulated gate transistor 1〇4: Insulated gate transistor 105: Insulated gate transistor 106: Insulation Gate transistor 107: Insulated gate transistor 108: Insulated gate transistor 109: Insulated gate transistor 1 10: Capacitor 1 11 : Resistor 1 1 2: Wiring 1 1 3 : Wiring -37- 201138027 1 1 4: wiring 1 1 5 : memory circuit 1 1 6 : inverter circuit 1 17 : load 200 : snubber circuit 201 : snubber circuit 2 1 0 : insulated gate transistor 2 1 1 : insulated gate transistor 2 1 2 : Insulated gate transistor 2 1 3 : Insulated gate transistor 220 : Insulated gate transistor 221 : Insulated gate transistor 222 : Insulated gate transistor 223 : Insulated gate transistor 6 0 1 : Substrate 603: insulating film 605: electrode 607: oxide semiconductor film 609: electrode 6 1 1 : gate insulating film 6 1 3 : electrode 6 1 7 : insulating film 6 2 5 : wiring 6 2 9 : wiring 201138027 63 1: 645 : 1 000 : 1001 : 1 002: 1 003 : 1 004 : 1010·· 10 11: 1012 : 1013: 1 020 : 1021 : 1 022: 1 023 1100: 110 1: 1102: 1103: 1104: Wiring insulated gate transistor induction cooker coil unit battery power regulator solar battery electric bicycle motor unit battery power regulator electric vehicle motor unit battery power regulator thyristor npn transistor ρηρ transistor Wiring wiring-39

Claims (1)

201138027 VII. Patent application scope: !. A semiconductor device comprising: first to ninth insulating gate transistors; - a capacitor; a first high power supply potential supplied to one of the first wirings; and a second high power supply potential Supplying to one of the second wirings; a first low power supply potential supplied to one of the third wirings; and a second low power supply potential supplied to one of the fourth wirings, wherein the first insulating gate transistor a gate is electrically connected to a terminal, a first terminal of the first insulating gate transistor is electrically connected to the third wiring, and a second terminal of the first insulating gate transistor is electrically connected to the second insulating gate a first terminal of the transistor, wherein a gate of the second insulating gate transistor is electrically connected to one of the first terminal of the insulating gate transistor and the first terminal of the eighth insulating gate transistor; One second end of the second insulating gate transistor is connected to one of the first terminal of the third insulating gate transistor, the first terminal of the fourth gate transistor, and the sixth insulating gate Crystal gate, where One of the three insulated gate transistors is electrically connected to the wiring 'and one of the second terminals of the third insulated gate transistor is electrically connected to the second wiring, wherein one of the gates of the fourth insulating gate transistor Electrically connecting to one of the first terminals of the insulating gate transistor, the first terminal of the sixth insulating gate transistor, the first electrode of the capacitor, and the electrical input of the eighth insulating gate to the seventh body One of the insulators is connected to the first body of the fifth body - 40-201138027 one gate of the crystal, and one gate of the ninth insulating gate transistor; and one of the fourth insulating gate transistors The terminal is electrically connected to the third wiring, wherein one of the gates of the fifth insulating gate transistor is electrically connected to the first wiring, and one of the second terminals of the fifth insulating gate transistor is electrically connected to the second wiring The second terminal of the sixth insulating gate transistor is electrically connected to the third wiring, wherein one of the gates of the seventh insulating gate transistor is electrically connected to the first wiring, and the seventh insulating gate One of the pole electrodes Connecting to the second wiring, wherein a second terminal of the eighth insulating gate transistor is electrically connected to the third wiring, wherein a first terminal of the ninth insulating gate transistor is electrically connected to an output terminal, And a second terminal of the ninth insulating gate transistor is electrically connected to the fourth wiring, and wherein a second electrode of the capacitor is electrically connected to the third wiring. 2. The semiconductor device as claimed in claim 1, further comprising a resistor, wherein a first terminal of the resistor is electrically connected to the gate of the first insulating gate transistor, and the resistor One of the second terminals is electrically connected to the third wiring. 3. The semiconductor device of claim 1, wherein the first high power supply potential and the second high power supply potential are the same potential. -41 - 201138027 4. A semiconductor device comprising: first to ninth insulating gate transistors; - a capacitor; a first high power supply potential supplied to one of the first wirings; a second high power supply potential supplied to a second wiring: a first low power supply potential supplied to one of the third wirings; and - a second low power supply potential supplied to one of the fourth wirings, wherein the first insulating gate transistor is one of the gates The pole is electrically connected to an input terminal, one first terminal of the first insulating gate transistor is electrically connected to the third wiring, and one of the second terminals of the first insulating gate transistor is electrically connected to the second insulation a first terminal of the gate transistor, wherein one of the gates of the second insulating gate transistor is electrically connected to one of the first terminal of the seventh insulating gate transistor and the eighth insulating gate transistor - a first terminal; and a second terminal of the second insulating gate transistor electrically connected to one of the first terminal of the third insulating gate transistor, the first terminal of the fourth insulating gate transistor, and The sixth insulated gate transistor a gate of the third insulating gate transistor electrically connected to the first wiring, and a second terminal of the third insulating gate transistor is electrically connected to the second wiring, wherein the first One of the four insulated gate transistors is electrically connected to one of the first terminals of the fifth insulating gate transistor, the first terminal of the sixth insulating gate transistor, the first electrode of the capacitor, and the first electrode a gate of an eighth insulating gate transistor and a gate of the ninth insulating gate transistor; and -42-201138027, a second terminal of the fourth insulating gate transistor is electrically connected to the third Wiring> wherein one of the gates of the fifth insulating gate transistor is electrically connected to the first wiring, and one of the second terminals of the fifth insulating gate transistor is electrically connected to the second wiring, wherein the sixth a second terminal of the insulating gate transistor is electrically connected to the third wiring, wherein one of the gates of the seventh insulating gate transistor is electrically connected to the first wiring, and one of the seventh insulating gate transistors The second terminal is electrically connected to the second wiring, Wherein a second terminal of the eighth insulating gate transistor is electrically connected to the third wiring, wherein a first terminal of the ninth insulating gate transistor is electrically connected to an output terminal, and the ninth insulating gate a second terminal of the transistor is electrically connected to the fourth wiring, wherein a second electrode of the capacitor is electrically connected to the third wiring, and wherein the first to ninth insulating gate transistors each have an oxide A semiconductor layer formed by a semiconductor. 5. The semiconductor device as claimed in claim 4, further comprising a resistor, wherein a first terminal of the resistor is electrically connected to the gate of the first insulating gate transistor, and the resistor One of the second terminals is electrically connected to the third wiring. The semiconductor device according to claim 4, wherein the secondary ion mass spectrometry detects a hydrogen concentration in the oxide semiconductor: 1 016 /cm 3 or less. 7. The semiconductor device according to claim 4, wherein the oxide semiconductor has a carrier concentration of less than lxl 〇 14 /cm 3 . 8. The semiconductor device of claim 4, wherein the first high power supply potential and the second high power supply potential are the same potential. A semiconductor device comprising: first to ninth insulating gate transistors; a capacitor; a buffer circuit; a first high power supply potential supplied to one of the first wirings; and a second high power supply potential supplied to a second wiring; a first low power supply potential supplied to one of the third wirings; and a second low power supply potential supplied to one of the fourth wirings, wherein the first insulating gate transistor is one of the gates The pole is electrically connected to a terminal, the first terminal of the first insulating gate transistor is electrically connected to the three wiring, and the second terminal of the first insulating gate transistor is electrically connected to the second insulating gate transistor a first terminal, wherein one of the gates of the second insulating gate transistor is electrically connected to one of the first terminals of the insulating gate transistor and the first terminal of the eighth insulating gated transistor: and the first a second end of the second insulating gate transistor is connected to one of the first terminal of the third insulating gate transistor, the first terminal of the fourth gate transistor, and the sixth insulating gate transistor The input by the special 1 X One of the electrical insulation of the seventh body of the seventh body is connected to a gate of -44-201138027, wherein one of the gates of the third insulated gate transistor is electrically connected to the first wiring, and one of the third insulated gate transistors The second terminal is electrically connected to the second wiring, wherein one of the gates of the fourth insulating gate transistor is electrically connected to one of the first terminals of the fifth insulating gate transistor, and the sixth insulating gate transistor a first terminal, a first electrode of the capacitor, a gate of the eighth insulating gate transistor, and a gate of the ninth insulating gate transistor: and the fourth insulating gate transistor a second terminal electrically connected to the third wiring> wherein one of the gates of the fifth insulating gate transistor is electrically connected to the first wiring, and one of the second terminals of the fifth insulating gate transistor is electrically connected To the second wiring, wherein a second terminal of the sixth insulating gate transistor is electrically connected to the third wiring, wherein one of the gates of the seventh insulating gate transistor is electrically connected to the first wiring, and One of the seventh insulated gate transistors The second terminal is electrically connected to the second wiring, wherein a second terminal of the eighth insulating gate transistor is electrically connected to the third wiring, wherein the first terminal of the ninth insulating gate transistor is electrically connected to the first terminal An output terminal, and a second terminal of the ninth insulating gate transistor is electrically connected to the fourth wiring, wherein a second electrode of the capacitor is electrically connected to the third wiring '45-201138027, wherein the first to The ninth insulating gate transistors each have a semiconductor layer formed using an oxide semiconductor, and wherein the gate of the fourth insulating gate transistor, the first terminal of the fifth insulating gate transistor a potential of the first terminal of the sixth insulating gate transistor, the first electrode of the capacitor, and one of the gates of the eighth insulating gate transistor electrically connected via the buffer circuit The gate is supplied to the ninth insulating gate transistor. The semiconductor device of claim 9, further comprising a resistor, wherein a first terminal of the resistor is electrically connected to the gate of the first insulating gate transistor, and the resistor One of the second terminals is electrically connected to the third wiring. 11. The semiconductor device according to claim 9, wherein the concentration of hydrogen in the oxide semiconductor detected by secondary ion mass spectrometry is lxlO16 /cm3 or less. The semiconductor device according to claim 9, wherein the oxide semiconductor has a carrier concentration of less than lxl 014 /cm3. The semiconductor device of claim 9, wherein the first high power supply potential and the second high power supply potential are the same potential. 1. The semiconductor device according to claim 9, wherein the buffer circuit comprises tenth to thirteenth insulating gate transistors> wherein a gate of the tenth insulating gate transistor is electrically connected To the first wiring, a first terminal of the tenth insulating gate transistor is electrically connected to the first -46-201138027 two wiring, and a second terminal of the tenth insulating gate transistor is electrically connected to the first a first terminal of the eleventh insulating gate transistor and a gate of the thirteenth insulating gate transistor, wherein a gate of the eleventh insulating gate transistor is electrically connected to the fourth insulating gate The gate of the transistor, the first terminal of the fifth insulating gate transistor, the first terminal of the sixth insulating gate transistor, the first electrode of the capacitor, and the eighth insulating gate a gate of the transistor; and a second terminal of the eleventh insulating gate transistor electrically connected to the third wiring, wherein a gate of the twelfth insulating gate transistor is electrically connected to the first Wiring, a first of the twelfth insulating gate transistor a sub-electrode is connected to the second wiring, and a second terminal of the twelfth insulating gate transistor is electrically connected to a first terminal of the thirteenth insulating gate transistor and the ninth insulating gate transistor The gate, and a second terminal of the thirteenth insulating gate transistor are electrically connected to the third wiring. 15. The semiconductor device according to claim 9, wherein the buffer circuit comprises tenth to thirteenth insulating gate transistors> wherein a gate of the tenth insulating gate transistor is electrically connected to The gate of the second insulating gate transistor, the first terminal of the seventh insulating gate transistor, and the first terminal of the eighth insulating gate transistor; the tenth insulating gate transistor a first terminal is electrically connected to the second wiring, and a second terminal of the tenth insulating gate transistor is electrically connected to a first terminal of the eleventh absolute-47-201138027 edge gate transistor and a gate of the thirteenth insulating gate transistor, wherein a gate of the eleventh insulating gate transistor is electrically connected to the gate of the fourth insulating gate transistor, the fifth insulating gate The first terminal of the transistor, the first terminal of the sixth insulating gate transistor, the first electrode of the capacitor, the gate of the eighth insulating gate transistor, and the twelfth insulating gate The gate of the polar crystal; and the eleventh insulating gate a second terminal electrically connected to the third wiring, wherein a first terminal of the twelfth insulating gate transistor is electrically connected to the second wiring 'and a second of the twelfth insulating gate transistor The terminal is electrically connected to a first terminal of the twelfth insulated transistor and the gate of the ninth insulating gate transistor, and wherein a second terminal of the thirteenth insulating gate transistor is electrically connected To the third wiring. -48 -