JP2003110110A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which a short channel is by reducing a gate length in order to improve practical field mobility, and to provide a method of manufacturing the semiconductor device at a low cost. SOLUTION: This semiconductor device has an electrode layer 1, a semiconductor layer 2, and a second electrode layer 3, which are successively layered in this order, and a first electrical insulation layer 4 and a third electrode layer 5, which are formed vertically in this order so as to be brought into contact with one-side sidewalls of the layered layers 1, 2, and 3. The first electrode layer 1, the second electrode layer 3, and the third electrode layer 5 are, for instance, a source electrode layer, a drain electrode layer, and a gate electrode layer. The first electrical insulation layer 4 is, for instance, a gate electrical insulation layer. The semiconductor device is, for instance, a vertical field effect transistor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more specifically, a source electrode layer,
The present invention relates to a sheet display in which a semiconductor layer and a drain electrode layer are sequentially stacked to control a current value by an electric signal, a vertical field effect transistor used as a drive arithmetic circuit of a sheet computer device, and a manufacturing method thereof.

[0002]

2. Description of the Related Art A thin film field effect transistor using an inorganic material for a semiconductor layer (active layer) is known in the art (DB Thomasson & al., IEEE El. Dev. Lett., Vol.
18, p. 117; March 1997. ), Already manufactured as an industrial product. FIG. 7 shows a thin film field effect transistor using a conventional inorganic material. As shown in FIG. 7, the conventional thin film field effect transistor using an inorganic material is arranged laterally with respect to the substrate 101. The source electrode layer 105 and the drain electrode layer 106 are provided so as to be separated by the electrically neutral inorganic semiconductor layer (channel layer region) 104. The gate electrode 102 is
The gate electrical insulating layer 103 is electrically separated from the inorganic semiconductor layer 104 and is provided over the substrate 101. As a semiconductor material forming the inorganic semiconductor layer 104, an inorganic material such as an inorganic amorphous material (hydrogenated amorphous Si) or an inorganic polycrystalline material is used.

A thin film field effect transistor using an organic material for a semiconductor layer is also known in the art (A. Dod).
abalapur & al., Appl. Phys. Lett., Vol. 69, pp. 42
See 27-29, December 1996. ). FIG. 8 shows a thin film field effect transistor using a conventional organic material. As shown in FIG. 8, this conventional thin film field effect transistor using an organic material is also laterally arranged with respect to the substrate 111, similarly to the thin film field effect transistor using an inorganic material. The source electrode layer 115 and the drain electrode layer 116 are provided separated by an electrically neutral organic semiconductor layer (channel layer region) 114. The gate electrode 112 is disposed on the substrate 111, being electrically separated from the organic semiconductor layer 114 by the gate electric insulation layer 113. As a semiconductor material forming the organic semiconductor layer 114, an organic material such as a π-electron conjugated polymer compound or an aromatic compound has been used.

[0004]

In these thin film field effect transistors, the electric field applied from the gate electrode layer through the gate insulating layer acts on the semiconductor layer (channel portion), so that the source electrode layer and the drain electrode layer are formed. Transistor operation is realized by controlling the current flowing between the layers. A thin-film field-effect transistor using an organic material for a semiconductor layer can manufacture an element without using a vacuum as compared with a thin-film field-effect transistor using an inorganic material such as hydrogenated amorphous Si for a semiconductor layer. There is an advantage that the manufacturing cost can be reduced due to the fact that an element having a uniform area can be manufactured, the electrode wiring can be formed without forming the source / drain regions, and the manufacturing method is simple. However, the thin film field effect transistor using an organic material for the semiconductor layer has a higher carrier mobility (transistor performance) than the thin film field effect transistor using an inorganic material such as hydrogenated amorphous Si for the semiconductor layer. Is low, (b) cannot pass a large current, and (c) cannot operate at high speed.

Conventionally, techniques developed to solve such problems include, for example, a technique for controlling the conjugated state of a π-conjugated polymer, a technique for using molecular electric conduction anisotropy,
There have been technologies related to organic semiconductor materials such as, and technology for achieving high crystallinity when an organic polymer film is obtained by a vapor deposition method.

In the conventional thin film field effect transistor using an inorganic material shown in FIG. 7, a voltage is applied between a source electrode layer and a drain electrode layer, and a voltage is applied to the gate electrode to A current is caused to flow between the source electrode layer and the drain electrode by inducing a channel at the interface between the electrical insulating layer and the semiconductor layer. The current (Id) between the source electrode layer and the drain electrode layer at this time is
In general, it can be expressed by the following formula.

[0007]

[Equation 1] However, C _ox , μ, V _g and V _th in the mathematical formula are as follows. C _ox : Gate capacitance (F / m ² ) μ: Field effect mobility (cm ² / Vs) V _g : Gate voltage (V) V _th : Threshold voltage (V)

In order to improve the transistor performance within a limited transistor size (W: gate width, L: gate length), it is necessary to realize a higher Id value. From the equation (1), as factors other than W and L for improving Id, Co
It is possible that x and μ increase. Conventionally, a material having a high relative dielectric constant for improving effective Cox (Japanese Patent Laid-Open No. 10-270712) and a material for improving μ by developing a π-conjugated polymer material (Japanese Patent Laid-Open No. 10-190
No. 001) has been reported, but particularly in the formula (1), decreasing L is a good idea for obtaining a high Id. Initially 10μ in Si technology
At present, the gate width of m-width is being reduced to about 0.1 μm. This is Id without the development of Cox and μ.
This will result in a 100-fold increase in value. This trend of short gate length has hitherto mainly depended on the improvement of the lithography processing limit. In the thin film field effect transistor using the conventional organic material shown in FIG. 8, a gate length of 10 to 5 μm is exclusively made as a prototype, but in the lithography processing technology, the gate length is further shortened. There was a problem that it was difficult to do.

The advantage of using an organic semiconductor for manufacturing a transistor is a low manufacturing cost. However, it is an advantage of an organic transistor to use a lithography processing technology developed by Si technology for manufacturing a transistor using an organic semiconductor. It is considered unlikely that this technology will be actively adopted, as it is contrary to the concept of low manufacturing cost. It has been proposed to manufacture an organic transistor by using a method called soft lithography. However, even if this method is used, it is 10 to 5 μm as described above.
It is difficult to shorten the gate length because it is currently possible to manufacture only those with the gate length.

The present invention aims to solve such problems. That is, an object of the present invention is to provide a semiconductor device in which the effective electric field mobility is improved by shortening the gate length and shortening the channel, and a manufacturing method thereof at low cost.

[0011]

Means for Solving the Problems The present inventor has sought to improve the effective field mobility of the field effect transistor by devising the structure of the field effect transistor, and has searched for the structure of the field effect transistor. In a semiconductor device in which the electrode layer, the semiconductor layer, and the second electrode layer are sequentially stacked, the first electrical insulating layer and the third electrode which are vertically provided so as to be in contact with one sidewall of those layers. When the layers are sequentially provided, the gate length can be shortened to shorten the channel, and it has been found that the effective electric field mobility can be improved, and the present invention has been completed.

That is, according to the invention described in claim 1, in order to achieve the above object, in a semiconductor device in which a first electrode layer, a semiconductor layer and a second electrode layer are sequentially laminated, those layers are A semiconductor device having a first electric insulating layer and a third electrode layer which are vertically provided so as to be in contact with one side wall and which are sequentially provided.

The invention described in claim 2 is the same as the invention described in claim 1, wherein a buffer is provided between the first electrode layer and the semiconductor layer and / or between the semiconductor layer and the second electrode layer. The semiconductor device according to claim 1, further comprising a layer.

According to the invention described in claim 3, in the invention described in claim 1 or 2, so as to be in contact with the other side wall of the first electrode layer, the semiconductor layer and the second electrode layer,
A second electric insulating layer provided upright in the vertical direction, and a third electric insulating layer provided in the vertical direction so as to be in contact with the outer side wall of the third electrode layer. is there.

The invention described in claim 4 is the invention according to claim 1
In the invention described in any one of 3 above, the first electrode layer, the second electrode layer, and the third electrode layer are a source electrode layer, a drain electrode layer, and a gate electrode layer, respectively. To do.

The invention described in claim 5 is the invention defined in claims 1 to 1.
In the invention described in any one of 4 above, the first electric insulating layer is a gate electric insulating layer.

The invention described in claim 6 is from claim 1
In the invention described in any one of 5 above, the second electric insulation layer and the third electric insulation layer are element isolation electric insulation layers.

The invention described in claim 7 is from claim 1
In the invention described in any of 6, the semiconductor layer is an acene molecular material selected from the group consisting of naphthalene, anthracene, tetracene, pentacene, hexacene and derivatives thereof, a phthalocyanine compound,
Pigments and derivatives thereof selected from the group consisting of azo compounds and perylene compounds, hydrazone compounds, triphenylmethane compounds, diphenylmethane compounds, stilbene compounds, aryl vinyl compounds, pyrazoline compounds, triphenylamine compounds, phenylene derivatives and triarylamines Low molecular weight compounds selected from the group consisting of compounds and their derivatives, or poly-N
A polymer compound selected from the group consisting of: vinylcarbazole, halogenated poly-N-vinylcarbazole, polyvinylpyrene, polyvinylanthracene, polythiophene derivative, thiophene oligomer derivative, pyreneformaldehyde resin, polyacetylene derivative, and ethylcarbazoleformaldehyde resin, It is characterized in that it is composed of an organic semiconductor material.

The invention described in claim 8 is from claim 1
In the invention described in any one of 6 above, the semiconductor layer is composed of an inorganic semiconductor material made of a metal oxide such as zinc oxide or tin oxide, or a composite oxide such as strontium titanate. To do.

The invention described in claim 9 is from claim 1
In the invention described in any one of 8 above, the first electric insulating layer, the second electric insulating layer and the third electric insulating layer each contain a hydroxyl group such as polyvinyl alcohol, polyvinyl butyral, a phenol resin or a novolac resin. It is characterized by comprising at least one kind of material selected from the group consisting of an electrically insulating polymer having, and an electrically insulating polymer having a cyano group such as polyacrylonitrile.

The invention described in claim 10 is claim 1
In the invention described in any one of 1 to 9, the first electrode layer, the second electrode layer, and the third electrode layer are made of chromium (C
r), thallium (Ta), titanium (Ti), copper (C
u), aluminum (Al), molybdenum (Mo), tungsten (W), nickel (Ni), gold (Au), palladium (Pd), platinum (Pt), silver (Ag), tin (S).
n), a conductive polyaniline, a conductive polypyrrole, a conductive polythiazyl, and a conductive polymer, and at least one material selected from the group consisting of the following:

The invention described in claim 11 is the same as claim 1.
In the invention described in any one of 10 to 10, the semiconductor device is formed on an insulating substrate.

The invention described in claim 12 is the same as claim 1.
In the invention described in any one of 1 to 11, the semiconductor device is a vertical field effect transistor.

The invention described in claim 13 is: (a) a step of forming a first electrode layer on a substrate; and (b) a first standing upright in contact with the right side wall of the source electrode layer. A first electric insulating layer, a second electric insulating layer which is erected so as to be in contact with the left side wall of the first electrode layer, and a width of the first electric insulating layer from the right side wall of the first electrode layer; Forming a third electric insulating layer standing vertically in a vertical direction, and (c) a semiconductor layer on the first electrode layer between the first electric insulating layer and the second electric insulating layer. Forming a third electrode layer on the substrate between the first electric insulating layer and the third electric insulating layer, and (e) forming the first electric insulating layer. And a step of forming a second electrode layer on the semiconductor layer between the second electrically insulating layer and the second electrically insulating layer.

The invention described in claim 14 is claim 1
In the invention described in 3, the photoresist is spin-coated in the step (b) to form a photoresist film, and then the first electrical insulation layer, the second electrical insulation layer and the third electrical insulation layer are formed.
The first electric insulating layer, the second electric insulating layer, and the third electric insulating layer are formed by exposing and developing to the width of the electric insulating layer.

The invention described in claim 15 is the same as claim 1.
In the invention described in 3 or 14, in the step (c), the solution of the polymer organic semiconductor material is subjected to an inkjet method,
A film is formed by means of a letterpress printing method, an intaglio printing method, an offset printing method, a screen printing method or the like, or a low molecular weight organic semiconductor material is formed by means of a vacuum vapor deposition method, a molecular beam vapor deposition method or the like, and a semiconductor It is characterized by forming a layer.

The invention described in claim 16 is the same as claim 1.
In the invention described in any one of 3 to 15,
In the steps (a), (d) and (e), the first electrode layer, the second electrode layer and the third electrode layer are printed with a solution of a polymer conductive material, an inkjet method. Method, letterpress printing method, intaglio printing method, offset printing method, screen printing method or the like, or metal deposition by means such as vacuum deposition method, ion plating method, sputtering method or plating method. Then, the first electrode layer, the second electrode layer, and the third electrode layer are formed.

The invention described in claim 17 is the same as claim 1.
In the invention described in any one of 3 to 16, the first electrode layer, the second electrode layer, and the third electrode layer are a source electrode layer, a drain electrode layer, and a gate electrode layer, respectively. It is a feature.

The invention described in claim 18 is claim 1
The invention described in any one of 3 to 17 is characterized in that the first electric insulating layer is a gate electric insulating layer.

The invention described in claim 19 is the same as claim 1.
The invention described in any one of 3 to 18 is characterized in that the second electrical insulation layer and the third electrical insulation layer are element isolation electrical insulation layers.

The invention described in claim 20 is the same as claim 1.
The invention described in any one of 3 to 19 is characterized in that the semiconductor device is a vertical field effect transistor.

According to a twenty-first aspect of the present invention, in the manufacture of a semiconductor device, a solution of an organic semiconductor material is applied between a pair of electrically insulating layers provided vertically on a substrate to form an organic semiconductor layer and an organic semiconductor layer. And / or an inorganic semiconductor and / or a conductive layer is formed, which is a method for manufacturing a semiconductor device.

[0033]

FIG. 1 is a sectional view of a semiconductor device showing an embodiment of the present invention. FIG. 2 is a cross-sectional view of a semiconductor device showing another embodiment of the present invention. Figure 3
FIG. 7 is a sectional view of a semiconductor device showing another embodiment of the present invention. FIG. 4 is an explanatory diagram for explaining electrical connection and operation for driving the semiconductor device of the present invention.
FIG. 5 is an explanatory diagram for explaining the manufacturing process of the semiconductor device showing the embodiment of the present invention. FIG. 6 is an explanatory diagram for explaining a process of microcontact printing.

As shown in FIG. 1, the semiconductor device (vertical field effect transistor) of the present invention comprises a first electrode layer 1 (source electrode), a semiconductor layer 2 (semiconductor region) and a second electrode layer 1 (source electrode).
In the semiconductor device in which the electrode layers 3 (drain electrodes) are sequentially stacked, the first electrical insulating layer 4 (gate electrical insulating film) and the 3 sequentially has the electrode layer 5 (gate electrode).

As shown in FIGS. 1 and 4, according to the semiconductor device of the present invention, a current (Id) is caused to flow in a direction perpendicular to the surface of the substrate 11 and then outside one of the active regions 10. Since the structure is such that an electric field is applied from the provided third electrode layer to the semiconductor layer 2, that is, the semiconductor region through the first electric insulating layer 4, the film thickness of the semiconductor layer 2 (the above formula (1 )
(Corresponding to the gate length L in FIG. 1) can be made even thinner, and therefore, the gate length L can be shortened and a dramatically short channel length can be structurally realized without using photolithography processing. , Transistor performance,
That is, the effective electric field mobility can be improved. Moreover, since the structure of the semiconductor device is simple, the manufacturing process can be simplified, and therefore, the manufacturing cost of the semiconductor device can be reduced.

As shown in FIG. 2, the semiconductor device of the present invention is preferably arranged between the first electrode layer 1 and the semiconductor layer 2 and / or the semiconductor layer 2 and the second electrode layer 3. It is possible to have buffer layers 8 and 9 between them. When the buffer layers 8 and 9 are provided between the first electrode layer 1 and the semiconductor layer 2 and / or between the semiconductor layer 2 and the second electrode layer 3, the first electrode layer 1 and the second electrode layer 3 are provided. Good electrical contact can be obtained between the second electrode layer 3 and the semiconductor layer 2. The buffer layers 8 and 9 are formed of, for example, a conductive polymer material that can be formed by a printing method, an ink jet method, or the like, and, in addition to polyaniline, polydioxythiophene, or the like, well-known charges for organic EL materials. The transfer material may be formed by a vacuum evaporation method. Further, as another buffer layer function, a function of reducing the transistor off current may be retained. There are two kinds of electrons and holes in the conduction carriers that contribute to electric conduction, and a material having an electron transporting function is used as the buffer layer of the hole transporting semiconductor material, and a buffer film of the electron transporting semiconductor material is used. As the material, a material having a hole transport function may be used. In the device thus constructed, the carriers are conducted over a slight potential barrier formed at the interface between the semiconductor layer and the buffer layer, so that the effect is particularly effective in reducing the transistor off current.

In the semiconductor device of the present invention, the first electrode layer 1, the semiconductor layer 2 and the second electrode layer 3 are vertically aligned so as to be in contact with the other side wall, that is, the other side wall of the active region 10. The second electrically insulating layer 6 provided upright and the third electrical insulating layer
The third electrically insulating layer 7 may be provided vertically so as to contact the outer side wall of the electrode layer 5. Such a second electric insulating layer 6 and a third electric insulating layer 7 are effective for element isolation, and when the semiconductor device of the present invention is manufactured, the first electrode layer 1, The semiconductor layer 2 and the second electrode layer 3 effectively act as a frame for sequentially forming a film in the vertical direction and as a frame for forming the third electrode layer 5.

The semiconductor layer is preferably composed of an acene molecular material selected from the group consisting of naphthalene, anthracene, tetracene, pentacene, hexacene and derivatives thereof, a phthalocyanine compound, an azo compound and a perylene compound. A low molecular weight compound selected from the group consisting of selected pigments and their derivatives, hydrazone compounds, triphenylmethane compounds, diphenylmethane compounds, stilbene compounds, aryl vinyl compounds, pyrazoline compounds, triphenylamine compounds, phenylene derivatives and triarylamine compounds. And their derivatives, or poly-N-vinylcarbazole, halogenated poly-N-vinylcarbazole, polyvinylpyrene, polyvinylanthracene, polythiophene derivatives, thiophenol Mer derivatives, pyrene-formaldehyde resins, polyacetylene derivatives, and a polymer compound selected from the group consisting of ethyl carbazole formaldehyde resin, and more becomes an organic semiconductor material. Further, fluorenone-based, diphenoquinone-based, benzoquinone-based, anthraquinone-based, and indenone-based compounds can also be used. As described above, since the material constituting the semiconductor is the organic semiconductor material, in the case of the polymer organic semiconductor material, the solution thereof can be formed into a film by a method such as a printing method or an inkjet method. Then, since it can be formed into a film by means such as a vacuum evaporation method, an extremely thin organic semiconductor layer can be formed at low cost.

The semiconductor layer may be made of an inorganic semiconductor material made of a metal oxide such as zinc oxide or tin oxide, or a composite oxide such as strontium titanate. As described above, since the inorganic semiconductor material can be formed by a method such as a vacuum vapor deposition method, an extremely thin inorganic semiconductor layer can be formed at low cost.

The first electrically insulating layer, the second electrically insulating layer and the third electrically insulating layer are made of polyvinyl alcohol,
It is composed of at least one material selected from the group consisting of an electrically insulating polymer having a hydroxyl group such as polyvinyl butyral, a phenol resin and a novolac resin, and an electrically insulating polymer having a cyano group such as polyacrylonitrile.

The first electrode layer, the second electrode layer and the third electrode layer
The electrode layers of are chromium (Cr), thallium (Ta), titanium (Ti), copper (Cu), aluminum (Al), molybdenum (Mo), tungsten (W), nickel (N).
i), gold (Au), palladium (Pd), platinum (P
t), silver (Ag), tin (Sn), conductive polyaniline,
It is made of at least one material selected from the group consisting of conductive polypyrrole, conductive polythiazyl, and conductive polymers.

The semiconductor device of the present invention is formed on the insulating substrate 11 and is effectively used as a vertical field effect transistor.

Manufacturing Example of Semiconductor Device of the Present Invention A semiconductor device (vertical field effect transistor) of the present invention is
As shown in FIGS. 6A to 6E, (a) a step (A) of forming the first electrode layer 1 (source electrode) on the substrate 11, (b) the first electrode layer A first electric insulating layer 4 (gate electric insulating film) standing vertically so as to come into contact with the right side wall of the first electrode, and a second electric insulating layer 6 standing so as to come into contact with the left side wall of the first electrode layer ( Element isolation electrical insulation film), and
From the right side wall of the first electrode layer 1 to the first electrical insulation layer 5
Step (B) of forming a third electric insulating layer 7 (element isolation electric insulating film) which is vertically stood apart by a width of (gate electric insulating film), and (c) the first electric insulating layer 4 (C) of forming the semiconductor layer 2 on the first electrode layer 1 between the second electric insulating layer 6 and the second electric insulating layer 6, (d) The first electric insulating layer 4 and the third electric insulating layer Step (D) of forming a third electrode layer 5 (gate electrode) on the substrate 11 between (7) and (7)
The step (E) of forming the second electrode layer 3 (drain electrode) on the semiconductor layer 2 between the electric insulating layer 4 and the second electric insulating layer 6 is sequentially performed. Note that FIG.
In (C), a is an active layer region, and b is a gate electrode region.

In the step (a), the first electrode layer 1
Is formed, for example, by forming gold (Au) on the glass substrate (11) by a well-known thin film forming method such as vapor deposition. In general, since the glass substrate and the Au film have poor adhesion, the adhesion layer is made of chromium (Cr), titanium (T
It is preferable to dispose a metal film such as i) or thallium (Ta). When an Au film is used, the alkanethiol-based organic material forms a self-regulating monomolecular adsorption film on the Au film surface.
The alkanethiol is transferred to a desired region of the Au film formed on the entire surface of the substrate, and then the exposed Au film is removed by wet etching to form an electrode pattern, that is, the first electrode. Form layer 1.

In the "microcontact printing method", as shown in FIGS. 5A to 5H, a step (a) of preparing a master (mainly a Si substrate) 21, a resist 22 on the master 21. Step (b) of covering the entire surface with the resist 2 by photolithography etching.
Step (c) of removing the desired portion 2 to form a pattern on the master 21, Step (d) of removing the remaining resist 22 (p) Pour polydimethylsiloxane (23) onto the master 21 on which the pattern is formed. A step (e) of heat-treating the same, a step (f) of peeling the heat-treated polydimethylsiloxane (23) from the master 21 to form a plate 23, and applying the alkanethiol ink 24 to the plate 23 thus formed. The step (g) and the step (h) of transferring the alkanethiol ink 24 onto the Au vapor deposition film formed on the substrate using the plate 23 inked with the alkanethiol ink 24 are sequentially performed.

The polydimethylsiloxane is a flexible resin, but if the conditions for transferring from the master pattern are optimized, the plate formed of this resin has a resolution of about 5 μm. The alkanethiol ink is applied to the plate thus formed and transferred to the Au vapor deposition film to form an alkanethiol self-regulating organized film.
In this textured film, Au and a thiol group are bound to each other and the alkyl groups are exposed on both sides. Therefore, when the Au vapor deposition film substrate is immersed in a polar solvent etching solution such as an iodine / ammonium iodide aqueous solution, Only the site without alkanethiol is etched (see the step (A) of the present invention). In conventional photolithography / etching, when compared with the method of obtaining a pattern film by sequentially performing resist coating, exposure, development, etching, and resist stripping each time, using such a “micro contact printing method”, A large amount of film can be processed simply by producing a plate, which is suitable for reducing the manufacturing cost.

In the step (b), preferably
After forming a photoresist film by spin-coating a photoresist, the first electric insulating layer 4 and the second electric insulating layer 6 are formed.
And the width of the third electric insulating layer 7 is exposed and developed to form the first electric insulating layer 4, the second electric insulating layer 6 and the third electric insulating layer 7. Such a first electric insulating layer 4, a second electric insulating layer 6 and a third electric insulating layer 7 are the first electrode layer 1, the semiconductor layer 2 and the third electric insulating layer 7 when manufacturing the semiconductor device of the present invention. The second electrode layer 3 effectively acts as a frame for sequentially forming the second electrode layer 3 in the vertical direction and as a frame for forming the third electrode layer 5 after the semiconductor device is formed. The first electric insulating layer 4 acts as an electric insulating film (gate electric insulating film), and the second electric insulating layer 6 and the third electric insulating layer 7 act as element isolation films. However, the second electric insulating layer 6 and the third electric insulating layer 7 may be removed after forming all the films, unless they are used as element isolation films.

The material of the first electric insulating film 4 is preferably one having a high relative dielectric constant in order to increase the C _ox expressed by the above formula (1). Organic materials are particularly preferable for such an electric insulating film because they are excellent in various processability. Introducing a naphthoquinonediazide UV photosensitive group into novolak resin,
So-called positive photoresists are preferable because they have a relatively high relative dielectric constant among organic materials. On the substrate 11,
After applying a photoresist and pre-baking, an exposure process, a development process, and a post-baking process are sequentially performed with a high-pressure mercury lamp to form these electrical insulating films. At this time, a UV cure treatment and a hard bake treatment at 280 ° C. or lower may be performed in order to prevent the resist film from being deteriorated in a subsequent step.

In the present invention, the above (c) is preferable.
In the step of, a solution of the polymer organic semiconductor material is formed into a film by a method such as an inkjet method, a letterpress printing method, an intaglio printing method, an offset printing method, a screen printing method, or a low molecular weight organic semiconductor material is vacuum deposited. A film is formed by a means such as a molecular beam deposition method to form a semiconductor layer. When the vacuum film formation method is used, an inorganic semiconductor material made of a metal oxide such as zinc oxide or tin oxide or a composite oxide such as strontium titanate can be formed.

In the present invention, preferably the above (a)
In the step (1), the step (d), and the step (e), the first electrode layer,
Whether the second electrode layer and the third electrode layer are formed by a solution of a polymer conductive material by a method such as a printing method, an inkjet method, a relief printing method, an intaglio printing method, an offset printing method, or a screen printing method. Alternatively, a metal is deposited by a method such as a vacuum evaporation method, an ion plating method, a sputtering method, or a plating method to form a first electrode layer, a second electrode layer, and a third electrode layer.

According to the method of manufacturing a semiconductor of the present invention, a current (Id) is caused to flow in a direction orthogonal to the surface of the substrate, and the first electrode layer is provided from the third electrode layer provided outside one of the active regions.
Since it is possible to manufacture a semiconductor device having a structure in which an electric field is applied to the semiconductor layer, that is, the semiconductor region via the electric insulating layer of, the thickness of the semiconductor layer (corresponding to the gate length L in the above formula (1)) can be reduced. The cost can be further reduced, and therefore, the gate length L can be shortened and a dramatically short channel length can be structurally realized without using photolithography processing. As a result, transistor performance, that is, execution The electric field mobility can be improved.

In the present invention, in the manufacture of a semiconductor device, a solution of an organic semiconductor material is applied between a pair of electrically insulating layers which are vertically provided on a substrate to apply an organic semiconductor layer and / or an inorganic semiconductor layer. And / or a conductive layer is formed.
As described above, when the organic semiconductor layer solution and / or the inorganic semiconductor and / or the conductive layer are formed by applying the solution of the organic semiconductor material between the pair of electrically insulating layers provided vertically on the substrate, the substrate Since the pair of electric insulating layers vertically provided on the above effectively acts as a mold for forming the organic semiconductor layer and / or the inorganic semiconductor and / or the conductive layer, the organic semiconductor layer and / or An inorganic semiconductor and / or a conductive layer can be formed at low cost.

[0053]

EXAMPLES Example 1 (1) A Cr film having a width of 30 nm was formed as an adhesion film on a glass substrate, and then an Au film having a thickness of 70 nm was formed on the Cr film.
The film was formed in the width. (2) Transfer using an alkane thiol ink inked plate on the Au film, and immerse the substrate in an etching solution composed of an iodine / ammonium iodide aqueous solution,
The first electrode layer (source electrode) was formed by etching the Au film and subsequently immersing this substrate in an aqueous nitric acid solution containing cerium ammonium nitrate to etch the Cr film. (3) Photoresist (OFPR80 manufactured by Tokyo Ohka Co., Ltd.)
0) is spin-coated on the substrate to form a resist film, and the resist film is exposed to light and developed into a desired pattern, and then post-baked and UV-cured to give the first electrode layer. A first electrically insulating layer (gate electrode) standing vertically so as to be in contact with the right side wall of the
A second electric insulating layer (element isolation electric insulating film) which is erected so as to be in contact with the left side wall of the electrode layer and a width of the first electric insulating layer 5 from the right side wall of the first electrode layer. A third electric insulating layer (element isolation electric insulating film) which was vertically stood was formed. At that time, the width of the active layer as the transistor operating portion was set to 200 μm. (4) Inkjet method as a solution of purified polyhexylthiophene (commercially available product) in chloroform on the first electrode layer 1 between the first and second electrical insulating layers. To form a semiconductor layer. At that time, since the organic semiconductor concentration was 0.5% by weight or less, it was possible to form a semiconductor layer having a thickness of about 100 nm or less. (5) Then, a conductive polymer solution (PEDOT manufactured by Bayer Co., Ltd.) is used on the substrate between the first electrically insulating layer and the third electrically insulating layer to form a third electrode layer (gate). Electrodes were formed to obtain a semiconductor device (vertical field effect transistor).

Comparative Example 1 A substrate made of a Si wafer doped with high concentration of boron was steam-oxidized to form a 100 nm thermal oxide film on the substrate, and then the thermal oxide film formed on the back surface of the substrate was removed. It was removed with an aqueous solution of hydrofluoric acid, and subsequently an Al electrode was formed on the substrate. Next, Au / Cr films were laminated as source / drain electrodes, and a pattern was formed on these films by photolithography etching. The dimensions of the transistor operating part are W = 20 μm and L =
It was 5 μm. Then, a semiconductor layer made of polyhexylthiophene was formed by spin coating to obtain a lateral field effect transistor.

The performance of the semiconductor device (vertical field effect transistor) obtained in Example 1 and the lateral field effect transistor obtained in Comparative Example 1 were tested. For the semiconductor device obtained in Example 1, a source / drain current of 5.6 μA was measured at a source / drain voltage of 20 V and a gate voltage of 20 V. On the other hand, the lateral field effect transistor obtained in Comparative Example 1 has
At a drain voltage of 20 V and a gate voltage of 20 V, a current value of 60 nA was measured as the source / drain current. When the field effect mobility was calculated based on the above formula (1), the current value of the semiconductor device obtained in Example 1 was equivalent to 2 × 10 ⁻⁴ cm ² / V · s. Therefore, it is understood that the semiconductor device (vertical field effect transistor) has a transistor performance improved about 100 times as compared with the conventional lateral field effect transistor.

[0056]

(1) According to the invention described in claims 1, 4, 5, 9 to 12, the semiconductor device causes the current (Id) to flow in the direction perpendicular to the surface of the substrate and activates it. Since the structure is such that an electric field is applied to the semiconductor layer, that is, the semiconductor region from the third electrode layer provided outside one of the regions through the first electrical insulating layer, the film thickness of the semiconductor layer ( (Corresponding to the gate length L in the above formula (1)) can be made even thinner. Therefore, the gate length L can be shortened and a dramatically short channel length can be structurally achieved without using photolithography. It can be realized, and as a result, the transistor performance, that is, the effective field mobility can be improved. Moreover, since the structure of the semiconductor device is simple, the manufacturing process can be simplified, and therefore, the manufacturing cost of the semiconductor device can be reduced.

(2) According to the invention described in claim 2, good electrical contact can be obtained between the first electrode layer and the second electrode layer and the semiconductor layer.

(3) According to the invention described in claims 3 and 6, the second electric insulating layer and the third electric insulating layer are effective for element isolation, and the present invention is also effective. When manufacturing a semiconductor device, the first electrode layer, the semiconductor layer and the second electrode layer are used as a mold for sequentially forming a film in the vertical direction, and for forming a third electrode layer. It works effectively as a formwork.

(4) According to the invention described in claims 7 and 8, since the material constituting the semiconductor is the organic semiconductor material and the inorganic semiconductor material, in the case of the polymer organic semiconductor material, the solution thereof is printed by a printing method, It can be formed into a film by a method such as an inkjet method, and can be formed into a film by a method such as a vacuum vapor deposition method for a low molecular weight organic semiconductor material, and can be formed with a vacuum vapor deposition method for an inorganic semiconductor material. Since the film can be formed by such means as described above, an extremely thin semiconductor layer can be formed at low cost.

(5) According to the invention described in claims 13 to 20, the semiconductor device allows a current (Id) to flow in a direction perpendicular to the surface of the substrate, and is provided outside one of the active regions. Since it is possible to manufacture a semiconductor device having a structure in which an electric field is applied from the third electrode layer to the semiconductor layer, that is, the semiconductor region via the first electrical insulating layer, the film thickness of the semiconductor layer (in the formula (1) above) (Corresponding to the gate length L) can be made thinner at low cost, and therefore, the gate length L can be shortened and a dramatically short channel length can be structurally realized without using photolithography. As a result, the transistor performance, that is, the effective electric field mobility can be improved.

(6) According to the invention as set forth in claim 21, a solution of an organic semiconductor material is applied between a pair of electric insulating layers provided upright on a substrate so as to form an organic semiconductor layer and an organic semiconductor layer. When the inorganic semiconductor and / or the conductive layer is formed,
Since the pair of electrical insulating layers vertically provided on the substrate effectively act as a mold for forming the organic semiconductor layer and / or the inorganic semiconductor and / or the conductive layer, the organic semiconductor layer and / or the organic semiconductor layer / Alternatively, the inorganic semiconductor and / or the conductive layer can be formed at low cost.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device showing an embodiment of the present invention.

FIG. 2 is a sectional view of a semiconductor device showing another embodiment of the present invention.

FIG. 3 is a sectional view of a semiconductor device showing another embodiment of the present invention.

FIG. 4 is an explanatory diagram for explaining electrical connection and operation for driving the semiconductor device of the present invention.

FIG. 5 is an explanatory diagram illustrating a manufacturing step for the semiconductor device according to the embodiment of the present invention.

FIG. 6 is an explanatory diagram for explaining a step of microcontact printing.

FIG. 7 is a thin film field effect transistor using a conventional inorganic material.

FIG. 8 is a thin film field effect transistor using a conventional organic material.

[Explanation of symbols]

1 First electrode layer (source electrode layer) 2 semiconductor layers 3 Second electrode layer (drain electrode layer) 4 First electrical insulation layer (gate electrical insulation layer) 5 Third electrode layer (gate electrode layer) 6 Second electrical insulation layer (element isolation electrical insulation layer) 7 Third electrical insulation layer (element isolation electrical insulation layer) 8,9 buffer layer 10 Active area 11 board

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Toshiya Kosaka             1-3-3 Nakamagome, Ota-ku, Tokyo Stocks             Company Ricoh (72) Inventor Takashi Okada             1-3-3 Nakamagome, Ota-ku, Tokyo Stocks             Company Ricoh (72) Inventor Masashi Torii             1-3-3 Nakamagome, Ota-ku, Tokyo Stocks             Company Ricoh (72) Inventor Shinichi Kawamura             1-3-3 Nakamagome, Ota-ku, Tokyo Stocks             Company Ricoh (72) Inventor Takanori Tano             1-3-3 Nakamagome, Ota-ku, Tokyo Stocks             Company Ricoh (72) Inventor Hiroshi Kondo             1-3-3 Nakamagome, Ota-ku, Tokyo Stocks             Company Ricoh (72) Inventor Hiroyuki Iechi             1-3-3 Nakamagome, Ota-ku, Tokyo Stocks             Company Ricoh F-term (reference) 5F110 AA01 AA16 CC09 DD02 EE01                       EE02 EE03 EE04 FF01 GG01                       GG04 GG05 GG41 GG42 HK01                       HK02 HK03 HK04 HK21 QQ06

Claims (21)

[Claims] 1. In a semiconductor device in which a first electrode layer, a semiconductor layer and a second electrode layer are sequentially stacked, a first device is provided upright in a vertical direction so as to be in contact with one side wall of these layers.
A semiconductor device having the electrical insulating layer and the third electrode layer in sequence. 2. The semiconductor device according to claim 1, further comprising a buffer layer between the first electrode layer and the semiconductor layer and / or between the semiconductor layer and the second electrode layer. 3. A second electrically insulating layer provided upright in a vertical direction so as to be in contact with the other side wall of the first electrode layer, the semiconductor layer and the second electrode layer, and the third electrode. The semiconductor device according to claim 1, further comprising a third electrically insulating layer provided in a vertical direction so as to be in contact with an outer sidewall of the layer. 4. The first electrode layer, the second electrode layer, and the third electrode layer are a source electrode layer, a drain electrode layer, and a gate electrode layer, respectively.
3. The semiconductor device according to any one of 3 above. 5. The semiconductor device according to claim 1, wherein the first electrically insulating layer is a gate electrically insulating layer. 6. The semiconductor device according to claim 1, wherein the second electrical insulation layer and the third electrical insulation layer are element isolation electrical insulation layers. 7. The acene molecular material, wherein the semiconductor layer is selected from the group consisting of naphthalene, anthracene, tetracene, pentacene, hexacene and derivatives thereof,
A pigment selected from the group consisting of phthalocyanine compounds, azo compounds and perylene compounds, and derivatives thereof,
Low molecular weight compounds selected from the group consisting of hydrazone compounds, triphenylmethane compounds, diphenylmethane compounds, stilbene compounds, aryl vinyl compounds, pyrazoline compounds, triphenylamine compounds, phenylene derivatives and triarylamine compounds, and derivatives thereof, or, Poly-N-vinylcarbazole, halogenated poly-N-vinylcarbazole, polyvinylpyrene, polyvinylanthracene, polythiophene derivative,
7. A polymer compound selected from the group consisting of a thiophene oligomer derivative, a pyrene formaldehyde resin, a polyacetylene derivative, and an ethylcarbazole formaldehyde resin, and an organic semiconductor material comprising the organic semiconductor material. The semiconductor device according to. 8. The semiconductor layer is made of an inorganic semiconductor material made of a metal oxide such as zinc oxide or tin oxide, or a composite oxide such as strontium titanate. The semiconductor device according to any one of 1. 9. The electrically insulating polymer, wherein the first electrically insulating layer, the second electrically insulating layer and the third electrically insulating layer have a hydroxyl group such as polyvinyl alcohol, polyvinyl butyral, a phenol resin and a novolac resin. 9. The semiconductor device according to claim 1, wherein the semiconductor device is made of at least one material selected from the group consisting of electrically insulating polymers having a cyano group such as polyacrylonitrile. 10. The first electrode layer, the second electrode layer and the third electrode layer are made of chromium (Cr), thallium (Ta),
Titanium (Ti), copper (Cu), aluminum (Al),
Molybdenum (Mo), tungsten (W), nickel (Ni), gold (Au), palladium (Pd), platinum (P
t), silver (Ag), tin (Sn), conductive polyaniline,
10. The semiconductor device according to claim 1, wherein the semiconductor device is made of at least one material selected from the group consisting of conductive polypyrrole, conductive polythiazyl, and conductive polymer. 11. The semiconductor device according to claim 1, wherein the semiconductor device is formed on an insulating substrate. 12. The semiconductor device according to claim 1, wherein the semiconductor device is a vertical field effect transistor. 13. (a) a step of forming a first electrode layer on a substrate; (b) a first electric insulating layer which is vertically erected so as to be in contact with a right side wall of the source electrode layer; A second electric insulating layer which is erected so as to contact the left side wall of the first electrode layer, and a third electric standing layer which is erected vertically apart from the right side wall of the first electrode layer by the width of the first electric insulating layer. Forming a semiconductor layer on the first electrode layer between the first electric insulating layer and the second electric insulating layer, and (d) Forming a third electrode layer on the substrate between the first electrical insulation layer and the third electrical insulation layer, (e) the first electrical insulation layer and the second electrical insulation layer And a step of forming a second electrode layer on the semiconductor layer between the step of and the step of forming a second electrode layer. 14. In the step (b), the photoresist is spin-coated to form a photoresist film, and then the first photoresist is formed.
To the widths of the electrically insulating layer, the second electrically insulating layer, and the third electrically insulating layer, and developing to form the first electrically insulating layer, the second electrically insulating layer, and the third electrically insulating layer. 14. The method of manufacturing a semiconductor device according to claim 13, wherein. 15. In the step (c), a solution of the polymer organic semiconductor material is formed into a film by means of an inkjet method, a relief printing method, an intaglio printing method, an offset printing method, a screen printing method, or the like, or The method for manufacturing a semiconductor device according to claim 13 or 14, wherein a low molecular organic semiconductor material is formed by a method such as a vacuum vapor deposition method or a molecular beam vapor deposition method to form a semiconductor layer. 16. The step (a), the step (d) and the step (e)
In the step of, the first electrode layer, the second electrode layer and the third electrode layer are printed with a solution of a polymer conductive material, an inkjet method, a relief printing method, an intaglio printing method, an offset printing method, a screen. The first electrode layer, the second electrode layer and the metal film are formed by a method such as a printing method or a metal is formed by a method such as a vacuum deposition method, an ion plating method, a sputtering method, and a plating method. The method for manufacturing a semiconductor device according to claim 13, wherein a third electrode layer is formed. 17. The first electrode layer, the second electrode layer, and the third electrode layer are a source electrode layer, a drain electrode layer, and a gate electrode layer, respectively.
17. The method for manufacturing a semiconductor device according to any one of 3 to 16. 18. The method of manufacturing a semiconductor device according to claim 13, wherein the first electrically insulating layer is a gate electrically insulating layer. 19. The method of manufacturing a semiconductor device according to claim 13, wherein the second electrically insulating layer and the third electrically insulating layer are element isolation electrically insulating layers. 20. The method of manufacturing a semiconductor device according to claim 13, wherein the semiconductor device is a vertical field effect transistor. 21. In the manufacture of a semiconductor device, a solution of an organic semiconductor material is applied between a pair of electrically insulating layers provided vertically on a substrate to form an organic semiconductor layer and / or an inorganic semiconductor and / or a conductive material. A method of manufacturing a semiconductor device, which comprises forming a layer.