TW201135879A - 3DIC architecture with interposer for bonding dies - Google Patents

3DIC architecture with interposer for bonding dies Download PDF

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Publication number
TW201135879A
TW201135879A TW100103852A TW100103852A TW201135879A TW 201135879 A TW201135879 A TW 201135879A TW 100103852 A TW100103852 A TW 100103852A TW 100103852 A TW100103852 A TW 100103852A TW 201135879 A TW201135879 A TW 201135879A
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TW
Taiwan
Prior art keywords
substrate
wafer
interconnect structure
integrated circuit
conductive
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TW100103852A
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English (en)
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TWI430406B (zh
Inventor
Hsien-Pin Hu
Chen-Hua Yu
Ming-Fa Chen
Jing-Cheng Lin
Jiun-Ren Lai
Yung-Chi Lin
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Taiwan Semiconductor Mfg
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Publication of TW201135879A publication Critical patent/TW201135879A/zh
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Publication of TWI430406B publication Critical patent/TWI430406B/zh

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    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Description

201135879 六、發明說明： 【發明所屬之技術領域】 本揭露書是有關於積體電路，且特別是有關於包含 中介層（interposers)之三維積體電路（three-dimensional integrated circuits，3DICs)及其形成方法。 【先前技術】 自從積體電路之發明起，半導體工業已經歷持續的 快速成長，這是由於各種電子元件（即，電晶體、二極體、 電阻元件、電容元件等）之整合密度的持續增進。佔最大 原因地，此整合密度之增進來自於最小特徵尺寸 (minimum feature size)的一再縮小化，其允許了更多元件 整合至所給予之晶片面積中。 這些整合增進實際上為實質二雉的，其中所整合之 元件所佔的體積實質於半導體晶圓之表面上。雖然，微 影製程之顯著的增進已於二維積體電路製作中造成相當 大的進步，但在二維中所能達到的密度有著物理限制。 這些限制其中之一為製造這些元件所需之最小尺寸。並 且，當更多的元件放進一晶片中時，需要更多複雜的設 計。另一附加限制係因為隨著元件數目之增加，元件間 之内連線的數目與長度隨之而顯著增加。當内連線之長 度與數目增加時，電路之電阻電容延遲（RC delay)與功率 損耗(power consumption)亦皆增加。 因而形成了三維積體電路（3DICs)，其中可堆疊兩晶 片，其於其中一晶片中形成有穿矽導電結構 0503^4945TWF/jychen 4 201135879 (through-silicon vias，TSVs)以將另一晶片連接至封裝基 * 板。穿石夕導電結構常常在前端製程（front-end-of-line， FEOL)(其中形成了元件，例如，電晶體)之後形成，且還 可能在後端製程（back-end-of-line，BEOL)(其中形成了内 連線結構）之後形成。這可能造成已形成之晶片的良率損 失。再者，既然穿矽導電結構是在積體電路形成之後才 形成，製造的流程時間亦會拉長。 • 【發明内容】 本發明一實施例提供一種積體電路元件，包括：一 中介層，大抵不具有積體電路元件，其中該中介層包括： 一基底，具有一第一側及相反於該第一側之一第二側； 複數個穿基底導電結構，位於該基底之中；一第一内連 線結構，位於該基底之該第一側上，且電性耦接至至少 一該些穿基底導電結構；以及一第二内連線結構，位於 該基底之該第二側上，且電性耦接至至少一該些穿基底 φ 導電結構；一第一晶片，接合於該第一内連線結構之上； 以及一第二晶片，接合於該第二内連線結構之上。 本發明一實施例提供一種積體電路元件，包括：一 中介層，大抵不具有積體電路元件，其中該中介層包括： 一基底，具有一第一側及相反於該第一側之一第二側； 複數個穿基底導電結構，位於該基底之中；一第一内連 線結構，位於該基底之該第一側上，且電性耦接至至少 一該些穿基底導電結構；以及一開口，位於該基底之中， 且鄰接至少一該些穿基底導電結構；一第一晶片，接合 0503^A34945TWF/jychei 5 201135879 形成於該 日片 於該第一内連線結構之上；以及一第，— 開口之中，且接合至該第一内連線結構之上 本發明一實施例提供一種積體電路元件的形成方 法，包括.提供一矽基底，大抵不具有積體電路元件； 肜成穿基底導電結構，自該石夕基底之一前側穿過該矽 基底至一預定深度；於該矽基底之該前側上形成一第一 内連線、、構’其中該第—内連線結構包括至少一介電層 =位於該至少-介電層中之金屬結構；將—第一晶片接 苐一内連線結構上；自該矽基底之-背側移除該 土底以使該穿基底導電結構之一端露出；於 ==形成:第二内連線結構，且該第二内連線結 ★竹筮以牙基底導電結構之該端；形成-開口， 二：連線結構及财基底，並到達該第-内連 面；以及將一第二晶片接合至該開口中之 該第一内連線結構的該表面上。 亦揭露其他實施例。 【實施方式】 以下將詳細說明本發明實施例之製作虛使 以應>主意的是，本發明提供 式 其可以多種特定型式眚尬 夕了供應用的發明概念， 例僅為製造與使用本發明之㈣論之特定實施 明之範圍。再者，當述及=非用以限制本發 層上或之上時，包括第— ^曰位於一第二材料 或間隔有一或更多其他材料層第直接接觸 月形。為了間單與清楚 〇503-A34945TWF/jychen 201135879 • 化，許多結構<能會繪成不同的尺寸。 ' 提供，雜新賴的三維積體電路（3DIC)及其形成方 法。將說明製造實施例之中間製程步驟。將討論實施例 之變化。在通篇的圖式與實施例中，相似的標號將用以 標示相似的元朴。 請參照第1A圖’提供基底10。在通篇說明中，基 底10及對應的内連線結構12及32(未顯示於第1A圖 中’請參照第1D圖）將共同稱作中介層晶圓（jnterp〇ser φ wafer)100。基底10可由半導體材料形成，例如矽、矽鍺、 碳化矽、砷化鎵、或其他常用的半導體材料。或者，基 底10係由介電材料形成。中介層晶圓100大抵不具有積 體電路元件，包含例如是電晶體及二極體之主動元件。 此外，中介層晶圓100可包括（或可不具有）例如是電容元 件、電阻元件、電感元件、變容元件（varactors)、及/或其 相似物之被動元件。 前側（front-side)内連線結構12係形成於基底之 _ 上。内連線結構12包括一或更多的介電層18及位於介 電層18中之金屬線路（metal丨匕以口4及介層窗（vias)16 〇 在通篇的欽述中’中介層晶圓100在第1A圖中朝上的一 側稱作别側’而朝下的一侧稱作背侧。金屬線路14及介 層 6 稱作如侧重佈線路（fr〇nt_side redistribution ♦ DLs) °再者，穿基底導電結構(thr0Ugh-sllbstrate τ=)2()係形成於基底10中至預定深度，且可能 牙過一些或全部的介電層18。穿基底導電結構20電性耦 接至前側重佈線路（14/16)。 0503--A34945TWF/jychen 7 201135879 接著’於中介層晶圓100之前側上形成前侧（金屬） 凸塊（或接墊）24 ’且其電性耦接至穿基底導電結構2〇及 重佈線路（14/16)。在一實施例中，前側金屬凸塊24為鮮 料凸塊（solder bumps)，例如共晶銲料凸塊（eutectic s〇lder bumps)。在另一實施例中，前侧金屬凸塊24為銅凸塊或 其他金屬凸塊，其可由金、銀、鎳、鎢、鋁、及/或前述 之合金而形成。前側金屬凸塊24可突出於内連線結構12 之表面。 請參照第1B圖’將晶片（ciies)22接合至前側金屬凸 塊24°晶片22可為包含積體電路元件之元件晶片，例如 包含電晶體、電容元件、電感元件、電阻元件（未顯示）、 及其相似物於其中。再者，晶片22可為包括核心電路（core circuit)之邏輯晶片’且可例如為中央處理單元（center processing unit ’ CPU)晶片。晶片22與前側金屬凸塊24 之間的接合可為銲料接合（s〇lder bonding)或直接金屬對 金屬接合（direct metal-to-metal bonding)，例如銅對銅接 合。作為替代地’晶片22係在背側内連線結構32(第ID 圖）形成之後才接合，之後將詳細討論。底膠23注入於晶 片.22與中介層晶圓1〇〇之間的間隔之中，並被固化。 請參照第1C圖，透過黏著層28將承載基板 (carrier)26(其可為玻璃晶圓，giass wafer)接合至中介層晶 圓100的前側之上。黏著層28可為紫外線膠(UV glue) 或可由其他所知的黏著材料形成。進行晶圓背侧研磨以 自背側薄化基底10直至穿基底導電結構20露出。可進 行蝕刻製程以進一步降低基底10之表面而使穿基底導電 0503/A34945TWF/jychen 8 201135879 結構20突出於基底10剩餘部分之背表面。 • 接著，如第1D及1E圖所示，形成背側内連線結構 32以連接穿基底導電結構20。在許多實施例中，背側内 連線結構32可具有相似於前側内連線結構12之結構， 而可包括金屬凸塊及一或更多層的重佈線路。例如，背 側内連線結構32可包括位於基底10上之介電層34，其 中介電層 34可為低溫聚醯亞胺層（low-temperature polyimide layer)或可由所週知的介電材料形成，例如旋塗 φ 玻璃（spin-on glass)、氧化石夕、氮氧化碎、或其相似物。 介電層34可使用化學氣相沉積（CVD)而形成。當使用低 溫聚醯亞胺層時，介電層34亦可用作應力緩衝層。如第 1E圖所示，接著形成凸塊下金屬層（UBM)36及背側金屬 凸塊38A。相似地，背侧金屬凸塊38A可為銲料凸塊， 例如共晶銲·料凸塊、銅凸塊、或其他由金、銀、鎳、鶴、 铭、及/或前述之合金所形成之金屬凸塊。在一實施例中， 凸塊下金屬層.36及背側金屬凸塊38A之形成可包括毯覆 • 式形成凸塊下金屬層、於凸塊下金屬層上形成遮罩，其 具有開口、於開口中電鍍背側金屬凸塊38A、移除遮罩、 及進行快速蝕刻以移除毯覆式凸塊下金屬層先前由遮罩 所覆蓋之部分。 請參照第1F圖，將晶片50接合至中介層晶圓100 的背側。晶片50可透過前側内連線結構12、背側内連線 結構32、及穿基底導電結構20而電性耦接至晶片22。 晶片22及晶片50可為不同型式之晶片。例如，晶片22 可為邏輯晶片，例如CPU晶片，而晶片50可為記憶體 一.. 0503^A34945TWF/jychen 9 201135879 晶片。 接著，如第1H圖所示，於中介層晶圓100的背側上 形成大凸塊38B，且其電性耦接至背側内連線結構32、 穿基底導電結構20、及可能的晶片22及50。大凸塊38B 可為鮮料凸塊，其例如由共晶銲料（eutectic solder)形成， 雖然它們亦可為其他型式的凸塊，例如金屬接點（metal bonds)。在其他實施例中，接合晶片50及形成大凸塊38B 之順序可顛倒。第1G圖顯示另一實施例，其中係先形成 大凸塊38B，接著接合晶片50以形成顯示於第1H圖中 之結構。在這些實施例中，凸塊38A(以下稱為小凸塊） 及大凸塊38B可使用單一步驟凸塊形成製程（one-step bump formation process)而同日夺形成。 在第II圖中，取下如第1H圖所示之承載基板26, 例如藉由對黏著層28(UV膠）照射紫外光而造成黏著層 28失去黏性。接著，將切割膠帶60貼合至最終結構之前 側。接著，沿著線62進行切割以將中介層晶圓100及接 合於中介層晶圓100上之晶片22及50分離成數個晶片。 在第II圖中，由於晶片50之存在，中介層晶圓100 之部分的背側不可用於形成大凸塊38B。然而，在顯示 於第2A-2D圖之其他實施例中，可形成更多的大凸塊 38B，這是因為一些大凸塊38B(如第2D圖所示，標示為 38B’）可形成作垂直對準並重疊於晶片50。簡要的製程流 程顯示於第2A-2D圖之中。此實施例之起始製程步驟可 實質上相同於第1A-1F圖所示者，其中形成了用以接合 晶片50之小凸塊38A，而這一次不形成大凸塊38B。接 0503-A34945TWF/jychen 10 201135879 著，如第2A圖所示，將晶片5〇接合至中介層晶圓1〇〇 • 之背侧。將底膠52填入晶片50與中介層晶圓1〇〇之間 的間隔之中，並接著將底膠52固化。 請參照第2B圖’將封裝化合物（m〇lding compound)54(或稱為封裝材料，encapSUiating material) 形成於晶片50及中介層晶圓丨〇〇之上。封裝化合物54 之頂表面可高於或等高於晶片50之頂表面。請參照第2C 圖，形成深介層窗（deep vias)56以穿過封裝化合物54， • 並電性耦接至背側内連線結構32。接著，形成内連線結 構58 ’其包括電性耦接至深介層窗56之重佈線路49， 並接著形成凸塊下金屬層（未標示）及大凸塊38B。再次， 可於凸塊下金屬層之下形成應力缓衝層，其可由聚醯亞 胺層或防銲層（solder resist)而形成。可發現一些大凸塊 38B(標作38B’)可直接形成於部分的晶片5〇之上，且與 部分的晶片50垂直重疊，因而大凸塊38B之數目可增加 至超出第II圖所示之結構。 • 在第2D圖中，取下承载基板26。接著，將切割膠 帶60貼合至最終結構之前側。接著，進行切割以將中介 層晶圓100及接合於中介層晶圓1〇〇上之晶片22及50 分離成複數個晶片。 第3A-3D圖顯示另一實施例，此實施例之起始製程 步驟可實質上相同於顯示於第1A-1F及第2A圖中者，其 中晶片50接合於中介層晶圓1〇〇之上。接著，如第3A 圖所示，將虛置晶圓（dummy wafer)66接合至中介層晶圓 100之上，其中虛置晶圓之材料亦稱為封裝材料 0503^A34945TWF/jychen 11 201135879 (encapsulating material)。在一實施例中，虛置晶圓66為 一虛置矽晶圓。在另一實施例中，虛置晶圓66由其他半 導體材料形成，例如碳化矽、砷化鎵、或其相似物。虛 置晶圓66可不具有積體電路元件（例如電容元件、電阻元 件、變容元件、電感元件、及/或電晶體）於其中。在又一 實施例中，虛置晶圓66可為介電材料晶圓（dielectric wafer)。空腔（cavities)68係形成於虛置晶圓66之中。虛 置晶圓66於中介層晶圓100上之接合可包括氧化物對氧 化物接合（〇xide-to-oxide bonding)。在一實施例中，在虛 置晶圓66接合至中介層晶圓100上之前，預先於虛置晶 圓66上形成氧化物層69，其可由氧化石夕（例如，熱氧化 物，thermal oxide)所形成，且氧化物層70可預先形成於 中介層晶圓100之上。接著，透過氧化物對氧化物接合 而將氧化物層69接合至氧化物層70之上。因此，晶片 50係藏置於空腔68之中，且最終結構之表面72是平坦 的。 接著，如第3B圖所示，形成穿基底導電結構（即， 深介層窗56)以穿過虛置晶圓66及氧化物層69及70,並 電性耦接至背側内連線結構32。接著，形成内連線結構 58，其包括電性耦接至深介層窗56之重佈線路49，並接 著形成凸塊下金屬層（未標示）及大凸塊38B。再次，大凸 塊38B包括凸塊38B’，其直接形成於晶片50之上，且 垂直重疊於晶片50。 在第3C圖中，將承載基板26取下。接著，將切割 膠帶60黏貼至最終結構之一側上。接著，進行切割以將 〇503^A34945TWF/jychen 12 201135879 中介層晶圓100及接合於中介層晶圓1〇 5〇分離成複數個晶片。 之曰曰片22及 第4A-4D圖顯示又一實施例，其中晶片％位於 2晶圓100中之空腔中。首先，形成顯示於第4A圖中之 結構’其中製程可實f上相同於如第ια·ιε圖所示者。 因此形成之細節在此不再討論。接著，如第4Β圖所示， :::層晶圓100中形成開口 74，例如可使用濕式蝕刻 Ϊ乾式_。其進行可藉由形成並®案化絲76,且接 者透過光阻76中之開口蝕刻中介層晶圓1〇〇。蝕刻可停 止:當蝕刻到前側内連線結構12時，或前側内連線結構 之邛分的金屬結構（metal features；)露出時。前側内連 線結構12中所露出的金屬結構可用作接塾（bGnd娜）。 在第4C圖中，將晶片5〇插入開口 ”中，並接人至 :側:人中之金屬結構之上。接合可為_ 金屬對金屬接合、或其相似接合。因此，晶片別可 輕接至W 22及？基底導f結構2()。接著，將底膠 80填入開口 74中之剩餘空間之中。 請參照第4D圖，形成大凸塊遍。在另一實施例中， ，^38!係形成於開口 74之形成(第4B圖)與晶片50 之别。在第4E圖中’黏貼切割膠帶60 ’且可將顯 不於第4Efflt之三維積體電路切割成個別的晶片。 在另貫施例中’在形成顯示於第圖之結構之 將封裝化合物54(第2B-2D圖）或虛置晶圓66(第 3A-3C圖）形成/接合於顯示於第4c圖之結構上，以及中 介層晶圓謂之相對於晶片22的相反側上。剩餘的製程 〇503-A34945TWF/jychen 13 201135879 步驟可相似於顯示於第2B_2D圖及第3a =:f討論。再者’在每-上述討論的實二因 之前或之後，將晶片22接合至中介岸 日日Θ 50之上，並可在形成大凸塊趣後接合。I層 在以上的實施例中，中介層晶圓⑽中 電結構20(例如參照帛1C圖）可具有相同的長度 實施例中’穿基底導電結構20可具有不同的長 形成具有不同長度之穿基底導電結構 Λ ' °月/照第5Α圖，提供中介層晶圓100之其麻 】〇，且内連線結構12係形成於基底1〇之上。= 構η包括凸塊下金屬層及凸塊（未標示）。接著，如第二 圖所不，將晶片22接合至中介層晶圓1〇〇之上，且 膠23注入晶片22與中介層晶圓100之間的間隔中，並 將底膠23固化。 j㈣Τ，並
Lit 5C圖，將承載基板26(其可為玻璃晶圓） 透過黏者層28而接合至中介層晶圓1〇〇之前側 晶圓背側研磨以自背側將基底1〇薄化至所需的厚度。接 著，形成穿基底導電結構開口（TS v 〇penings)(其由所示之 穿基底導電結構20所佔據）以穿過基底1〇。再者，穿美 底導電結構開π延伸進人介電層18，其用以形成内連ς 結構12。接著’於穿基底導電結構開口中填充金屬材料 以升/成穿基底導電結構2()’並形成用以電性隔離穿基底 導電結構20與基底1〇之介電層25。在最終結構中，（内 連線、（構12之）金屬結構如_柳包括金屬結構 88A及88B ’其中金屬結構88A相較於金屬結構剛埋 0503^A34945TWF/jychen 201135879 • ^較深的介電層18内部。在穿基底導電結構開口之形 ，金屬結構88A及88B可用作姓刻停止層，因而介 1 18之钱刻停止於不同的深度。因此，穿基底導電結 A之長度L1(第5D圖）大於穿基底導電結構2〇B之 長度L2。後續製程步驟可實f上相同於顯示^ 七 =中者，或實質相同於顯示於其他實施例中者（當合 時）。 ° 可發現在實施例中（例如，第U、2D、3C、及4ε圖广 中不需穿基底導電結構，雖然穿 ?導電.4疋可以形成於晶片22及5〇的。然而，晶 2及5G中之元件可電性輕接至大凸塊湖，並彼此 2輕接。在f知的三維積體電路中，穿基底導電結構 白、形成了 7C件晶片中之積體電路之後才形成。這造成 良率損失及封裝流程時間的增加。然而 ，件晶片…中不需穿基底導電結構二 ^因為於晶片22及5〇中形成穿基底導電結構時所可能 損失。再者，因為中介層晶圓1〇0及相應的 f基底導電結構可形成於晶片22及％已形成的時候， 所以流程時間可減少。 雖然本發明已以數·個較佳實施例揭露如上，然其並 ^用以限定本發明’任何所屬技術領域中具有通常知識 ，在不脫離本發明之精神和範圍内，#可作任 動與潤# ’因此本發明之保護範圍# ^ 範圍所界定者為準。 0503--A34945TWF/jychen 15 201135879 .【圖式簡單說明】 第1A-1I圖顯示根據本發明實施例製造三維積體電 路的製程剖面圖，复中曰y拉人从山人„ ，丨 第2A-2D圖顯示根據本發明實施例製造三維積體電 路的製程剖面圖’其中使用封裝化合物以形成用以形成 更多大凸塊之平坦表面。 第3A-3C圖顯示根據本發明實施例製造三維積體電 路的製程剖面圖’其中使用虛置矽晶圓以形成用以形成 更多大凸塊之平坦表面。 第4A-4E圖顯示根據本發明實施例製造三維積體電 路的製程剖面圖，其中一晶片位於中介層之開口之中。 第·5Α_5ϋ圖顯示根據本發明實施例製造三維積體電 路的製程剖面圖’其中中介層中之穿基底導電結構具有 不同的長度。 【主要元件符號說明】 10〜基底； 12、32、58〜内連線結構； 14〜金屬線路； 16〜介層窗； 18、25〜介電層； 20、20Α、20Β〜穿基底導電結構； 22、 50〜晶片； 23、 52、80〜底膠； 24〜前侧（金屬）凸塊（或接墊）； 〇503-A34945TWF/jychen 16 201135879 26〜承載基板， ' 28〜黏著層； 34〜介電層； 36〜凸塊下金屬層； 38〜背側金屬凸塊； 38A、38B、38B’〜凸塊； 49〜重佈線路； 54〜封裝化合物； • 56〜深介層窗； 60〜切割膠帶； 6 2〜線， 66〜虛置晶圓， 68〜空腔； 69、70〜氧化物層； 72〜表面； 74〜開口； φ 76〜光阻； 88、88A、88B〜金屬結構； 100〜中介層晶圓； LI、L2〜長度。 050>A34945TWF/jychen 17

Claims (1)

  1. 201135879 七、申請專利範圍： L 一種積體電路元件，包括： 層包括： 中介層，大抵不具有積體電路元件， 其中該中介 一基底’具有―第—側及相反於該第ϋ之-第二 複數個穿基底導電結構，位於該基底之中； -第-内連線結構，位於該基底之該第—側上且 電性耦接至至少一該些穿基底導電結構；以及 ί二内連線結構’位於該基底之該第二側上，且 電性耦接至至少一該些穿基底導電結構； 側； 一第 晶 片，接合於該第—㈣線結構之上；以及 一第二晶片’接合於該第二内連線結構之上。 2.如申請專利範圍第μ所述之積體電路元件，更 包枯· 該第二^材料’位於該第二内連線結構之上，且包圍 一導電介層窗’穿過該封I 第二内連線結構； 電性耦接至該 一第二内料結構，㈣該封 連接至該導電介層窗；以及 丁代上且電性 一凸塊，形成於該第三内 接至該導電介層窗。 相結構之上，且電性鶴 包括3:.如申請專利範圍第1項所述之積體電路元件，更 0503^A34945TWF/jychen 201135879 片之上；以及 晶 二^材料’位於該第—日日π上：以 ::腔申= 該封裝材料與該第二晶 包括 “專利範圍第3項所述之積體電路元件，更 第二内穿過該封裝材料’且電性耦接至該 帛二㈣線結構，位於該封裝材料之上，且電性 耦接至該導電介層窗；以及 接”^二形成於該第三内連線結構之上，且電性耦 接至該導電介層窗。 5.如巾π專利範㈣4項所述之龍電路元件，其 中該封裝材料包括一虛置矽基底。 如申作專利範圍第i項所述之積體電路元件，其 中該些穿基底導電結構具有不同的長度，且自該基底延 伸進入該第一内連線結構不同的深度。 7. 如申凊專利範圍第1項所述之積體電路元件，更 包括-銲料凸塊，位於該第二内連線結構之上且鄰接 該第二晶片。 8. 一種積體電路元件，包括： 一中介層，大抵不具有積體電路元件，其中該中介 層包括： 側； 一基底，具有一第一側及相反於該第一側之一第二 複數個穿基底導電結構，位於該基底之中； 一第一内連線結構，位於該基底之該第一侧上，且 0503-A34945TWF/jychen 19 201135879 電性麵接至至少—該些穿基底導電結構；以及 一開口，位於該基底之中，B抑私 底導電結構； _ +且鄰接至少-該些穿基 一第一晶 第 片’接合於該第-内連線結構之上；以及 W’形成於該開口之+，且接合至 内連線結構之上。 9.如巾請相_第8項所述之積體電路元件更
    j一第二内連線結構’位於該基底之該第二側之上， 且電性耦接至少一該些穿基底導電結構。 一種積體電路元件的形成方法，包括： &供石夕基底，大抵不具有積體電路元件； =成-穿基底導電結構，自财基底之—前侧穿過 該矽基底至一預定深度； 於該⑦基底之該前側上形成H連線結構，其 該第内連線結構包括至少_介電層及位於該至少一 介電層中之金屬結構；
    將一第一晶片接合至該第.一内連線結構上； 自該石夕基底之-背侧移除财基底以使該穿基底導 電結構之一端露出； 於該矽基底之該背側上形成一第二内連線結構，且 該第二内連線結構電性耦接至該穿基底導電結構之該 端； 、，形成一開口，穿過該第二内連線結構及該矽基底， 並到達該第一内連線結構之一表面；以及 將一第二晶片接合至該開口中之該第一内連線結構 〇503-A34945TWF/jychen 201135879 的該表面上。
    0503^A34945TWF/jychen
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