TW201135868A - Method of forming a semiconductor die - Google Patents

Method of forming a semiconductor die Download PDF

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Publication number
TW201135868A
TW201135868A TW099147016A TW99147016A TW201135868A TW 201135868 A TW201135868 A TW 201135868A TW 099147016 A TW099147016 A TW 099147016A TW 99147016 A TW99147016 A TW 99147016A TW 201135868 A TW201135868 A TW 201135868A
Authority
TW
Taiwan
Prior art keywords
die
grains
wafer
semiconductor
dies
Prior art date
Application number
TW099147016A
Other languages
English (en)
Chinese (zh)
Inventor
Gordon M Grivna
Michael J Seddon
Original Assignee
Semiconductor Components Ind
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Components Ind filed Critical Semiconductor Components Ind
Publication of TW201135868A publication Critical patent/TW201135868A/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/28—Configurations of stacked chips the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/811—Multiple chips on leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/137—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being directly on the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Dicing (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
TW099147016A 2010-01-18 2010-12-30 Method of forming a semiconductor die TW201135868A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/689,126 US8384231B2 (en) 2010-01-18 2010-01-18 Method of forming a semiconductor die

Publications (1)

Publication Number Publication Date
TW201135868A true TW201135868A (en) 2011-10-16

Family

ID=44268046

Family Applications (1)

Application Number Title Priority Date Filing Date
TW099147016A TW201135868A (en) 2010-01-18 2010-12-30 Method of forming a semiconductor die

Country Status (5)

Country Link
US (1) US8384231B2 (enExample)
JP (1) JP2011146718A (enExample)
KR (1) KR20110084836A (enExample)
CN (1) CN102130022A (enExample)
TW (1) TW201135868A (enExample)

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US9418894B2 (en) 2014-03-21 2016-08-16 Semiconductor Components Industries, Llc Electronic die singulation method
US9472458B2 (en) 2014-06-04 2016-10-18 Semiconductor Components Industries, Llc Method of reducing residual contamination in singulated semiconductor die
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US9337098B1 (en) 2015-08-14 2016-05-10 Semiconductor Components Industries, Llc Semiconductor die back layer separation method
US11342189B2 (en) 2015-09-17 2022-05-24 Semiconductor Components Industries, Llc Semiconductor packages with die including cavities and related methods
US11430746B2 (en) 2020-04-29 2022-08-30 Semiconductor Components Industries, Llc Multidie supports for reducing die warpage
US10529576B2 (en) * 2017-08-17 2020-01-07 Semiconductor Components Industries, Llc Multi-faced molded semiconductor package and related methods
US10319639B2 (en) 2017-08-17 2019-06-11 Semiconductor Components Industries, Llc Thin semiconductor package and related methods
US9991338B2 (en) 2015-09-17 2018-06-05 Semiconductor Components Industries, Llc Electronic device including a conductive structure surrounded by an insulating structure
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US11367619B2 (en) 2017-08-17 2022-06-21 Semiconductor Components Industries, Llc Semiconductor package electrical contacts and related methods
US11404276B2 (en) 2017-08-17 2022-08-02 Semiconductor Components Industries, Llc Semiconductor packages with thin die and related methods
US11404277B2 (en) 2017-08-17 2022-08-02 Semiconductor Components Industries, Llc Die sidewall coatings and related methods
US11393692B2 (en) 2017-08-17 2022-07-19 Semiconductor Components Industries, Llc Semiconductor package electrical contact structures and related methods
US11348796B2 (en) 2017-08-17 2022-05-31 Semiconductor Components Industries, Llc Backmetal removal methods
US10741487B2 (en) 2018-04-24 2020-08-11 Semiconductor Components Industries, Llc SOI substrate and related methods
US11361970B2 (en) 2017-08-17 2022-06-14 Semiconductor Components Industries, Llc Silicon-on-insulator die support structures and related methods
US12230502B2 (en) 2017-08-17 2025-02-18 Semiconductor Components Industries, Llc Semiconductor package stress balance structures and related methods
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Also Published As

Publication number Publication date
CN102130022A (zh) 2011-07-20
US8384231B2 (en) 2013-02-26
KR20110084836A (ko) 2011-07-26
JP2011146718A (ja) 2011-07-28
US20110175242A1 (en) 2011-07-21

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