TW201044555A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

Info

Publication number
TW201044555A
TW201044555A TW099108633A TW99108633A TW201044555A TW 201044555 A TW201044555 A TW 201044555A TW 099108633 A TW099108633 A TW 099108633A TW 99108633 A TW99108633 A TW 99108633A TW 201044555 A TW201044555 A TW 201044555A
Authority
TW
Taiwan
Prior art keywords
resin film
film
semiconductor device
thin film
forming
Prior art date
Application number
TW099108633A
Other languages
English (en)
Chinese (zh)
Inventor
Ichiro Mihara
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Publication of TW201044555A publication Critical patent/TW201044555A/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/129—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/497—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Pressure Sensors (AREA)
  • Measuring Fluid Pressure (AREA)
TW099108633A 2009-03-25 2010-03-24 Semiconductor device and manufacturing method thereof TW201044555A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009075277A JP2010232230A (ja) 2009-03-25 2009-03-25 半導体装置およびその製造方法

Publications (1)

Publication Number Publication Date
TW201044555A true TW201044555A (en) 2010-12-16

Family

ID=42772157

Family Applications (1)

Application Number Title Priority Date Filing Date
TW099108633A TW201044555A (en) 2009-03-25 2010-03-24 Semiconductor device and manufacturing method thereof

Country Status (4)

Country Link
US (1) US8278734B2 (enExample)
JP (1) JP2010232230A (enExample)
CN (1) CN101847610B (enExample)
TW (1) TW201044555A (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5758605B2 (ja) 2010-09-30 2015-08-05 株式会社テラプローブ 半導体装置及びその製造方法
US9219106B2 (en) * 2011-08-05 2015-12-22 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated inductor
US8952530B2 (en) * 2012-09-14 2015-02-10 Taiwan Semiconductor Manufacturing Company, Ltd. Post passivation interconnect structures and methods for forming the same
JP6038280B2 (ja) * 2013-03-08 2016-12-07 三菱電機株式会社 半導体装置および半導体装置の製造方法
DE102017210654B4 (de) 2017-06-23 2022-06-09 Infineon Technologies Ag Elektronische Vorrichtung, die ein einen Hohlraum umfassendes Umverdrahtungsschicht-Pad umfasst
US12476228B2 (en) 2022-08-25 2025-11-18 Qualcomm Incorporated Wafer level packaging process for thin film inductors

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3465617B2 (ja) * 1999-02-15 2003-11-10 カシオ計算機株式会社 半導体装置
JP3540729B2 (ja) * 2000-08-11 2004-07-07 沖電気工業株式会社 半導体装置および半導体装置の製造方法
JP3615206B2 (ja) * 2001-11-15 2005-02-02 富士通株式会社 半導体装置の製造方法
JP3871609B2 (ja) 2002-05-27 2007-01-24 松下電器産業株式会社 半導体装置及びその製造方法
JP4341249B2 (ja) 2003-01-15 2009-10-07 セイコーエプソン株式会社 半導体装置の製造方法
JP2006041357A (ja) * 2004-07-29 2006-02-09 Fujikura Ltd 半導体装置およびその製造方法
SG119329A1 (en) * 2004-07-29 2006-02-28 Fujikura Ltd Semiconductor device and method for manufacturing the same
JP2008210828A (ja) * 2007-02-23 2008-09-11 Casio Comput Co Ltd 半導体装置およびその製造方法

Also Published As

Publication number Publication date
JP2010232230A (ja) 2010-10-14
CN101847610B (zh) 2012-12-19
US20100244188A1 (en) 2010-09-30
US8278734B2 (en) 2012-10-02
CN101847610A (zh) 2010-09-29

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