CN101847610B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN101847610B
CN101847610B CN201010143224XA CN201010143224A CN101847610B CN 101847610 B CN101847610 B CN 101847610B CN 201010143224X A CN201010143224X A CN 201010143224XA CN 201010143224 A CN201010143224 A CN 201010143224A CN 101847610 B CN101847610 B CN 101847610B
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CN
China
Prior art keywords
resin film
film
semiconductor device
connection pad
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201010143224XA
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English (en)
Chinese (zh)
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CN101847610A (zh
Inventor
三原一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
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Casio Computer Co Ltd
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Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Publication of CN101847610A publication Critical patent/CN101847610A/zh
Application granted granted Critical
Publication of CN101847610B publication Critical patent/CN101847610B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227Inductive arrangements or effects of, or between, wiring layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0236Shape of the insulating layers therebetween
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/024Material of the insulating layers therebetween
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/94Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/94Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Pressure Sensors (AREA)
  • Measuring Fluid Pressure (AREA)
CN201010143224XA 2009-03-25 2010-03-24 半导体装置及其制造方法 Expired - Fee Related CN101847610B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP075277/2009 2009-03-25
JP2009075277A JP2010232230A (ja) 2009-03-25 2009-03-25 半導体装置およびその製造方法

Publications (2)

Publication Number Publication Date
CN101847610A CN101847610A (zh) 2010-09-29
CN101847610B true CN101847610B (zh) 2012-12-19

Family

ID=42772157

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201010143224XA Expired - Fee Related CN101847610B (zh) 2009-03-25 2010-03-24 半导体装置及其制造方法

Country Status (4)

Country Link
US (1) US8278734B2 (enExample)
JP (1) JP2010232230A (enExample)
CN (1) CN101847610B (enExample)
TW (1) TW201044555A (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5758605B2 (ja) 2010-09-30 2015-08-05 株式会社テラプローブ 半導体装置及びその製造方法
US9219106B2 (en) * 2011-08-05 2015-12-22 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated inductor
US8952530B2 (en) * 2012-09-14 2015-02-10 Taiwan Semiconductor Manufacturing Company, Ltd. Post passivation interconnect structures and methods for forming the same
US10157865B2 (en) * 2013-03-08 2018-12-18 Mitsubishi Electric Corporation Semiconductor device with metal film and method for manufacturing semiconductor device with metal film
DE102017210654B4 (de) 2017-06-23 2022-06-09 Infineon Technologies Ag Elektronische Vorrichtung, die ein einen Hohlraum umfassendes Umverdrahtungsschicht-Pad umfasst
US12476228B2 (en) 2022-08-25 2025-11-18 Qualcomm Incorporated Wafer level packaging process for thin film inductors

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1420527A (zh) * 2001-11-15 2003-05-28 富士通株式会社 半导体器件的制造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3465617B2 (ja) * 1999-02-15 2003-11-10 カシオ計算機株式会社 半導体装置
JP3540729B2 (ja) * 2000-08-11 2004-07-07 沖電気工業株式会社 半導体装置および半導体装置の製造方法
JP3871609B2 (ja) * 2002-05-27 2007-01-24 松下電器産業株式会社 半導体装置及びその製造方法
JP4341249B2 (ja) * 2003-01-15 2009-10-07 セイコーエプソン株式会社 半導体装置の製造方法
JP2006041357A (ja) * 2004-07-29 2006-02-09 Fujikura Ltd 半導体装置およびその製造方法
SG119329A1 (en) * 2004-07-29 2006-02-28 Fujikura Ltd Semiconductor device and method for manufacturing the same
JP2008210828A (ja) * 2007-02-23 2008-09-11 Casio Comput Co Ltd 半導体装置およびその製造方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1420527A (zh) * 2001-11-15 2003-05-28 富士通株式会社 半导体器件的制造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
JP特开2008-210828A 2008.09.11

Also Published As

Publication number Publication date
JP2010232230A (ja) 2010-10-14
TW201044555A (en) 2010-12-16
CN101847610A (zh) 2010-09-29
US8278734B2 (en) 2012-10-02
US20100244188A1 (en) 2010-09-30

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SE01 Entry into force of request for substantive examination
C53 Correction of patent of invention or patent application
CB02 Change of applicant information

Address after: Tokyo, Japan, Japan

Applicant after: Casio Computer Co Ltd

Address before: Tokyo, Japan, Japan

Applicant before: CASIO Computer Co., Ltd.

COR Change of bibliographic data

Free format text: CORRECT: APPLICANT; FROM: CASIO COMPUTER CO., LTD. TO: ZHAOZHUANGWEI CO., LTD.

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Granted publication date: 20121219

Termination date: 20150324

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