CN101847610B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

Info

Publication number
CN101847610B
CN101847610B CN201010143224XA CN201010143224A CN101847610B CN 101847610 B CN101847610 B CN 101847610B CN 201010143224X A CN201010143224X A CN 201010143224XA CN 201010143224 A CN201010143224 A CN 201010143224A CN 101847610 B CN101847610 B CN 101847610B
Authority
CN
China
Prior art keywords
resin film
film
semiconductor device
connection pad
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201010143224XA
Other languages
English (en)
Chinese (zh)
Other versions
CN101847610A (zh
Inventor
三原一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Publication of CN101847610A publication Critical patent/CN101847610A/zh
Application granted granted Critical
Publication of CN101847610B publication Critical patent/CN101847610B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/129—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/497—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Pressure Sensors (AREA)
  • Measuring Fluid Pressure (AREA)
CN201010143224XA 2009-03-25 2010-03-24 半导体装置及其制造方法 Expired - Fee Related CN101847610B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP075277/2009 2009-03-25
JP2009075277A JP2010232230A (ja) 2009-03-25 2009-03-25 半導体装置およびその製造方法

Publications (2)

Publication Number Publication Date
CN101847610A CN101847610A (zh) 2010-09-29
CN101847610B true CN101847610B (zh) 2012-12-19

Family

ID=42772157

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201010143224XA Expired - Fee Related CN101847610B (zh) 2009-03-25 2010-03-24 半导体装置及其制造方法

Country Status (4)

Country Link
US (1) US8278734B2 (enExample)
JP (1) JP2010232230A (enExample)
CN (1) CN101847610B (enExample)
TW (1) TW201044555A (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5758605B2 (ja) 2010-09-30 2015-08-05 株式会社テラプローブ 半導体装置及びその製造方法
US9219106B2 (en) * 2011-08-05 2015-12-22 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated inductor
US8952530B2 (en) * 2012-09-14 2015-02-10 Taiwan Semiconductor Manufacturing Company, Ltd. Post passivation interconnect structures and methods for forming the same
JP6038280B2 (ja) * 2013-03-08 2016-12-07 三菱電機株式会社 半導体装置および半導体装置の製造方法
DE102017210654B4 (de) 2017-06-23 2022-06-09 Infineon Technologies Ag Elektronische Vorrichtung, die ein einen Hohlraum umfassendes Umverdrahtungsschicht-Pad umfasst
US12476228B2 (en) 2022-08-25 2025-11-18 Qualcomm Incorporated Wafer level packaging process for thin film inductors

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1420527A (zh) * 2001-11-15 2003-05-28 富士通株式会社 半导体器件的制造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3465617B2 (ja) * 1999-02-15 2003-11-10 カシオ計算機株式会社 半導体装置
JP3540729B2 (ja) * 2000-08-11 2004-07-07 沖電気工業株式会社 半導体装置および半導体装置の製造方法
JP3871609B2 (ja) 2002-05-27 2007-01-24 松下電器産業株式会社 半導体装置及びその製造方法
JP4341249B2 (ja) 2003-01-15 2009-10-07 セイコーエプソン株式会社 半導体装置の製造方法
JP2006041357A (ja) * 2004-07-29 2006-02-09 Fujikura Ltd 半導体装置およびその製造方法
SG119329A1 (en) * 2004-07-29 2006-02-28 Fujikura Ltd Semiconductor device and method for manufacturing the same
JP2008210828A (ja) * 2007-02-23 2008-09-11 Casio Comput Co Ltd 半導体装置およびその製造方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1420527A (zh) * 2001-11-15 2003-05-28 富士通株式会社 半导体器件的制造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
JP特开2008-210828A 2008.09.11

Also Published As

Publication number Publication date
JP2010232230A (ja) 2010-10-14
TW201044555A (en) 2010-12-16
US20100244188A1 (en) 2010-09-30
US8278734B2 (en) 2012-10-02
CN101847610A (zh) 2010-09-29

Similar Documents

Publication Publication Date Title
US8097941B2 (en) Semiconductor device having projecting electrode formed by electrolytic plating, and manufacturing method thereof
JP5249080B2 (ja) 半導体装置
US20070170566A1 (en) Semiconductor Device and Method of Manufacturing the Same, Circuit Board, and Electronic Instrument
CN101847610B (zh) 半导体装置及其制造方法
CN207800597U (zh) 半导体装置
JP5385452B2 (ja) 半導体装置の製造方法
JP2012009508A (ja) 半導体装置およびその製造方法
JP2004158758A (ja) 半導体装置およびその製造方法
CN101281908A (zh) 具有薄膜电路元件的半导体装置
JP2010056266A (ja) 半導体装置の製造方法
TWI445145B (zh) 半導體裝置及其製造方法
JP2008210828A (ja) 半導体装置およびその製造方法
KR20100093357A (ko) 웨이퍼 레벨 칩스케일 패키지
JP3915670B2 (ja) 半導体装置およびその製造方法
KR101074894B1 (ko) 배선의 접속 패드부보다 큰 평면 사이즈를 갖는 주상전극을 구비한 반도체 장치 및 그 제조방법
JP4747508B2 (ja) 半導体装置
JP5137320B2 (ja) 半導体装置およびその製造方法
JP2008047732A (ja) 半導体装置及びその製造方法
JP2004172163A (ja) 半導体装置及びその製造方法
JP2005093931A (ja) 半導体装置
JP2011014843A (ja) 半導体装置およびその製造方法
JP2011034988A (ja) 半導体装置
JP2009049306A (ja) 半導体装置
JP2011199130A (ja) 半導体装置およびその製造方法
JP2010062176A (ja) 半導体装置およびその製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C53 Correction of patent of invention or patent application
CB02 Change of applicant information

Address after: Tokyo, Japan, Japan

Applicant after: Casio Computer Co Ltd

Address before: Tokyo, Japan, Japan

Applicant before: CASIO Computer Co., Ltd.

COR Change of bibliographic data

Free format text: CORRECT: APPLICANT; FROM: CASIO COMPUTER CO., LTD. TO: ZHAOZHUANGWEI CO., LTD.

C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20121219

Termination date: 20150324

EXPY Termination of patent right or utility model